diff options
| author | joshua <joshua@fedora.framework> | 2022-05-14 23:30:38 -0500 |
|---|---|---|
| committer | joshua <joshua@fedora.framework> | 2022-05-14 23:30:38 -0500 |
| commit | b8936029065835366e9e057a219c0c5194db8662 (patch) | |
| tree | 31e50944ac6e23850f92bb0e0f6d851b74307f60 | |
| parent | d6b7d26cf51b4b3a7b5604f9b81bb43f55cbc33c (diff) | |
| download | riscv-processor-inorder-b8936029065835366e9e057a219c0c5194db8662.tar.gz | |
Verilog update
107 files changed, 31805 insertions, 77 deletions
diff --git a/ddr3demo.pdf b/ddr3demo.pdf Binary files differdeleted file mode 100644 index 24c9089..0000000 --- a/ddr3demo.pdf +++ /dev/null diff --git a/isa.pdf b/isa.pdf Binary files differdeleted file mode 100644 index 533c1cb..0000000 --- a/isa.pdf +++ /dev/null diff --git a/isalist.pdf b/isalist.pdf Binary files differdeleted file mode 100644 index f5d2c53..0000000 --- a/isalist.pdf +++ /dev/null diff --git a/privileged.pdf b/privileged.pdf Binary files differdeleted file mode 100644 index 2303a01..0000000 --- a/privileged.pdf +++ /dev/null diff --git a/ramcontroller.pdf b/ramcontroller.pdf Binary files differdeleted file mode 100644 index da8e3e5..0000000 --- a/ramcontroller.pdf +++ /dev/null diff --git a/riscv-card.pdf b/riscv-card.pdf Binary files differdeleted file mode 100644 index 2286ca6..0000000 --- a/riscv-card.pdf +++ /dev/null diff --git a/verilog/alu/LUTS b/verilog/alu/LUTS new file mode 100644 index 0000000..94ec7ce --- /dev/null +++ b/verilog/alu/LUTS @@ -0,0 +1,95 @@ +=== alu V1 === + + Number of wires: 1965 + Number of wire bits: 2876 + Number of public wires: 1965 + Number of public wire bits: 2876 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 2269 + CCU2C 32 + L6MUX21 339 + LUT4 1339 + PFUMX 559 + + +=== alu V2 === + + Number of wires: 2094 + Number of wire bits: 3031 + Number of public wires: 2094 + Number of public wire bits: 3031 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 2386 + CCU2C 32 + L6MUX21 374 + LUT4 1385 + PFUMX 595 + + +=== alu3 === + + Number of wires: 2006 + Number of wire bits: 3043 + Number of public wires: 2006 + Number of public wire bits: 3043 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 2317 + CCU2C 48 + L6MUX21 356 + LUT4 1346 + PFUMX 567 + + +=== alu V4 === + + Number of wires: 1746 + Number of wire bits: 2619 + Number of public wires: 1746 + Number of public wire bits: 2619 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 2042 + CCU2C 32 + L6MUX21 297 + LUT4 1218 + PFUMX 495 + + + +=== alu V5 === + + Number of wires: 1728 + Number of wire bits: 2635 + Number of public wires: 1728 + Number of public wire bits: 2635 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 2039 + CCU2C 32 + L6MUX21 295 + LUT4 1223 + PFUMX 489 + + +=== alu6 === + + Number of wires: 871 + Number of wire bits: 1857 + Number of public wires: 871 + Number of public wire bits: 1857 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 1183 + CCU2C 48 + L6MUX21 109 + LUT4 778 + PFUMX 248 diff --git a/verilog/alu/alu.v b/verilog/alu/alu.v deleted file mode 100644 index 3a4213a..0000000 --- a/verilog/alu/alu.v +++ /dev/null @@ -1,26 +0,0 @@ -`include "aluOp.vh" - -module riscv_alu -( -input wire [31:0] alu_in_1, -input wire[31:0] alu_in_2, -input wire[3:0] alu_op_i, -output wire[31:0] alu_output -); - - -wire diff = alu_in_1 - alu_in_2; -wire ones = 32'hFFFFFFFF; - -assign alu_output = alu_op_i == ADD ? alu_in_1 + alu_in_2 : - alu_op_i == SUB ? diff : - alu_op_i == XOR ? alu_in_1 ^ alu_in_2 : - alu_op_i == OR ? alu_in_1 | alu_in_2 : - alu_op_i == AND ? alu_in_1 & alu_in_2 : - alu_op_i == SLL ? alu_in_1 << alu_in_2 : - alu_op_i == SRL ? alu_in_1 >> alu_in_2 : - alu_op_i == SLT ? (alu_in_1 < alu_in_2 ? 32'b1 : 32'b0) : - alu_op_i == NONE ? alu_in_1 : 32'b0 : - alu_op_i == SLTU ? (alu_in_1[31] == alu_in_2[31] ? (diff[31] == 0 ? 0 : 1) : (alu_in_1[31] == 1 ? 1 : 0) ) : - alu_op_i == SRA ? alu_in_1[31] == 0 ? alu_in_1 >> alu_in_2 : ; -endmodule diff --git a/verilog/alu/backup/alu2.dot b/verilog/alu/backup/alu2.dot new file mode 100644 index 0000000..ae04559 --- /dev/null +++ b/verilog/alu/backup/alu2.dot @@ -0,0 +1,179 @@ +digraph "alu" { +label="alu"; +rankdir="LR"; +remincross=true; +n37 [ shape=diamond, label="result", color="black", fontcolor="black" ]; +n38 [ shape=diamond, label="diff", color="black", fontcolor="black" ]; +n39 [ shape=octagon, label="alu_output", color="black", fontcolor="black" ]; +n40 [ shape=octagon, label="alu_op_i", color="black", fontcolor="black" ]; +n41 [ shape=octagon, label="alu_in_2", color="black", fontcolor="black" ]; +n42 [ shape=octagon, label="alu_in_1", color="black", fontcolor="black" ]; +c46 [ shape=record, label="{{<p43> A|<p44> B}|$35\n$or|{<p45> Y}}" ]; +v0 [ label="0" ]; +c48 [ shape=record, label="{{<p43> A|<p44> B|<p47> S}|$34\n$mux|{<p45> Y}}" ]; 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+} + +//============================================================ +// Evaluation loop + +void Valu___024root___eval_initial(Valu___024root* vlSelf); +void Valu___024root___eval_settle(Valu___024root* vlSelf); +void Valu___024root___eval(Valu___024root* vlSelf); +#ifdef VL_DEBUG +void Valu___024root___eval_debug_assertions(Valu___024root* vlSelf); +#endif // VL_DEBUG +void Valu___024root___final(Valu___024root* vlSelf); + +static void _eval_initial_loop(Valu__Syms* __restrict vlSymsp) { + vlSymsp->__Vm_didInit = true; + Valu___024root___eval_initial(&(vlSymsp->TOP)); + // Evaluate till stable + vlSymsp->__Vm_activity = true; + do { + VL_DEBUG_IF(VL_DBG_MSGF("+ Initial loop\n");); + Valu___024root___eval_settle(&(vlSymsp->TOP)); + Valu___024root___eval(&(vlSymsp->TOP)); + } while (0); +} + +void Valu::eval_step() { + VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate Valu::eval_step\n"); ); +#ifdef VL_DEBUG + // Debug assertions + Valu___024root___eval_debug_assertions(&(vlSymsp->TOP)); +#endif // VL_DEBUG + // Initialize + if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp); + // Evaluate till stable + vlSymsp->__Vm_activity = true; + do { + VL_DEBUG_IF(VL_DBG_MSGF("+ Clock loop\n");); + Valu___024root___eval(&(vlSymsp->TOP)); + } while (0); + // Evaluate cleanup +} + +//============================================================ +// Utilities + +VerilatedContext* Valu::contextp() const { + return vlSymsp->_vm_contextp__; +} + +const char* Valu::name() const { + return vlSymsp->name(); +} + +//============================================================ +// Invoke final blocks + +VL_ATTR_COLD void Valu::final() { + Valu___024root___final(&(vlSymsp->TOP)); +} + +//============================================================ +// Trace configuration + +void Valu___024root__trace_init_top(Valu___024root* vlSelf, VerilatedVcd* tracep); + +VL_ATTR_COLD static void trace_init(void* voidSelf, VerilatedVcd* tracep, uint32_t code) { + // Callback from tracep->open() + Valu___024root* const __restrict vlSelf VL_ATTR_UNUSED = static_cast<Valu___024root*>(voidSelf); + Valu__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; + if (!vlSymsp->_vm_contextp__->calcUnusedSigs()) { + VL_FATAL_MT(__FILE__, __LINE__, __FILE__, + "Turning on wave traces requires Verilated::traceEverOn(true) call before time 0."); + } + vlSymsp->__Vm_baseCode = code; + tracep->scopeEscape(' '); + tracep->pushNamePrefix(std::string{vlSymsp->name()} + ' '); + Valu___024root__trace_init_top(vlSelf, tracep); + tracep->popNamePrefix(); + tracep->scopeEscape('.'); +} + +VL_ATTR_COLD void Valu___024root__trace_register(Valu___024root* vlSelf, VerilatedVcd* tracep); + +VL_ATTR_COLD void Valu::trace(VerilatedVcdC* tfp, int levels, int options) { + if (false && levels && options) {} // Prevent unused + tfp->spTrace()->addInitCb(&trace_init, &(vlSymsp->TOP)); + Valu___024root__trace_register(&(vlSymsp->TOP), tfp->spTrace()); +} diff --git a/verilog/alu/obj_dir/Valu.h b/verilog/alu/obj_dir/Valu.h new file mode 100644 index 0000000..57738b5 --- /dev/null +++ b/verilog/alu/obj_dir/Valu.h @@ -0,0 +1,73 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Primary model header +// +// This header should be included by all source files instantiating the design. +// The class here is then constructed to instantiate the design. +// See the Verilator manual for examples. + +#ifndef VERILATED_VALU_H_ +#define VERILATED_VALU_H_ // guard + +#include "verilated.h" + +class Valu__Syms; +class Valu___024root; +class VerilatedVcdC; + +// This class is the main interface to the Verilated model +class Valu VL_NOT_FINAL { + private: + // Symbol table holding complete model state (owned by this class) + Valu__Syms* const vlSymsp; + + public: + + // PORTS + // The application code writes and reads these signals to + // propagate new values into/out from the Verilated model. + VL_IN8(&op,3,0); + VL_IN(&in1,31,0); + VL_IN(&in2,31,0); + VL_OUT(&out,31,0); + + // CELLS + // Public to allow access to /* verilator public */ items. + // Otherwise the application code can consider these internals. + + // Root instance pointer to allow access to model internals, + // including inlined /* verilator public_flat_* */ items. + Valu___024root* const rootp; + + // CONSTRUCTORS + /// Construct the model; called by application code + /// If contextp is null, then the model will use the default global context + /// If name is "", then makes a wrapper with a + /// single model invisible with respect to DPI scope names. + explicit Valu(VerilatedContext* contextp, const char* name = "TOP"); + explicit Valu(const char* name = "TOP"); + /// Destroy the model; called (often implicitly) by application code + virtual ~Valu(); + private: + VL_UNCOPYABLE(Valu); ///< Copying not allowed + + public: + // API METHODS + /// Evaluate the model. Application must call when inputs change. + void eval() { eval_step(); } + /// Evaluate when calling multiple units/models per time step. + void eval_step(); + /// Evaluate at end of a timestep for tracing, when using eval_step(). + /// Application must call after all eval() and before time changes. + void eval_end_step() {} + /// Simulation complete, run final blocks. Application must call on completion. + void final(); + /// Trace signals in the model; called by application code + void trace(VerilatedVcdC* tfp, int levels, int options = 0); + /// Return current simulation context for this model. + /// Used to get to e.g. simulation time via contextp()->time() + VerilatedContext* contextp() const; + /// Retrieve name of this model instance (as passed to constructor). + const char* name() const; +} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES); + +#endif // guard diff --git a/verilog/alu/obj_dir/Valu.mk b/verilog/alu/obj_dir/Valu.mk new file mode 100644 index 0000000..15a2c2f --- /dev/null +++ b/verilog/alu/obj_dir/Valu.mk @@ -0,0 +1,68 @@ +# Verilated -*- Makefile -*- +# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable +# +# Execute this makefile from the object directory: +# make -f Valu.mk + +default: Valu + +### Constants... +# Perl executable (from $PERL) +PERL = perl +# Path to Verilator kit (from $VERILATOR_ROOT) +VERILATOR_ROOT = /usr/share/verilator +# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE) +SYSTEMC_INCLUDE ?= +# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR) +SYSTEMC_LIBDIR ?= + +### Switches... +# C++ code coverage 0/1 (from --prof-c) +VM_PROFC = 0 +# SystemC output mode? 0/1 (from --sc) +VM_SC = 0 +# Legacy or SystemC output mode? 0/1 (from --sc) +VM_SP_OR_SC = $(VM_SC) +# Deprecated +VM_PCLI = 1 +# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH) +VM_SC_TARGET_ARCH = linux + +### Vars... +# Design prefix (from --prefix) +VM_PREFIX = Valu +# Module prefix (from --prefix) +VM_MODPREFIX = Valu +# User CFLAGS (from -CFLAGS on Verilator command line) +VM_USER_CFLAGS = \ + +# User LDLIBS (from -LDFLAGS on Verilator command line) +VM_USER_LDLIBS = \ + +# User .cpp files (from .cpp's on Verilator command line) +VM_USER_CLASSES = \ + tbalu \ + +# User .cpp directories (from .cpp's on Verilator command line) +VM_USER_DIR = \ + . \ + + +### Default rules... +# Include list of all generated classes +include Valu_classes.mk +# Include global rules +include $(VERILATOR_ROOT)/include/verilated.mk + +### Executable rules... (from --exe) +VPATH += $(VM_USER_DIR) + +tbalu.o: tbalu.cpp + $(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $< + +### Link rules... (from --exe) +Valu: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a $(VM_HIER_LIBS) + $(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) $(LIBS) $(SC_LIBS) -o $@ + + +# Verilated -*- Makefile -*- diff --git a/verilog/alu/obj_dir/Valu__ALL.a b/verilog/alu/obj_dir/Valu__ALL.a Binary files differnew file mode 100644 index 0000000..4ad5286 --- /dev/null +++ b/verilog/alu/obj_dir/Valu__ALL.a diff --git a/verilog/alu/obj_dir/Valu__ALL.cpp b/verilog/alu/obj_dir/Valu__ALL.cpp new file mode 100644 index 0000000..ed815ee --- /dev/null +++ b/verilog/alu/obj_dir/Valu__ALL.cpp @@ -0,0 +1,9 @@ +// DESCRIPTION: Generated by verilator_includer via makefile +#define VL_INCLUDE_OPT include +#include "Valu.cpp" +#include "Valu___024root__DepSet_ha59b247d__0.cpp" +#include "Valu__Trace__0.cpp" +#include "Valu___024root__Slow.cpp" +#include "Valu___024root__DepSet_ha59b247d__0__Slow.cpp" +#include "Valu__Syms.cpp" +#include "Valu__Trace__0__Slow.cpp" diff --git a/verilog/alu/obj_dir/Valu__ALL.d b/verilog/alu/obj_dir/Valu__ALL.d new file mode 100644 index 0000000..636205f --- /dev/null +++ b/verilog/alu/obj_dir/Valu__ALL.d @@ -0,0 +1,13 @@ +Valu__ALL.o: Valu__ALL.cpp Valu.cpp Valu.h \ + /usr/share/verilator/include/verilated.h \ + /usr/share/verilator/include/verilatedos.h \ + /usr/share/verilator/include/verilated_config.h \ + /usr/share/verilator/include/verilated_types.h \ + /usr/share/verilator/include/verilated_funcs.h Valu__Syms.h \ + Valu___024root.h /usr/share/verilator/include/verilated_vcd_c.h \ + /usr/share/verilator/include/verilated.h \ + /usr/share/verilator/include/verilated_trace.h \ + /usr/share/verilator/include/verilated_trace_defs.h \ + Valu___024root__DepSet_ha59b247d__0.cpp Valu__Trace__0.cpp \ + Valu___024root__Slow.cpp Valu___024root__DepSet_ha59b247d__0__Slow.cpp \ + Valu__Syms.cpp Valu__Trace__0__Slow.cpp diff --git a/verilog/alu/obj_dir/Valu__ALL.o b/verilog/alu/obj_dir/Valu__ALL.o Binary files differnew file mode 100644 index 0000000..1377001 --- /dev/null +++ b/verilog/alu/obj_dir/Valu__ALL.o diff --git a/verilog/alu/obj_dir/Valu__Syms.cpp b/verilog/alu/obj_dir/Valu__Syms.cpp new file mode 100644 index 0000000..bd9fdd1 --- /dev/null +++ b/verilog/alu/obj_dir/Valu__Syms.cpp @@ -0,0 +1,26 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Symbol table implementation internals + +#include "Valu__Syms.h" +#include "Valu.h" +#include "Valu___024root.h" + +// FUNCTIONS +Valu__Syms::~Valu__Syms() +{ +} + +Valu__Syms::Valu__Syms(VerilatedContext* contextp, const char* namep,Valu* modelp) + : VerilatedSyms{contextp} + // Setup internal state of the Syms class + , __Vm_modelp{modelp} + // Setup module instances + , TOP(namep) +{ + // Configure time unit / time precision + _vm_contextp__->timeunit(-6); + _vm_contextp__->timeprecision(-9); + // Setup each module's pointers to their submodules + // Setup each module's pointer back to symbol table (for public functions) + TOP.__Vconfigure(this, true); +} diff --git a/verilog/alu/obj_dir/Valu__Syms.h b/verilog/alu/obj_dir/Valu__Syms.h new file mode 100644 index 0000000..e69592b --- /dev/null +++ b/verilog/alu/obj_dir/Valu__Syms.h @@ -0,0 +1,39 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Symbol table internal header +// +// Internal details; most calling programs do not need this header, +// unless using verilator public meta comments. + +#ifndef VERILATED_VALU__SYMS_H_ +#define VERILATED_VALU__SYMS_H_ // guard + +#include "verilated.h" + +// INCLUDE MODEL CLASS + +#include "Valu.h" + +// INCLUDE MODULE CLASSES +#include "Valu___024root.h" + +// SYMS CLASS (contains all model state) +class Valu__Syms final : public VerilatedSyms { + public: + // INTERNAL STATE + Valu* const __Vm_modelp; + bool __Vm_activity = false; ///< Used by trace routines to determine change occurred + uint32_t __Vm_baseCode = 0; ///< Used by trace routines when tracing multiple models + bool __Vm_didInit = false; + + // MODULE INSTANCE STATE + Valu___024root TOP; + + // CONSTRUCTORS + Valu__Syms(VerilatedContext* contextp, const char* namep, Valu* modelp); + ~Valu__Syms(); + + // METHODS + const char* name() { return TOP.name(); } +} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES); + +#endif // guard diff --git a/verilog/alu/obj_dir/Valu__Trace__0.cpp b/verilog/alu/obj_dir/Valu__Trace__0.cpp new file mode 100644 index 0000000..4713f0f --- /dev/null +++ b/verilog/alu/obj_dir/Valu__Trace__0.cpp @@ -0,0 +1,42 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Tracing implementation internals +#include "verilated_vcd_c.h" +#include "Valu__Syms.h" + + +void Valu___024root__trace_chg_sub_0(Valu___024root* vlSelf, VerilatedVcd* tracep); + +void Valu___024root__trace_chg_top_0(void* voidSelf, VerilatedVcd* tracep) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu___024root__trace_chg_top_0\n"); ); + // Init + Valu___024root* const __restrict vlSelf VL_ATTR_UNUSED = static_cast<Valu___024root*>(voidSelf); + Valu__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; + if (VL_UNLIKELY(!vlSymsp->__Vm_activity)) return; + // Body + Valu___024root__trace_chg_sub_0((&vlSymsp->TOP), tracep); +} + +void Valu___024root__trace_chg_sub_0(Valu___024root* vlSelf, VerilatedVcd* tracep) { + if (false && vlSelf) {} // Prevent unused + Valu__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu___024root__trace_chg_sub_0\n"); ); + // Init + vluint32_t* const oldp VL_ATTR_UNUSED = tracep->oldp(vlSymsp->__Vm_baseCode + 1); + // Body + tracep->chgIData(oldp+0,(vlSelf->in1),32); + tracep->chgIData(oldp+1,(vlSelf->in2),32); + tracep->chgCData(oldp+2,(vlSelf->op),4); + tracep->chgIData(oldp+3,(vlSelf->out),32); + tracep->chgIData(oldp+4,(vlSelf->alu__DOT__result),32); +} + +void Valu___024root__trace_cleanup(void* voidSelf, VerilatedVcd* /*unused*/) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu___024root__trace_cleanup\n"); ); + // Init + Valu___024root* const __restrict vlSelf VL_ATTR_UNUSED = static_cast<Valu___024root*>(voidSelf); + Valu__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; + VlUnpacked<CData/*0:0*/, 1> __Vm_traceActivity; + // Body + vlSymsp->__Vm_activity = false; + __Vm_traceActivity[0U] = 0U; +} diff --git a/verilog/alu/obj_dir/Valu__Trace__0__Slow.cpp b/verilog/alu/obj_dir/Valu__Trace__0__Slow.cpp new file mode 100644 index 0000000..25d47f5 --- /dev/null +++ b/verilog/alu/obj_dir/Valu__Trace__0__Slow.cpp @@ -0,0 +1,74 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Tracing implementation internals +#include "verilated_vcd_c.h" +#include "Valu__Syms.h" + + +VL_ATTR_COLD void Valu___024root__trace_init_sub__TOP__0(Valu___024root* vlSelf, VerilatedVcd* tracep) { + if (false && vlSelf) {} // Prevent unused + Valu__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu___024root__trace_init_sub__TOP__0\n"); ); + // Init + const int c = vlSymsp->__Vm_baseCode; + // Body + tracep->declBus(c+1,"in1", false,-1, 31,0); + tracep->declBus(c+2,"in2", false,-1, 31,0); + tracep->declBus(c+3,"op", false,-1, 3,0); + tracep->declBus(c+4,"out", false,-1, 31,0); + tracep->pushNamePrefix("alu "); + tracep->declBus(c+1,"in1", false,-1, 31,0); + tracep->declBus(c+2,"in2", false,-1, 31,0); + tracep->declBus(c+3,"op", false,-1, 3,0); + tracep->declBus(c+4,"out", false,-1, 31,0); + tracep->declBus(c+6,"diff", false,-1, 31,0); + tracep->declBus(c+5,"result", false,-1, 31,0); + tracep->popNamePrefix(1); +} + +VL_ATTR_COLD void Valu___024root__trace_init_top(Valu___024root* vlSelf, VerilatedVcd* tracep) { + if (false && vlSelf) {} // Prevent unused + Valu__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu___024root__trace_init_top\n"); ); + // Body + Valu___024root__trace_init_sub__TOP__0(vlSelf, tracep); +} + +VL_ATTR_COLD void Valu___024root__trace_full_top_0(void* voidSelf, VerilatedVcd* tracep); +void Valu___024root__trace_chg_top_0(void* voidSelf, VerilatedVcd* tracep); +void Valu___024root__trace_cleanup(void* voidSelf, VerilatedVcd* /*unused*/); + +VL_ATTR_COLD void Valu___024root__trace_register(Valu___024root* vlSelf, VerilatedVcd* tracep) { + if (false && vlSelf) {} // Prevent unused + Valu__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu___024root__trace_register\n"); ); + // Body + tracep->addFullCb(&Valu___024root__trace_full_top_0, vlSelf); + tracep->addChgCb(&Valu___024root__trace_chg_top_0, vlSelf); + tracep->addCleanupCb(&Valu___024root__trace_cleanup, vlSelf); +} + +VL_ATTR_COLD void Valu___024root__trace_full_sub_0(Valu___024root* vlSelf, VerilatedVcd* tracep); + +VL_ATTR_COLD void Valu___024root__trace_full_top_0(void* voidSelf, VerilatedVcd* tracep) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu___024root__trace_full_top_0\n"); ); + // Init + Valu___024root* const __restrict vlSelf VL_ATTR_UNUSED = static_cast<Valu___024root*>(voidSelf); + Valu__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; + // Body + Valu___024root__trace_full_sub_0((&vlSymsp->TOP), tracep); +} + +VL_ATTR_COLD void Valu___024root__trace_full_sub_0(Valu___024root* vlSelf, VerilatedVcd* tracep) { + if (false && vlSelf) {} // Prevent unused + Valu__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu___024root__trace_full_sub_0\n"); ); + // Init + vluint32_t* const oldp VL_ATTR_UNUSED = tracep->oldp(vlSymsp->__Vm_baseCode); + // Body + tracep->fullIData(oldp+1,(vlSelf->in1),32); + tracep->fullIData(oldp+2,(vlSelf->in2),32); + tracep->fullCData(oldp+3,(vlSelf->op),4); + tracep->fullIData(oldp+4,(vlSelf->out),32); + tracep->fullIData(oldp+5,(vlSelf->alu__DOT__result),32); + tracep->fullIData(oldp+6,(0U),32); +} diff --git a/verilog/alu/obj_dir/Valu___024root.h b/verilog/alu/obj_dir/Valu___024root.h new file mode 100644 index 0000000..18b3f2f --- /dev/null +++ b/verilog/alu/obj_dir/Valu___024root.h @@ -0,0 +1,34 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design internal header +// See Valu.h for the primary calling header + +#ifndef VERILATED_VALU___024ROOT_H_ +#define VERILATED_VALU___024ROOT_H_ // guard + +#include "verilated.h" + +class Valu__Syms; +VL_MODULE(Valu___024root) { + public: + + // DESIGN SPECIFIC STATE + VL_IN8(op,3,0); + VL_IN(in1,31,0); + VL_IN(in2,31,0); + VL_OUT(out,31,0); + IData/*31:0*/ alu__DOT__result; + + // INTERNAL VARIABLES + Valu__Syms* vlSymsp; // Symbol table + + // CONSTRUCTORS + Valu___024root(const char* name); + ~Valu___024root(); + VL_UNCOPYABLE(Valu___024root); + + // INTERNAL METHODS + void __Vconfigure(Valu__Syms* symsp, bool first); +} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES); + + +#endif // guard diff --git a/verilog/alu/obj_dir/Valu___024root__DepSet_ha59b247d__0.cpp b/verilog/alu/obj_dir/Valu___024root__DepSet_ha59b247d__0.cpp new file mode 100644 index 0000000..99146ec --- /dev/null +++ b/verilog/alu/obj_dir/Valu___024root__DepSet_ha59b247d__0.cpp @@ -0,0 +1,117 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design implementation internals +// See Valu.h for the primary calling header + +#include "verilated.h" + +#include "Valu___024root.h" + +VL_INLINE_OPT void Valu___024root___combo__TOP__0(Valu___024root* vlSelf) { + if (false && vlSelf) {} // Prevent unused + Valu__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu___024root___combo__TOP__0\n"); ); + // Body + vlSelf->alu__DOT__result = ((8U & (IData)(vlSelf->op)) + ? ((4U & (IData)(vlSelf->op)) + ? ((2U & (IData)(vlSelf->op)) + ? ((1U & (IData)(vlSelf->op)) + ? vlSelf->in1 + : 0U) : + ((1U & (IData)(vlSelf->op)) + ? (((0x1fU + >= vlSelf->in2) + ? (vlSelf->in1 + >> vlSelf->in2) + : 0U) + | ((vlSelf->in1 + >> 0x1fU) + ? + ((IData)(0xffffffffU) + << + ((0x10U + & ((~ + (vlSelf->in2 + >> 4U)) + << 4U)) + | ((8U + & ((~ + (vlSelf->in2 + >> 3U)) + << 3U)) + | ((4U + & ((~ + (vlSelf->in2 + >> 2U)) + << 2U)) + | ((2U + & ((~ + (vlSelf->in2 + >> 1U)) + << 1U)) + | (1U + & (~ vlSelf->in2))))))) + : 0U)) + : 0U)) : 0U) + : ((4U & (IData)(vlSelf->op)) + ? ((2U & (IData)(vlSelf->op)) + ? ((1U & (IData)(vlSelf->op)) + ? (vlSelf->in1 + & vlSelf->in2) + : (vlSelf->in1 + | vlSelf->in2)) + : ((1U & (IData)(vlSelf->op)) + ? ((0x1fU + >= vlSelf->in2) + ? + (vlSelf->in1 + >> vlSelf->in2) + : 0U) + : (vlSelf->in1 + - vlSelf->in2))) + : ((2U & (IData)(vlSelf->op)) + ? ((1U & (IData)(vlSelf->op)) + ? ((vlSelf->in1 + < vlSelf->in2) + ? 1U + : 0U) + : (((vlSelf->in1 + >> 0x1fU) + == + (vlSelf->in2 + >> 0x1fU)) + ? 0U + : + ((vlSelf->in1 + >> 0x1fU) + ? 1U + : 0U))) + : ((1U & (IData)(vlSelf->op)) + ? ((0x1fU + >= vlSelf->in2) + ? + (vlSelf->in1 + >> vlSelf->in2) + : 0U) + : (vlSelf->in1 + + vlSelf->in2))))); + vlSelf->out = vlSelf->alu__DOT__result; +} + +void Valu___024root___eval(Valu___024root* vlSelf) { + if (false && vlSelf) {} // Prevent unused + Valu__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu___024root___eval\n"); ); + // Body + Valu___024root___combo__TOP__0(vlSelf); +} + +#ifdef VL_DEBUG +void Valu___024root___eval_debug_assertions(Valu___024root* vlSelf) { + if (false && vlSelf) {} // Prevent unused + Valu__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu___024root___eval_debug_assertions\n"); ); + // Body + if (VL_UNLIKELY((vlSelf->op & 0xf0U))) { + Verilated::overWidthError("op");} +} +#endif // VL_DEBUG diff --git a/verilog/alu/obj_dir/Valu___024root__DepSet_ha59b247d__0__Slow.cpp b/verilog/alu/obj_dir/Valu___024root__DepSet_ha59b247d__0__Slow.cpp new file mode 100644 index 0000000..99dde1e --- /dev/null +++ b/verilog/alu/obj_dir/Valu___024root__DepSet_ha59b247d__0__Slow.cpp @@ -0,0 +1,41 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design implementation internals +// See Valu.h for the primary calling header + +#include "verilated.h" + +#include "Valu___024root.h" + +VL_ATTR_COLD void Valu___024root___eval_initial(Valu___024root* vlSelf) { + if (false && vlSelf) {} // Prevent unused + Valu__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu___024root___eval_initial\n"); ); +} + +void Valu___024root___combo__TOP__0(Valu___024root* vlSelf); + +VL_ATTR_COLD void Valu___024root___eval_settle(Valu___024root* vlSelf) { + if (false && vlSelf) {} // Prevent unused + Valu__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu___024root___eval_settle\n"); ); + // Body + Valu___024root___combo__TOP__0(vlSelf); +} + +VL_ATTR_COLD void Valu___024root___final(Valu___024root* vlSelf) { + if (false && vlSelf) {} // Prevent unused + Valu__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu___024root___final\n"); ); +} + +VL_ATTR_COLD void Valu___024root___ctor_var_reset(Valu___024root* vlSelf) { + if (false && vlSelf) {} // Prevent unused + Valu__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu___024root___ctor_var_reset\n"); ); + // Body + vlSelf->in1 = VL_RAND_RESET_I(32); + vlSelf->in2 = VL_RAND_RESET_I(32); + vlSelf->op = VL_RAND_RESET_I(4); + vlSelf->out = VL_RAND_RESET_I(32); + vlSelf->alu__DOT__result = VL_RAND_RESET_I(32); +} diff --git a/verilog/alu/obj_dir/Valu___024root__Slow.cpp b/verilog/alu/obj_dir/Valu___024root__Slow.cpp new file mode 100644 index 0000000..7e197c5 --- /dev/null +++ b/verilog/alu/obj_dir/Valu___024root__Slow.cpp @@ -0,0 +1,25 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design implementation internals +// See Valu.h for the primary calling header + +#include "verilated.h" + +#include "Valu__Syms.h" +#include "Valu___024root.h" + +void Valu___024root___ctor_var_reset(Valu___024root* vlSelf); + +Valu___024root::Valu___024root(const char* _vcname__) + : VerilatedModule(_vcname__) + { + // Reset structure values + Valu___024root___ctor_var_reset(this); +} + +void Valu___024root::__Vconfigure(Valu__Syms* _vlSymsp, bool first) { + if (false && first) {} // Prevent unused + this->vlSymsp = _vlSymsp; +} + +Valu___024root::~Valu___024root() { +} diff --git a/verilog/alu/obj_dir/Valu__ver.d b/verilog/alu/obj_dir/Valu__ver.d new file mode 100644 index 0000000..050f4a2 --- /dev/null +++ b/verilog/alu/obj_dir/Valu__ver.d @@ -0,0 +1 @@ +obj_dir/Valu.cpp obj_dir/Valu.h obj_dir/Valu.mk obj_dir/Valu__Syms.cpp obj_dir/Valu__Syms.h obj_dir/Valu__Trace__0.cpp obj_dir/Valu__Trace__0__Slow.cpp obj_dir/Valu___024root.h obj_dir/Valu___024root__DepSet_ha59b247d__0.cpp obj_dir/Valu___024root__DepSet_ha59b247d__0__Slow.cpp obj_dir/Valu___024root__Slow.cpp obj_dir/Valu__ver.d obj_dir/Valu_classes.mk : /usr/bin/verilator_bin /usr/bin/verilator_bin alu.v aluOp.vh diff --git a/verilog/alu/obj_dir/Valu__verFiles.dat b/verilog/alu/obj_dir/Valu__verFiles.dat new file mode 100644 index 0000000..9886e43 --- /dev/null +++ b/verilog/alu/obj_dir/Valu__verFiles.dat @@ -0,0 +1,19 @@ +# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will. +C "-Wall --cc --exe --build tbalu.cpp alu.v --trace" +S 8301864 49571880 1647534899 665184882 1647204701 0 "/usr/bin/verilator_bin" +S 826 47450694 1650399377 438046012 1650399377 438046012 "alu.v" +S 391 47450690 1650315291 577169333 1650315291 577169333 "aluOp.vh" +T 3738 47972485 1650399379 228051294 1650399379 228051294 "obj_dir/Valu.cpp" +T 2663 47972468 1650399379 228051294 1650399379 228051294 "obj_dir/Valu.h" +T 1808 47972982 1650399379 228051294 1650399379 228051294 "obj_dir/Valu.mk" +T 735 47972353 1650399379 228051294 1650399379 228051294 "obj_dir/Valu__Syms.cpp" +T 1073 47972356 1650399379 228051294 1650399379 228051294 "obj_dir/Valu__Syms.h" +T 1816 47972973 1650399379 228051294 1650399379 228051294 "obj_dir/Valu__Trace__0.cpp" +T 3410 47972972 1650399379 228051294 1650399379 228051294 "obj_dir/Valu__Trace__0__Slow.cpp" +T 765 47972494 1650399379 228051294 1650399379 228051294 "obj_dir/Valu___024root.h" +T 6435 47972971 1650399379 228051294 1650399379 228051294 "obj_dir/Valu___024root__DepSet_ha59b247d__0.cpp" +T 1597 47972817 1650399379 228051294 1650399379 228051294 "obj_dir/Valu___024root__DepSet_ha59b247d__0__Slow.cpp" +T 630 47972816 1650399379 228051294 1650399379 228051294 "obj_dir/Valu___024root__Slow.cpp" +T 421 47972983 1650399379 228051294 1650399379 228051294 "obj_dir/Valu__ver.d" +T 0 0 1650399379 228051294 1650399379 228051294 "obj_dir/Valu__verFiles.dat" +T 1735 47972979 1650399379 228051294 1650399379 228051294 "obj_dir/Valu_classes.mk" diff --git a/verilog/alu/obj_dir/Valu_classes.mk b/verilog/alu/obj_dir/Valu_classes.mk new file mode 100644 index 0000000..ba99411 --- /dev/null +++ b/verilog/alu/obj_dir/Valu_classes.mk @@ -0,0 +1,54 @@ +# Verilated -*- Makefile -*- +# DESCRIPTION: Verilator output: Make include file with class lists +# +# This file lists generated Verilated files, for including in higher level makefiles. +# See Valu.mk for the caller. + +### Switches... +# C11 constructs required? 0/1 (always on now) +VM_C11 = 1 +# Coverage output mode? 0/1 (from --coverage) +VM_COVERAGE = 0 +# Parallel builds? 0/1 (from --output-split) +VM_PARALLEL_BUILDS = 0 +# Threaded output mode? 0/1/N threads (from --threads) +VM_THREADS = 0 +# Tracing output mode? 0/1 (from --trace/--trace-fst) +VM_TRACE = 1 +# Tracing output mode in FST format? 0/1 (from --trace-fst) +VM_TRACE_FST = 0 +# Tracing threaded output mode? 0/1/N threads (from --trace-thread) +VM_TRACE_THREADS = 0 +# Separate FST writer thread? 0/1 (from --trace-fst with --trace-thread > 0) +VM_TRACE_FST_WRITER_THREAD = 0 + +### Object file lists... +# Generated module classes, fast-path, compile with highest optimization +VM_CLASSES_FAST += \ + Valu \ + Valu___024root__DepSet_ha59b247d__0 \ + +# Generated module classes, non-fast-path, compile with low/medium optimization +VM_CLASSES_SLOW += \ + Valu___024root__Slow \ + Valu___024root__DepSet_ha59b247d__0__Slow \ + +# Generated support classes, fast-path, compile with highest optimization +VM_SUPPORT_FAST += \ + Valu__Trace__0 \ + +# Generated support classes, non-fast-path, compile with low/medium optimization +VM_SUPPORT_SLOW += \ + Valu__Syms \ + Valu__Trace__0__Slow \ + +# Global classes, need linked once per executable, fast-path, compile with highest optimization +VM_GLOBAL_FAST += \ + verilated \ + verilated_vcd_c \ + +# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization +VM_GLOBAL_SLOW += \ + + +# Verilated -*- Makefile -*- diff --git a/verilog/alu/obj_dir/tbalu.d b/verilog/alu/obj_dir/tbalu.d new file mode 100644 index 0000000..4964d6f --- /dev/null +++ b/verilog/alu/obj_dir/tbalu.d @@ -0,0 +1,9 @@ +tbalu.o: ../tbalu.cpp /usr/share/verilator/include/verilated.h \ + /usr/share/verilator/include/verilatedos.h \ + /usr/share/verilator/include/verilated_config.h \ + /usr/share/verilator/include/verilated_types.h \ + /usr/share/verilator/include/verilated_funcs.h \ + /usr/share/verilator/include/verilated_vcd_c.h \ + /usr/share/verilator/include/verilated.h \ + /usr/share/verilator/include/verilated_trace.h \ + /usr/share/verilator/include/verilated_trace_defs.h Valu.h ../aluOp.h diff --git a/verilog/alu/obj_dir/tbalu.o b/verilog/alu/obj_dir/tbalu.o Binary files differnew file mode 100644 index 0000000..1612e2b --- /dev/null +++ b/verilog/alu/obj_dir/tbalu.o diff --git a/verilog/alu/obj_dir/verilated.d b/verilog/alu/obj_dir/verilated.d new file mode 100644 index 0000000..7f4c5e4 --- /dev/null +++ b/verilog/alu/obj_dir/verilated.d @@ -0,0 +1,9 @@ +verilated.o: /usr/share/verilator/include/verilated.cpp \ + /usr/share/verilator/include/verilatedos.h \ + /usr/share/verilator/include/verilated_imp.h \ + /usr/share/verilator/include/verilated.h \ + /usr/share/verilator/include/verilated_config.h \ + /usr/share/verilator/include/verilated_types.h \ + /usr/share/verilator/include/verilated_funcs.h \ + /usr/share/verilator/include/verilated_syms.h \ + /usr/share/verilator/include/verilated_sym_props.h diff --git a/verilog/alu/obj_dir/verilated.o b/verilog/alu/obj_dir/verilated.o Binary files differnew file mode 100644 index 0000000..a226a8b --- /dev/null +++ b/verilog/alu/obj_dir/verilated.o diff --git a/verilog/alu/obj_dir/verilated_vcd_c.d b/verilog/alu/obj_dir/verilated_vcd_c.d new file mode 100644 index 0000000..667485f --- /dev/null +++ b/verilog/alu/obj_dir/verilated_vcd_c.d @@ -0,0 +1,11 @@ +verilated_vcd_c.o: /usr/share/verilator/include/verilated_vcd_c.cpp \ + /usr/share/verilator/include/verilatedos.h \ + /usr/share/verilator/include/verilated.h \ + /usr/share/verilator/include/verilated_config.h \ + /usr/share/verilator/include/verilated_types.h \ + /usr/share/verilator/include/verilated_funcs.h \ + /usr/share/verilator/include/verilated_vcd_c.h \ + /usr/share/verilator/include/verilated_trace.h \ + /usr/share/verilator/include/verilated_trace_defs.h \ + /usr/share/verilator/include/verilated_trace_imp.cpp \ + /usr/share/verilator/include/verilated_intrinsics.h diff --git a/verilog/alu/obj_dir/verilated_vcd_c.o b/verilog/alu/obj_dir/verilated_vcd_c.o Binary files differnew file mode 100644 index 0000000..469c75e --- /dev/null +++ b/verilog/alu/obj_dir/verilated_vcd_c.o diff --git a/verilog/alu/tbalu.v b/verilog/alu/tbalu.v deleted file mode 100644 index 7ffc8bf..0000000 --- a/verilog/alu/tbalu.v +++ /dev/null @@ -1,50 +0,0 @@ -`timescale 1us/1ns - -`include "alu_ops.vh" -`include "alu.v" - -module tbalu; - -reg [31:0] in1,in2; -wire [31:0] out; -reg [3:0] op; - -alu alu0 (in1, in2,op, out); - -initial begin - in1=-32'b1; - in2=32'b1; - op=`ADD; - #5 - $display("\nPlus:\t\t %d %32b + %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out); - op=`SUB; - #5 - $display("\nMinus:\t\t %d %32b - %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out); - op=`XOR; - #5 - $display("\nXor:\t\t %d %32b ^ %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out); - op=`OR; - #5 - $display("\nOr:\t\t %d %32b | %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out); - op=`AND; - #5 - $display("\nAnd:\t\t %d %32b & %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out); - op=`SLL; - #5 - $display("\nLeft Logical:\t %d %32b << %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out); - op=`SRL; - #5 - $display("\nRight Logical:\t %d %32b >> %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out); - op=`SRA; - #5 - $display("\nRight Arith:\t %d %32b >>> %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out); - op=`SLT; - #5 - $display("\nSet Less:\t %d %32b < %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out); - op=`SLTU; - #5 - $display("\nSet Less U:\t %d %32b < U %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out); - $finish; -end - -endmodule diff --git a/verilog/alu/v1/Makefile b/verilog/alu/v1/Makefile new file mode 100644 index 0000000..74816c7 --- /dev/null +++ b/verilog/alu/v1/Makefile @@ -0,0 +1,35 @@ +PROJ=alu +VERION:=r0.2 +RM = rm -rf +COPY = cp -a +PATH_SEP = / + + +crab: ${PROJ}.dfu + +dfu: ${PROJ}.dfu + dfu-util -D $< + + +%.json: %.v + yosys -p "read_verilog $<; synth_ecp5 -top ${PROJ} -json $@" + +%_out.config: %.json + nextpnr-ecp5 --json $< --textcfg $@ --25k --package CSFBGA285 --lpf crab.pcf + +%.bit: %_out.config + ecppack --compress --freq 38.8 --input $< --bit $@ + +%.dfu : %.bit + $(COPY) $< $@ + dfu-suffix -v 1209 -p 5af0 -a $@ + +sim: + verilator -Wall --cc --exe --build tbalu.cpp alu.v --trace && ./obj_dir/Valu > out +simclean: + rm -rf obj_dir/* out + +clean: + $(RM) -f ${PROJ}.bit ${PROJ}_out.config ${PROJ}.json ${PROJ}.dfu + +.PHONY: prog clean diff --git a/verilog/alu/v1/alu.v b/verilog/alu/v1/alu.v new file mode 100644 index 0000000..cb66ddb --- /dev/null +++ b/verilog/alu/v1/alu.v @@ -0,0 +1,34 @@ +`default_nettype none +`timescale 1us/1ns + +`include "aluOp.vh" + +module alu +( +input wire [31:0] alu_in_1, +input wire[31:0] alu_in_2, +input wire[3:0] alu_op_i, +output wire[31:0] alu_output +); + + +wire [31:0] diff = alu_in_1 - alu_in_2; + +assign alu_output = + alu_op_i == `ADD ? alu_in_1 + alu_in_2 : + alu_op_i == `SUB ? diff : + alu_op_i == `XOR ? alu_in_1 ^ alu_in_2 : + alu_op_i == `OR ? alu_in_1 | alu_in_2 : + alu_op_i == `AND ? alu_in_1 & alu_in_2 : + alu_op_i == `SLL ? alu_in_1 << alu_in_2 : + alu_op_i == `SRL ? alu_in_1 >> alu_in_2 : + alu_op_i == `SLTU ? (alu_in_1 < alu_in_2 ? 32'b1 : 32'b0) : + alu_op_i == `NONE ? alu_in_1 : + alu_op_i == `SLT ? (alu_in_1[31] == alu_in_2[31] ? (diff[31] == 1'b0 ? 32'b0 : 32'b1) : (alu_in_1[31] == 1'b1 ? 32'b1 : 32'b0) ) : + alu_op_i == `SRA ? (alu_in_1 >> alu_in_2) | (alu_in_1[31] == 1'b0 ? 32'b0 : + 32'hFFFFFFFF << ((alu_in_2[4] ? 0 : 5'b10000) + (alu_in_2[3] ? 0 : 5'b01000) + + (alu_in_2[2] ? 0 : 5'b00100) + (alu_in_2[1] ? 0 : 5'b00010) + (alu_in_2[0] ? 0 : 5'b00001)) + ) : + 32'b0; + +endmodule diff --git a/verilog/alu/v1/aluOp.h b/verilog/alu/v1/aluOp.h new file mode 100644 index 0000000..999dac2 --- /dev/null +++ b/verilog/alu/v1/aluOp.h @@ -0,0 +1,16 @@ +#ifndef ALU_OP +#define ALU_OP + +#define ADD 0 +#define SUB 8 +#define XOR 4 +#define OR 6 +#define AND 7 +#define SLL 1 +#define SRL 5 +#define SRA 13 +#define SLT 2 +#define SLTU 3 +#define NONE 15 + +#endif diff --git a/verilog/alu/aluOp.vh b/verilog/alu/v1/aluOp.vh index c67cd33..b6e916f 100644 --- a/verilog/alu/aluOp.vh +++ b/verilog/alu/v1/aluOp.vh @@ -1,5 +1,6 @@ `ifndef ALU_OP `define ALU_OP + `define ADD 4'b0000 `define SUB 4'b1000 `define XOR 4'b0100 @@ -10,5 +11,6 @@ `define SRA 4'b1101 `define SLT 4'b0010 `define SLTU 4'b0011 -`define NONE 4'h1111 +`define NONE 4'b1111 + `endif diff --git a/verilog/alu/v1/crab.pcf b/verilog/alu/v1/crab.pcf new file mode 100644 index 0000000..c0d91c5 --- /dev/null +++ b/verilog/alu/v1/crab.pcf @@ -0,0 +1,254 @@ +LOCATE COMP "clk48" SITE "A9"; +IOBUF PORT "clk48" IO_TYPE=LVCMOS33; +FREQUENCY PORT "clk48" 48.0 MHz; + +LOCATE COMP "ddram_a[0]" SITE "C4"; +IOBUF PORT "ddram_a[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[0]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[1]" SITE "D2"; +IOBUF PORT "ddram_a[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[1]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[2]" SITE "D3"; +IOBUF PORT "ddram_a[2]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[2]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[3]" SITE "A3"; +IOBUF PORT "ddram_a[3]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[3]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[4]" SITE "A4"; +IOBUF PORT "ddram_a[4]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[4]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[5]" SITE "D4"; +IOBUF PORT "ddram_a[5]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[5]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[6]" SITE "C3"; +IOBUF PORT "ddram_a[6]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[6]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[7]" SITE "B2"; +IOBUF PORT "ddram_a[7]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[7]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[8]" SITE "B1"; +IOBUF PORT "ddram_a[8]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[8]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[9]" SITE "D1"; +IOBUF PORT "ddram_a[9]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[9]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[10]" SITE "A7"; +IOBUF PORT "ddram_a[10]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[10]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[11]" SITE "C2"; +IOBUF PORT "ddram_a[11]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[11]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[12]" SITE "B6"; +IOBUF PORT "ddram_a[12]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[12]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[13]" SITE "C1"; +IOBUF PORT "ddram_a[13]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[13]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[14]" SITE "A2"; +IOBUF PORT "ddram_a[14]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[14]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[15]" SITE "C7"; +IOBUF PORT "ddram_a[15]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[15]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_ba[0]" SITE "D6"; +IOBUF PORT "ddram_ba[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_ba[0]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_ba[1]" SITE "B7"; +IOBUF PORT "ddram_ba[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_ba[1]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_ba[2]" SITE "A6"; +IOBUF PORT "ddram_ba[2]" SLEWRATE=FAST; +IOBUF PORT "ddram_ba[2]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_ras_n" SITE "C12"; +IOBUF PORT "ddram_ras_n" SLEWRATE=FAST; +IOBUF PORT "ddram_ras_n" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_cas_n" SITE "D13"; +IOBUF PORT "ddram_cas_n" SLEWRATE=FAST; +IOBUF PORT "ddram_cas_n" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_we_n" SITE "B12"; +IOBUF PORT "ddram_we_n" SLEWRATE=FAST; +IOBUF PORT "ddram_we_n" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_cs_n" SITE "A12"; +IOBUF PORT "ddram_cs_n" SLEWRATE=FAST; +IOBUF PORT "ddram_cs_n" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_dm[0]" SITE "D16"; +IOBUF PORT "ddram_dm[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_dm[0]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_dm[1]" SITE "G16"; +IOBUF PORT "ddram_dm[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_dm[1]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_dq[0]" SITE "C17"; +IOBUF PORT "ddram_dq[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[0]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[0]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[1]" SITE "D15"; +IOBUF PORT "ddram_dq[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[1]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[1]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[2]" SITE "B17"; +IOBUF PORT "ddram_dq[2]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[2]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[2]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[3]" SITE "C16"; +IOBUF PORT "ddram_dq[3]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[3]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[3]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[4]" SITE "A15"; +IOBUF PORT "ddram_dq[4]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[4]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[4]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[5]" SITE "B13"; +IOBUF PORT "ddram_dq[5]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[5]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[5]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[6]" SITE "A17"; +IOBUF PORT "ddram_dq[6]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[6]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[6]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[7]" SITE "A13"; +IOBUF PORT "ddram_dq[7]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[7]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[7]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[8]" SITE "F17"; +IOBUF PORT "ddram_dq[8]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[8]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[8]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[9]" SITE "F16"; +IOBUF PORT "ddram_dq[9]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[9]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[9]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[10]" SITE "G15"; +IOBUF PORT "ddram_dq[10]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[10]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[10]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[11]" SITE "F15"; +IOBUF PORT "ddram_dq[11]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[11]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[11]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[12]" SITE "J16"; +IOBUF PORT "ddram_dq[12]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[12]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[12]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[13]" SITE "C18"; +IOBUF PORT "ddram_dq[13]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[13]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[13]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[14]" SITE "H16"; +IOBUF PORT "ddram_dq[14]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[14]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[14]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[15]" SITE "F18"; +IOBUF PORT "ddram_dq[15]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[15]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[15]" TERMINATION=OFF; +LOCATE COMP "ddram_dqs_p[0]" SITE "B15"; +IOBUF PORT "ddram_dqs_p[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_dqs_p[0]" IO_TYPE=SSTL135D_I; +IOBUF PORT "ddram_dqs_p[0]" TERMINATION=OFF; +IOBUF PORT "ddram_dqs_p[0]" DIFFRESISTOR=100; +LOCATE COMP "ddram_dqs_p[1]" SITE "G18"; +IOBUF PORT "ddram_dqs_p[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_dqs_p[1]" IO_TYPE=SSTL135D_I; +IOBUF PORT "ddram_dqs_p[1]" TERMINATION=OFF; +IOBUF PORT "ddram_dqs_p[1]" DIFFRESISTOR=100; +LOCATE COMP "ddram_clk_p" SITE "J18"; +IOBUF PORT "ddram_clk_p" SLEWRATE=FAST; +IOBUF PORT "ddram_clk_p" IO_TYPE=SSTL135D_I; +LOCATE COMP "ddram_cke" SITE "D18"; +IOBUF PORT "ddram_cke" SLEWRATE=FAST; +IOBUF PORT "ddram_cke" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_odt" SITE "C13"; +IOBUF PORT "ddram_odt" SLEWRATE=FAST; +IOBUF PORT "ddram_odt" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_reset_n" SITE "L18"; +IOBUF PORT "ddram_reset_n" SLEWRATE=FAST; +IOBUF PORT "ddram_reset_n" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_vccio[0]" SITE "K16"; +IOBUF PORT "ddram_vccio[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[0]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_vccio[1]" SITE "D17"; +IOBUF PORT "ddram_vccio[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[1]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_vccio[2]" SITE "K15"; +IOBUF PORT "ddram_vccio[2]" SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[2]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_vccio[3]" SITE "K17"; +IOBUF PORT "ddram_vccio[3]" SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[3]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_vccio[4]" SITE "B18"; +IOBUF PORT "ddram_vccio[4]" SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[4]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_vccio[5]" SITE "C6"; +IOBUF PORT "ddram_vccio[5]" SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[5]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_gnd[0]" SITE "L15"; +IOBUF PORT "ddram_gnd[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_gnd[0]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_gnd[1]" SITE "L16"; +IOBUF PORT "ddram_gnd[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_gnd[1]" IO_TYPE=SSTL135_II; +LOCATE COMP "rgb_led0_r" SITE "K4"; +IOBUF PORT "rgb_led0_r" IO_TYPE=LVCMOS33; +LOCATE COMP "rgb_led0_g" SITE "M3"; +IOBUF PORT "rgb_led0_g" IO_TYPE=LVCMOS33; +LOCATE COMP "rgb_led0_b" SITE "J3"; +IOBUF PORT "rgb_led0_b" IO_TYPE=LVCMOS33; +LOCATE COMP "gpio_0" SITE "N17"; +IOBUF PORT "gpio_0" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_0" PULLMODE=DOWN; +LOCATE COMP "gpio_1" SITE "M18"; +IOBUF PORT "gpio_1" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_1" PULLMODE=DOWN; +LOCATE COMP "gpio_5" SITE "B10"; +IOBUF PORT "gpio_5" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_5" PULLMODE=DOWN; +LOCATE COMP "gpio_6" SITE "B9"; +IOBUF PORT "gpio_6" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_6" PULLMODE=DOWN; +LOCATE COMP "gpio_9" SITE "C8"; +IOBUF PORT "gpio_9" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_9" PULLMODE=DOWN; +LOCATE COMP "gpio_10" SITE "B8"; +IOBUF PORT "gpio_10" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_10" PULLMODE=DOWN; +LOCATE COMP "gpio_11" SITE "A8"; +IOBUF PORT "gpio_11" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_11" PULLMODE=DOWN; +LOCATE COMP "gpio_12" SITE "H2"; +IOBUF PORT "gpio_12" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_12" PULLMODE=DOWN; +LOCATE COMP "gpio_13" SITE "J2"; +IOBUF PORT "gpio_13" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_13" PULLMODE=DOWN; +LOCATE COMP "gpio_a0" SITE "L4"; +IOBUF PORT "gpio_a0" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_a0" PULLMODE=DOWN; +LOCATE COMP "gpio_a1" SITE "N3"; +IOBUF PORT "gpio_a1" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_a1" PULLMODE=DOWN; +LOCATE COMP "gpio_a2" SITE "N4"; +IOBUF PORT "gpio_a2" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_a2" PULLMODE=DOWN; +LOCATE COMP "gpio_a3" SITE "H4"; +IOBUF PORT "gpio_a3" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_a3" PULLMODE=DOWN; +LOCATE COMP "usr_btn" SITE "J17"; +IOBUF PORT "usr_btn" IO_TYPE=SSTL135_I; +LOCATE COMP "rst_n" SITE "V17"; +IOBUF PORT "rst_n" IO_TYPE=LVCMOS33; +LOCATE COMP "spiflash4x_cs_n" SITE "U17"; +IOBUF PORT "spiflash4x_cs_n" IO_TYPE=LVCMOS33; +LOCATE COMP "spiflash4x_dq[0]" SITE "U18"; +IOBUF PORT "spiflash4x_dq[0]" IO_TYPE=LVCMOS33; +LOCATE COMP "spiflash4x_dq[1]" SITE "T18"; +IOBUF PORT "spiflash4x_dq[1]" IO_TYPE=LVCMOS33; +LOCATE COMP "spiflash4x_dq[2]" SITE "R18"; +IOBUF PORT "spiflash4x_dq[2]" IO_TYPE=LVCMOS33; +LOCATE COMP "spiflash4x_dq[3]" SITE "N18"; +IOBUF PORT "spiflash4x_dq[3]" IO_TYPE=LVCMOS33; +LOCATE COMP "usb_d_p" SITE "N1"; +IOBUF PORT "usb_d_p" IO_TYPE=LVCMOS33; +LOCATE COMP "usb_d_n" SITE "M2"; +IOBUF PORT "usb_d_n" IO_TYPE=LVCMOS33; +LOCATE COMP "usb_pullup" SITE "N2"; +IOBUF PORT "usb_pullup" IO_TYPE=LVCMOS33; diff --git a/verilog/alu/v1/tbalu.cpp b/verilog/alu/v1/tbalu.cpp new file mode 100644 index 0000000..b3947f8 --- /dev/null +++ b/verilog/alu/v1/tbalu.cpp @@ -0,0 +1,45 @@ +#include <stdlib.h> +#include <iostream> +#include <verilated.h> +#include <verilated_vcd_c.h> +#include "Valu.h" +#include "aluOp.h" +#define OP SRA +#define OPSTR "SRA" +#define SIGN "SRA" +#define LOWER -10 +#define UPPER 0 + +vluint64_t sim_time = 0; + +int main(int argc, char** argv, char** env) { + Valu *dut = new Valu; + + Verilated::traceEverOn(true); + VerilatedVcdC *m_trace = new VerilatedVcdC; + dut->trace(m_trace, 5); + m_trace->open("waveform.vcd"); + + dut->op = OP; + for (dut->in1 = LOWER; (int) dut->in1 < UPPER; dut->in1++) { + for (dut->in2 = 0; (int) dut->in2 < 10; dut->in2++) { + dut->eval(); + std::cout << OPSTR << ": " << (int) dut->in1 << " " << SIGN << " " << (int) dut->in2 << " = " << (int) dut->out << "\n"; + sim_time++; + m_trace->dump(sim_time); + } + } + + for (dut->in1 = 1; (int) dut->in1 < 10; dut->in1++) { + for (dut->in2 = 0; (int) dut->in2 < 10; dut->in2++) { + dut->eval(); + std::cout << OPSTR << ": " << dut->in1 << " " << SIGN << " " << dut->in2 << " = " << dut->out << "\n"; + sim_time++; + m_trace->dump(sim_time); + } + } + + m_trace->close(); + delete dut; + exit(EXIT_SUCCESS); +} diff --git a/verilog/alu/v2/Makefile b/verilog/alu/v2/Makefile new file mode 100644 index 0000000..6de97ff --- /dev/null +++ b/verilog/alu/v2/Makefile @@ -0,0 +1,35 @@ +PROJ=alu2 +VERION:=r0.2 +RM = rm -rf +COPY = cp -a +PATH_SEP = / + + +crab: ${PROJ}.dfu + +dfu: ${PROJ}.dfu + dfu-util -D $< + + +%.json: %.v + yosys -p "read_verilog $<; synth_ecp5 -top ${PROJ} -json $@" + +%_out.config: %.json + nextpnr-ecp5 --json $< --textcfg $@ --25k --package CSFBGA285 --lpf crab.pcf + +%.bit: %_out.config + ecppack --compress --freq 38.8 --input $< --bit $@ + +%.dfu : %.bit + $(COPY) $< $@ + dfu-suffix -v 1209 -p 5af0 -a $@ + +sim: + verilator -Wall --cc --exe --build tbalu.cpp alu.v --trace && ./obj_dir/Valu > out +simclean: + rm -rf obj_dir/* out + +clean: + $(RM) -f ${PROJ}.bit ${PROJ}_out.config ${PROJ}.json ${PROJ}.dfu + +.PHONY: prog clean diff --git a/verilog/alu/v2/alu2.v b/verilog/alu/v2/alu2.v new file mode 100644 index 0000000..d7a0324 --- /dev/null +++ b/verilog/alu/v2/alu2.v @@ -0,0 +1,40 @@ +`default_nettype none +`timescale 1us/1ns + +`include "aluOp.vh" + +module alu2 +( +input wire [31:0] in1, +input wire[31:0] in2, +input wire[3:0] op, +output wire[31:0] out +); + + +wire [31:0] diff = in1 - in2; +reg [31:0] result; + +always @ (*) +begin + case (op) + `ADD: result = in1 + in2; + `SUB: result = diff; + `XOR: result = in1 ^ in2; + `OR: result = in1 | in2; + `AND: result = in1 & in2; + `SLL: result = in1 << in2; + `SRL: result = in1 >> in2; + `SLTU: result = (in1 < in2 ? 32'b1 : 32'b0); + `NONE: result = in1; + `SLT: result = (in1[31] == in2[31] ? (diff[31] == 1'b0 ? 32'b0 : 32'b1) : (in1[31] == 1'b1 ? 32'b1 : 32'b0) ); + `SRA: result = (in1 >> in2) | (in1[31] == 1'b0 ? 32'b0 : + 32'hFFFFFFFF << ((in2[4] ? 0 : 5'b10000) + (in2[3] ? 0 : 5'b01000) + + (in2[2] ? 0 : 5'b00100) + (in2[1] ? 0 : 5'b00010) + (in2[0] ? 0 : 5'b00001)) + ); + default: result = 32'b0; + endcase +end + +assign out = result; +endmodule diff --git a/verilog/alu/v2/aluOp.h b/verilog/alu/v2/aluOp.h new file mode 100644 index 0000000..999dac2 --- /dev/null +++ b/verilog/alu/v2/aluOp.h @@ -0,0 +1,16 @@ +#ifndef ALU_OP +#define ALU_OP + +#define ADD 0 +#define SUB 8 +#define XOR 4 +#define OR 6 +#define AND 7 +#define SLL 1 +#define SRL 5 +#define SRA 13 +#define SLT 2 +#define SLTU 3 +#define NONE 15 + +#endif diff --git a/verilog/alu/v2/aluOp.vh b/verilog/alu/v2/aluOp.vh new file mode 100644 index 0000000..b6e916f --- /dev/null +++ b/verilog/alu/v2/aluOp.vh @@ -0,0 +1,16 @@ +`ifndef ALU_OP +`define ALU_OP + +`define ADD 4'b0000 +`define SUB 4'b1000 +`define XOR 4'b0100 +`define OR 4'b0110 +`define AND 4'b0111 +`define SLL 4'b0001 +`define SRL 4'b0101 +`define SRA 4'b1101 +`define SLT 4'b0010 +`define SLTU 4'b0011 +`define NONE 4'b1111 + +`endif diff --git a/verilog/alu/v2/crab.pcf b/verilog/alu/v2/crab.pcf new file mode 100644 index 0000000..c0d91c5 --- /dev/null +++ b/verilog/alu/v2/crab.pcf @@ -0,0 +1,254 @@ +LOCATE COMP "clk48" SITE "A9"; +IOBUF PORT "clk48" IO_TYPE=LVCMOS33; +FREQUENCY PORT "clk48" 48.0 MHz; + +LOCATE COMP "ddram_a[0]" SITE "C4"; +IOBUF PORT "ddram_a[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[0]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[1]" SITE "D2"; +IOBUF PORT "ddram_a[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[1]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[2]" SITE "D3"; +IOBUF PORT "ddram_a[2]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[2]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[3]" SITE "A3"; +IOBUF PORT "ddram_a[3]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[3]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[4]" SITE "A4"; +IOBUF PORT "ddram_a[4]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[4]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[5]" SITE "D4"; +IOBUF PORT "ddram_a[5]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[5]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[6]" SITE "C3"; +IOBUF PORT "ddram_a[6]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[6]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[7]" SITE "B2"; +IOBUF PORT "ddram_a[7]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[7]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[8]" SITE "B1"; +IOBUF PORT "ddram_a[8]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[8]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[9]" SITE "D1"; +IOBUF PORT "ddram_a[9]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[9]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[10]" SITE "A7"; +IOBUF PORT "ddram_a[10]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[10]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[11]" SITE "C2"; +IOBUF PORT "ddram_a[11]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[11]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[12]" SITE "B6"; +IOBUF PORT "ddram_a[12]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[12]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[13]" SITE "C1"; +IOBUF PORT "ddram_a[13]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[13]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[14]" SITE "A2"; +IOBUF PORT "ddram_a[14]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[14]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[15]" SITE "C7"; +IOBUF PORT "ddram_a[15]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[15]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_ba[0]" SITE "D6"; +IOBUF PORT "ddram_ba[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_ba[0]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_ba[1]" SITE "B7"; +IOBUF PORT "ddram_ba[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_ba[1]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_ba[2]" SITE "A6"; +IOBUF PORT "ddram_ba[2]" SLEWRATE=FAST; +IOBUF PORT "ddram_ba[2]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_ras_n" SITE "C12"; +IOBUF PORT "ddram_ras_n" SLEWRATE=FAST; +IOBUF PORT "ddram_ras_n" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_cas_n" SITE "D13"; +IOBUF PORT "ddram_cas_n" SLEWRATE=FAST; +IOBUF PORT "ddram_cas_n" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_we_n" SITE "B12"; +IOBUF PORT "ddram_we_n" SLEWRATE=FAST; +IOBUF PORT "ddram_we_n" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_cs_n" SITE "A12"; +IOBUF PORT "ddram_cs_n" SLEWRATE=FAST; +IOBUF PORT "ddram_cs_n" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_dm[0]" SITE "D16"; +IOBUF PORT "ddram_dm[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_dm[0]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_dm[1]" SITE "G16"; +IOBUF PORT "ddram_dm[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_dm[1]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_dq[0]" SITE "C17"; +IOBUF PORT "ddram_dq[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[0]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[0]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[1]" SITE "D15"; +IOBUF PORT "ddram_dq[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[1]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[1]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[2]" SITE "B17"; +IOBUF PORT "ddram_dq[2]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[2]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[2]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[3]" SITE "C16"; +IOBUF PORT "ddram_dq[3]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[3]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[3]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[4]" SITE "A15"; +IOBUF PORT "ddram_dq[4]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[4]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[4]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[5]" SITE "B13"; +IOBUF PORT "ddram_dq[5]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[5]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[5]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[6]" SITE "A17"; +IOBUF PORT "ddram_dq[6]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[6]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[6]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[7]" SITE "A13"; +IOBUF PORT "ddram_dq[7]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[7]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[7]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[8]" SITE "F17"; +IOBUF PORT "ddram_dq[8]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[8]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[8]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[9]" SITE "F16"; +IOBUF PORT "ddram_dq[9]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[9]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[9]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[10]" SITE "G15"; +IOBUF PORT "ddram_dq[10]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[10]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[10]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[11]" SITE "F15"; +IOBUF PORT "ddram_dq[11]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[11]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[11]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[12]" SITE "J16"; +IOBUF PORT "ddram_dq[12]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[12]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[12]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[13]" SITE "C18"; +IOBUF PORT "ddram_dq[13]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[13]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[13]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[14]" SITE "H16"; +IOBUF PORT "ddram_dq[14]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[14]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[14]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[15]" SITE "F18"; +IOBUF PORT "ddram_dq[15]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[15]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[15]" TERMINATION=OFF; +LOCATE COMP "ddram_dqs_p[0]" SITE "B15"; +IOBUF PORT "ddram_dqs_p[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_dqs_p[0]" IO_TYPE=SSTL135D_I; +IOBUF PORT "ddram_dqs_p[0]" TERMINATION=OFF; +IOBUF PORT "ddram_dqs_p[0]" DIFFRESISTOR=100; +LOCATE COMP "ddram_dqs_p[1]" SITE "G18"; +IOBUF PORT "ddram_dqs_p[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_dqs_p[1]" IO_TYPE=SSTL135D_I; +IOBUF PORT "ddram_dqs_p[1]" TERMINATION=OFF; +IOBUF PORT "ddram_dqs_p[1]" DIFFRESISTOR=100; +LOCATE COMP "ddram_clk_p" SITE "J18"; +IOBUF PORT "ddram_clk_p" SLEWRATE=FAST; +IOBUF PORT "ddram_clk_p" IO_TYPE=SSTL135D_I; +LOCATE COMP "ddram_cke" SITE "D18"; +IOBUF PORT "ddram_cke" SLEWRATE=FAST; +IOBUF PORT "ddram_cke" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_odt" SITE "C13"; +IOBUF PORT "ddram_odt" SLEWRATE=FAST; +IOBUF PORT "ddram_odt" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_reset_n" SITE "L18"; +IOBUF PORT "ddram_reset_n" SLEWRATE=FAST; +IOBUF PORT "ddram_reset_n" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_vccio[0]" SITE "K16"; +IOBUF PORT "ddram_vccio[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[0]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_vccio[1]" SITE "D17"; +IOBUF PORT "ddram_vccio[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[1]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_vccio[2]" SITE "K15"; +IOBUF PORT "ddram_vccio[2]" SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[2]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_vccio[3]" SITE "K17"; +IOBUF PORT "ddram_vccio[3]" SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[3]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_vccio[4]" SITE "B18"; +IOBUF PORT "ddram_vccio[4]" SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[4]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_vccio[5]" SITE "C6"; +IOBUF PORT "ddram_vccio[5]" SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[5]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_gnd[0]" SITE "L15"; +IOBUF PORT "ddram_gnd[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_gnd[0]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_gnd[1]" SITE "L16"; +IOBUF PORT "ddram_gnd[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_gnd[1]" IO_TYPE=SSTL135_II; +LOCATE COMP "rgb_led0_r" SITE "K4"; +IOBUF PORT "rgb_led0_r" IO_TYPE=LVCMOS33; +LOCATE COMP "rgb_led0_g" SITE "M3"; +IOBUF PORT "rgb_led0_g" IO_TYPE=LVCMOS33; +LOCATE COMP "rgb_led0_b" SITE "J3"; +IOBUF PORT "rgb_led0_b" IO_TYPE=LVCMOS33; +LOCATE COMP "gpio_0" SITE "N17"; +IOBUF PORT "gpio_0" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_0" PULLMODE=DOWN; +LOCATE COMP "gpio_1" SITE "M18"; +IOBUF PORT "gpio_1" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_1" PULLMODE=DOWN; +LOCATE COMP "gpio_5" SITE "B10"; +IOBUF PORT "gpio_5" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_5" PULLMODE=DOWN; +LOCATE COMP "gpio_6" SITE "B9"; +IOBUF PORT "gpio_6" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_6" PULLMODE=DOWN; +LOCATE COMP "gpio_9" SITE "C8"; +IOBUF PORT "gpio_9" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_9" PULLMODE=DOWN; +LOCATE COMP "gpio_10" SITE "B8"; +IOBUF PORT "gpio_10" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_10" PULLMODE=DOWN; +LOCATE COMP "gpio_11" SITE "A8"; +IOBUF PORT "gpio_11" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_11" PULLMODE=DOWN; +LOCATE COMP "gpio_12" SITE "H2"; +IOBUF PORT "gpio_12" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_12" PULLMODE=DOWN; +LOCATE COMP "gpio_13" SITE "J2"; +IOBUF PORT "gpio_13" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_13" PULLMODE=DOWN; +LOCATE COMP "gpio_a0" SITE "L4"; +IOBUF PORT "gpio_a0" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_a0" PULLMODE=DOWN; +LOCATE COMP "gpio_a1" SITE "N3"; +IOBUF PORT "gpio_a1" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_a1" PULLMODE=DOWN; +LOCATE COMP "gpio_a2" SITE "N4"; +IOBUF PORT "gpio_a2" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_a2" PULLMODE=DOWN; +LOCATE COMP "gpio_a3" SITE "H4"; +IOBUF PORT "gpio_a3" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_a3" PULLMODE=DOWN; +LOCATE COMP "usr_btn" SITE "J17"; +IOBUF PORT "usr_btn" IO_TYPE=SSTL135_I; +LOCATE COMP "rst_n" SITE "V17"; +IOBUF PORT "rst_n" IO_TYPE=LVCMOS33; +LOCATE COMP "spiflash4x_cs_n" SITE "U17"; +IOBUF PORT "spiflash4x_cs_n" IO_TYPE=LVCMOS33; +LOCATE COMP "spiflash4x_dq[0]" SITE "U18"; +IOBUF PORT "spiflash4x_dq[0]" IO_TYPE=LVCMOS33; +LOCATE COMP "spiflash4x_dq[1]" SITE "T18"; +IOBUF PORT "spiflash4x_dq[1]" IO_TYPE=LVCMOS33; +LOCATE COMP "spiflash4x_dq[2]" SITE "R18"; +IOBUF PORT "spiflash4x_dq[2]" IO_TYPE=LVCMOS33; +LOCATE COMP "spiflash4x_dq[3]" SITE "N18"; +IOBUF PORT "spiflash4x_dq[3]" IO_TYPE=LVCMOS33; +LOCATE COMP "usb_d_p" SITE "N1"; +IOBUF PORT "usb_d_p" IO_TYPE=LVCMOS33; +LOCATE COMP "usb_d_n" SITE "M2"; +IOBUF PORT "usb_d_n" IO_TYPE=LVCMOS33; +LOCATE COMP "usb_pullup" SITE "N2"; +IOBUF PORT "usb_pullup" IO_TYPE=LVCMOS33; diff --git a/verilog/alu/v2/tbalu.cpp b/verilog/alu/v2/tbalu.cpp new file mode 100644 index 0000000..b3947f8 --- /dev/null +++ b/verilog/alu/v2/tbalu.cpp @@ -0,0 +1,45 @@ +#include <stdlib.h> +#include <iostream> +#include <verilated.h> +#include <verilated_vcd_c.h> +#include "Valu.h" +#include "aluOp.h" +#define OP SRA +#define OPSTR "SRA" +#define SIGN "SRA" +#define LOWER -10 +#define UPPER 0 + +vluint64_t sim_time = 0; + +int main(int argc, char** argv, char** env) { + Valu *dut = new Valu; + + Verilated::traceEverOn(true); + VerilatedVcdC *m_trace = new VerilatedVcdC; + dut->trace(m_trace, 5); + m_trace->open("waveform.vcd"); + + dut->op = OP; + for (dut->in1 = LOWER; (int) dut->in1 < UPPER; dut->in1++) { + for (dut->in2 = 0; (int) dut->in2 < 10; dut->in2++) { + dut->eval(); + std::cout << OPSTR << ": " << (int) dut->in1 << " " << SIGN << " " << (int) dut->in2 << " = " << (int) dut->out << "\n"; + sim_time++; + m_trace->dump(sim_time); + } + } + + for (dut->in1 = 1; (int) dut->in1 < 10; dut->in1++) { + for (dut->in2 = 0; (int) dut->in2 < 10; dut->in2++) { + dut->eval(); + std::cout << OPSTR << ": " << dut->in1 << " " << SIGN << " " << dut->in2 << " = " << dut->out << "\n"; + sim_time++; + m_trace->dump(sim_time); + } + } + + m_trace->close(); + delete dut; + exit(EXIT_SUCCESS); +} diff --git a/verilog/alu/v3/Makefile b/verilog/alu/v3/Makefile new file mode 100644 index 0000000..11821cb --- /dev/null +++ b/verilog/alu/v3/Makefile @@ -0,0 +1,35 @@ +PROJ=alu3 +VERION:=r0.2 +RM = rm -rf +COPY = cp -a +PATH_SEP = / + + +crab: ${PROJ}.dfu + +dfu: ${PROJ}.dfu + dfu-util -D $< + + +%.json: %.v + yosys -p "read_verilog $<; synth_ecp5 -top ${PROJ} -json $@" + +%_out.config: %.json + nextpnr-ecp5 --json $< --textcfg $@ --25k --package CSFBGA285 --lpf crab.pcf + +%.bit: %_out.config + ecppack --compress --freq 38.8 --input $< --bit $@ + +%.dfu : %.bit + $(COPY) $< $@ + dfu-suffix -v 1209 -p 5af0 -a $@ + +sim: + verilator -Wall --cc --exe --build tbalu.cpp alu.v --trace && ./obj_dir/Valu > out +simclean: + rm -rf obj_dir/* out + +clean: + $(RM) -f ${PROJ}.bit ${PROJ}_out.config ${PROJ}.json ${PROJ}.dfu + +.PHONY: prog clean diff --git a/verilog/alu/v3/alu3.v b/verilog/alu/v3/alu3.v new file mode 100644 index 0000000..556b226 --- /dev/null +++ b/verilog/alu/v3/alu3.v @@ -0,0 +1,41 @@ +`default_nettype none +`timescale 1us/1ns + +`include "aluOp.vh" + +module alu3 +( +input wire [31:0] alu_in_1, +input wire[31:0] alu_in_2, +input wire[3:0] alu_op_i, +output wire[31:0] alu_output +); + + +wire [31:0] diff = alu_in_1 - alu_in_1; +reg [31:0] result; + +always @ (*) +begin + case(alu_op_i) + `ADD: result = alu_in_1 + alu_in_2; + `SUB: result = diff; + `XOR: result = alu_in_1 ^ alu_in_2; + `OR: result = alu_in_1 | alu_in_2; + `AND: result = alu_in_1 & alu_in_2; + `SLL: result = alu_in_1 >> alu_in_2; + `SRL: result = alu_in_1 << alu_in_2; + `SLTU: result = (alu_in_1 < alu_in_2 ? 32'b1 : 32'b0); + `NONE: result = alu_in_1; + `SLT: result = (alu_in_1[31] == alu_in_2[31] ? (diff[31] == 1'b0 ? 32'b0 : 32'b1) : (alu_in_1[31] == 1'b1 ? 32'b1 : 32'b0)); + `SRA: result = + (alu_in_1 >> alu_in_2) | + (alu_in_1[31] == 1'b0 ? 32'b0 : + (32'hFFFFFFFF << {~alu_in_2[4], ~alu_in_2[3], ~alu_in_2[2], ~alu_in_2[1], ~alu_in_2[0]})); + default: result = 32'b0; + endcase +end + +assign alu_output = result; + +endmodule diff --git a/verilog/alu/v3/aluOp.h b/verilog/alu/v3/aluOp.h new file mode 100644 index 0000000..999dac2 --- /dev/null +++ b/verilog/alu/v3/aluOp.h @@ -0,0 +1,16 @@ +#ifndef ALU_OP +#define ALU_OP + +#define ADD 0 +#define SUB 8 +#define XOR 4 +#define OR 6 +#define AND 7 +#define SLL 1 +#define SRL 5 +#define SRA 13 +#define SLT 2 +#define SLTU 3 +#define NONE 15 + +#endif diff --git a/verilog/alu/v3/aluOp.vh b/verilog/alu/v3/aluOp.vh new file mode 100644 index 0000000..b6e916f --- /dev/null +++ b/verilog/alu/v3/aluOp.vh @@ -0,0 +1,16 @@ +`ifndef ALU_OP +`define ALU_OP + +`define ADD 4'b0000 +`define SUB 4'b1000 +`define XOR 4'b0100 +`define OR 4'b0110 +`define AND 4'b0111 +`define SLL 4'b0001 +`define SRL 4'b0101 +`define SRA 4'b1101 +`define SLT 4'b0010 +`define SLTU 4'b0011 +`define NONE 4'b1111 + +`endif diff --git a/verilog/alu/v3/crab.pcf b/verilog/alu/v3/crab.pcf new file mode 100644 index 0000000..c0d91c5 --- /dev/null +++ b/verilog/alu/v3/crab.pcf @@ -0,0 +1,254 @@ +LOCATE COMP "clk48" SITE "A9"; +IOBUF PORT "clk48" IO_TYPE=LVCMOS33; +FREQUENCY PORT "clk48" 48.0 MHz; + +LOCATE COMP "ddram_a[0]" SITE "C4"; +IOBUF PORT "ddram_a[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[0]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[1]" SITE "D2"; +IOBUF PORT "ddram_a[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[1]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[2]" SITE "D3"; +IOBUF PORT "ddram_a[2]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[2]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[3]" SITE "A3"; +IOBUF PORT "ddram_a[3]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[3]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[4]" SITE "A4"; +IOBUF PORT "ddram_a[4]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[4]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[5]" SITE "D4"; +IOBUF PORT "ddram_a[5]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[5]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[6]" SITE "C3"; +IOBUF PORT "ddram_a[6]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[6]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[7]" SITE "B2"; +IOBUF PORT "ddram_a[7]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[7]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[8]" SITE "B1"; +IOBUF PORT "ddram_a[8]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[8]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[9]" SITE "D1"; +IOBUF PORT "ddram_a[9]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[9]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[10]" SITE "A7"; +IOBUF PORT "ddram_a[10]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[10]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[11]" SITE "C2"; +IOBUF PORT "ddram_a[11]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[11]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[12]" SITE "B6"; +IOBUF PORT "ddram_a[12]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[12]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[13]" SITE "C1"; +IOBUF PORT "ddram_a[13]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[13]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[14]" SITE "A2"; +IOBUF PORT "ddram_a[14]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[14]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[15]" SITE "C7"; +IOBUF PORT "ddram_a[15]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[15]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_ba[0]" SITE "D6"; +IOBUF PORT "ddram_ba[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_ba[0]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_ba[1]" SITE "B7"; +IOBUF PORT "ddram_ba[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_ba[1]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_ba[2]" SITE "A6"; +IOBUF PORT "ddram_ba[2]" SLEWRATE=FAST; +IOBUF PORT "ddram_ba[2]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_ras_n" SITE "C12"; +IOBUF PORT "ddram_ras_n" SLEWRATE=FAST; +IOBUF PORT "ddram_ras_n" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_cas_n" SITE "D13"; +IOBUF PORT "ddram_cas_n" SLEWRATE=FAST; +IOBUF PORT "ddram_cas_n" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_we_n" SITE "B12"; +IOBUF PORT "ddram_we_n" SLEWRATE=FAST; +IOBUF PORT "ddram_we_n" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_cs_n" SITE "A12"; +IOBUF PORT "ddram_cs_n" SLEWRATE=FAST; +IOBUF PORT "ddram_cs_n" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_dm[0]" SITE "D16"; +IOBUF PORT "ddram_dm[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_dm[0]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_dm[1]" SITE "G16"; +IOBUF PORT "ddram_dm[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_dm[1]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_dq[0]" SITE "C17"; +IOBUF PORT "ddram_dq[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[0]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[0]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[1]" SITE "D15"; +IOBUF PORT "ddram_dq[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[1]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[1]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[2]" SITE "B17"; +IOBUF PORT "ddram_dq[2]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[2]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[2]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[3]" SITE "C16"; +IOBUF PORT "ddram_dq[3]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[3]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[3]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[4]" SITE "A15"; +IOBUF PORT "ddram_dq[4]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[4]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[4]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[5]" SITE "B13"; +IOBUF PORT "ddram_dq[5]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[5]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[5]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[6]" SITE "A17"; +IOBUF PORT "ddram_dq[6]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[6]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[6]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[7]" SITE "A13"; +IOBUF PORT "ddram_dq[7]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[7]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[7]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[8]" SITE "F17"; +IOBUF PORT "ddram_dq[8]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[8]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[8]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[9]" SITE "F16"; +IOBUF PORT "ddram_dq[9]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[9]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[9]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[10]" SITE "G15"; +IOBUF PORT "ddram_dq[10]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[10]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[10]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[11]" SITE "F15"; +IOBUF PORT "ddram_dq[11]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[11]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[11]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[12]" SITE "J16"; +IOBUF PORT "ddram_dq[12]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[12]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[12]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[13]" SITE "C18"; +IOBUF PORT "ddram_dq[13]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[13]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[13]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[14]" SITE "H16"; +IOBUF PORT "ddram_dq[14]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[14]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[14]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[15]" SITE "F18"; +IOBUF PORT "ddram_dq[15]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[15]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[15]" TERMINATION=OFF; +LOCATE COMP "ddram_dqs_p[0]" SITE "B15"; +IOBUF PORT "ddram_dqs_p[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_dqs_p[0]" IO_TYPE=SSTL135D_I; +IOBUF PORT "ddram_dqs_p[0]" TERMINATION=OFF; +IOBUF PORT "ddram_dqs_p[0]" DIFFRESISTOR=100; +LOCATE COMP "ddram_dqs_p[1]" SITE "G18"; +IOBUF PORT "ddram_dqs_p[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_dqs_p[1]" IO_TYPE=SSTL135D_I; +IOBUF PORT "ddram_dqs_p[1]" TERMINATION=OFF; +IOBUF PORT "ddram_dqs_p[1]" DIFFRESISTOR=100; +LOCATE COMP "ddram_clk_p" SITE "J18"; +IOBUF PORT "ddram_clk_p" SLEWRATE=FAST; +IOBUF PORT "ddram_clk_p" IO_TYPE=SSTL135D_I; +LOCATE COMP "ddram_cke" SITE "D18"; +IOBUF PORT "ddram_cke" SLEWRATE=FAST; +IOBUF PORT "ddram_cke" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_odt" SITE "C13"; +IOBUF PORT "ddram_odt" SLEWRATE=FAST; +IOBUF PORT "ddram_odt" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_reset_n" SITE "L18"; +IOBUF PORT "ddram_reset_n" SLEWRATE=FAST; +IOBUF PORT "ddram_reset_n" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_vccio[0]" SITE "K16"; +IOBUF PORT "ddram_vccio[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[0]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_vccio[1]" SITE "D17"; +IOBUF PORT "ddram_vccio[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[1]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_vccio[2]" SITE "K15"; +IOBUF PORT "ddram_vccio[2]" SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[2]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_vccio[3]" SITE "K17"; +IOBUF PORT "ddram_vccio[3]" SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[3]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_vccio[4]" SITE "B18"; +IOBUF PORT "ddram_vccio[4]" SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[4]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_vccio[5]" SITE "C6"; +IOBUF PORT "ddram_vccio[5]" SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[5]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_gnd[0]" SITE "L15"; +IOBUF PORT "ddram_gnd[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_gnd[0]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_gnd[1]" SITE "L16"; +IOBUF PORT "ddram_gnd[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_gnd[1]" IO_TYPE=SSTL135_II; +LOCATE COMP "rgb_led0_r" SITE "K4"; +IOBUF PORT "rgb_led0_r" IO_TYPE=LVCMOS33; +LOCATE COMP "rgb_led0_g" SITE "M3"; +IOBUF PORT "rgb_led0_g" IO_TYPE=LVCMOS33; +LOCATE COMP "rgb_led0_b" SITE "J3"; +IOBUF PORT "rgb_led0_b" IO_TYPE=LVCMOS33; +LOCATE COMP "gpio_0" SITE "N17"; +IOBUF PORT "gpio_0" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_0" PULLMODE=DOWN; +LOCATE COMP "gpio_1" SITE "M18"; +IOBUF PORT "gpio_1" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_1" PULLMODE=DOWN; +LOCATE COMP "gpio_5" SITE "B10"; +IOBUF PORT "gpio_5" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_5" PULLMODE=DOWN; +LOCATE COMP "gpio_6" SITE "B9"; +IOBUF PORT "gpio_6" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_6" PULLMODE=DOWN; +LOCATE COMP "gpio_9" SITE "C8"; +IOBUF PORT "gpio_9" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_9" PULLMODE=DOWN; +LOCATE COMP "gpio_10" SITE "B8"; +IOBUF PORT "gpio_10" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_10" PULLMODE=DOWN; +LOCATE COMP "gpio_11" SITE "A8"; +IOBUF PORT "gpio_11" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_11" PULLMODE=DOWN; +LOCATE COMP "gpio_12" SITE "H2"; +IOBUF PORT "gpio_12" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_12" PULLMODE=DOWN; +LOCATE COMP "gpio_13" SITE "J2"; +IOBUF PORT "gpio_13" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_13" PULLMODE=DOWN; +LOCATE COMP "gpio_a0" SITE "L4"; +IOBUF PORT "gpio_a0" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_a0" PULLMODE=DOWN; +LOCATE COMP "gpio_a1" SITE "N3"; +IOBUF PORT "gpio_a1" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_a1" PULLMODE=DOWN; +LOCATE COMP "gpio_a2" SITE "N4"; +IOBUF PORT "gpio_a2" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_a2" PULLMODE=DOWN; +LOCATE COMP "gpio_a3" SITE "H4"; +IOBUF PORT "gpio_a3" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_a3" PULLMODE=DOWN; +LOCATE COMP "usr_btn" SITE "J17"; +IOBUF PORT "usr_btn" IO_TYPE=SSTL135_I; +LOCATE COMP "rst_n" SITE "V17"; +IOBUF PORT "rst_n" IO_TYPE=LVCMOS33; +LOCATE COMP "spiflash4x_cs_n" SITE "U17"; +IOBUF PORT "spiflash4x_cs_n" IO_TYPE=LVCMOS33; +LOCATE COMP "spiflash4x_dq[0]" SITE "U18"; +IOBUF PORT "spiflash4x_dq[0]" IO_TYPE=LVCMOS33; +LOCATE COMP "spiflash4x_dq[1]" SITE "T18"; +IOBUF PORT "spiflash4x_dq[1]" IO_TYPE=LVCMOS33; +LOCATE COMP "spiflash4x_dq[2]" SITE "R18"; +IOBUF PORT "spiflash4x_dq[2]" IO_TYPE=LVCMOS33; +LOCATE COMP "spiflash4x_dq[3]" SITE "N18"; +IOBUF PORT "spiflash4x_dq[3]" IO_TYPE=LVCMOS33; +LOCATE COMP "usb_d_p" SITE "N1"; +IOBUF PORT "usb_d_p" IO_TYPE=LVCMOS33; +LOCATE COMP "usb_d_n" SITE "M2"; +IOBUF PORT "usb_d_n" IO_TYPE=LVCMOS33; +LOCATE COMP "usb_pullup" SITE "N2"; +IOBUF PORT "usb_pullup" IO_TYPE=LVCMOS33; diff --git a/verilog/alu/v3/tbalu.cpp b/verilog/alu/v3/tbalu.cpp new file mode 100644 index 0000000..b3947f8 --- /dev/null +++ b/verilog/alu/v3/tbalu.cpp @@ -0,0 +1,45 @@ +#include <stdlib.h> +#include <iostream> +#include <verilated.h> +#include <verilated_vcd_c.h> +#include "Valu.h" +#include "aluOp.h" +#define OP SRA +#define OPSTR "SRA" +#define SIGN "SRA" +#define LOWER -10 +#define UPPER 0 + +vluint64_t sim_time = 0; + +int main(int argc, char** argv, char** env) { + Valu *dut = new Valu; + + Verilated::traceEverOn(true); + VerilatedVcdC *m_trace = new VerilatedVcdC; + dut->trace(m_trace, 5); + m_trace->open("waveform.vcd"); + + dut->op = OP; + for (dut->in1 = LOWER; (int) dut->in1 < UPPER; dut->in1++) { + for (dut->in2 = 0; (int) dut->in2 < 10; dut->in2++) { + dut->eval(); + std::cout << OPSTR << ": " << (int) dut->in1 << " " << SIGN << " " << (int) dut->in2 << " = " << (int) dut->out << "\n"; + sim_time++; + m_trace->dump(sim_time); + } + } + + for (dut->in1 = 1; (int) dut->in1 < 10; dut->in1++) { + for (dut->in2 = 0; (int) dut->in2 < 10; dut->in2++) { + dut->eval(); + std::cout << OPSTR << ": " << dut->in1 << " " << SIGN << " " << dut->in2 << " = " << dut->out << "\n"; + sim_time++; + m_trace->dump(sim_time); + } + } + + m_trace->close(); + delete dut; + exit(EXIT_SUCCESS); +} diff --git a/verilog/alu/v4/Makefile b/verilog/alu/v4/Makefile new file mode 100644 index 0000000..e3d78e9 --- /dev/null +++ b/verilog/alu/v4/Makefile @@ -0,0 +1,35 @@ +PROJ=alu4 +VERION:=r0.2 +RM = rm -rf +COPY = cp -a +PATH_SEP = / + + +crab: ${PROJ}.dfu + +dfu: ${PROJ}.dfu + dfu-util -D $< + + +%.json: %.v + yosys -p "read_verilog $<; synth_ecp5 -top ${PROJ} -json $@" + +%_out.config: %.json + nextpnr-ecp5 --json $< --textcfg $@ --25k --package CSFBGA285 --lpf crab.pcf + +%.bit: %_out.config + ecppack --compress --freq 38.8 --input $< --bit $@ + +%.dfu : %.bit + $(COPY) $< $@ + dfu-suffix -v 1209 -p 5af0 -a $@ + +sim: + verilator -Wall --cc --exe --build tbalu.cpp alu.v --trace && ./obj_dir/Valu > out +simclean: + rm -rf obj_dir/* out + +clean: + $(RM) -f ${PROJ}.bit ${PROJ}_out.config ${PROJ}.json ${PROJ}.dfu + +.PHONY: prog clean diff --git a/verilog/alu/v4/alu4.v b/verilog/alu/v4/alu4.v new file mode 100644 index 0000000..a7b9892 --- /dev/null +++ b/verilog/alu/v4/alu4.v @@ -0,0 +1,30 @@ +`default_nettype none +`timescale 1us/1ns + +`include "aluOp.vh" + +module alu4 +( +input wire [31:0] alu_in_1, +input wire[31:0] alu_in_2, +input wire[3:0] alu_op_i, +output wire[31:0] alu_output +); + + +wire [31:0] diff = alu_in_1 - alu_in_2; + +assign alu_output = + alu_op_i == `ADD ? alu_in_1 + alu_in_2 : + alu_op_i == `SUB ? diff : + alu_op_i == `XOR ? alu_in_1 ^ alu_in_2 : + alu_op_i == `OR ? alu_in_1 | alu_in_2 : + alu_op_i == `AND ? alu_in_1 & alu_in_2 : + alu_op_i == `SLL ? alu_in_1 << alu_in_2 : + alu_op_i == `SRL ? alu_in_1 >> alu_in_2 : + alu_op_i == `SLTU ? (alu_in_1 < alu_in_2 ? 32'b1 : 32'b0) : + alu_op_i == `NONE ? alu_in_1 : + alu_op_i == `SLT ? (alu_in_1[31] == alu_in_2[31] ? (diff[31] == 1'b0 ? 32'b0 : 32'b1) : (alu_in_1[31] == 1'b1 ? 32'b1 : 32'b0) ) : + alu_op_i == `SRA ? (alu_in_1 >> alu_in_2) | (alu_in_1[31] == 1'b0 ? 32'b0 : (32'hFFFFFFFF << {~alu_in_2[4], ~alu_in_2[3], ~alu_in_2[2], ~alu_in_2[1], ~alu_in_2[0]})) : + 32'b0; +endmodule diff --git a/verilog/alu/v4/aluOp.h b/verilog/alu/v4/aluOp.h new file mode 100644 index 0000000..999dac2 --- /dev/null +++ b/verilog/alu/v4/aluOp.h @@ -0,0 +1,16 @@ +#ifndef ALU_OP +#define ALU_OP + +#define ADD 0 +#define SUB 8 +#define XOR 4 +#define OR 6 +#define AND 7 +#define SLL 1 +#define SRL 5 +#define SRA 13 +#define SLT 2 +#define SLTU 3 +#define NONE 15 + +#endif diff --git a/verilog/alu/v4/aluOp.vh b/verilog/alu/v4/aluOp.vh new file mode 100644 index 0000000..b6e916f --- /dev/null +++ b/verilog/alu/v4/aluOp.vh @@ -0,0 +1,16 @@ +`ifndef ALU_OP +`define ALU_OP + +`define ADD 4'b0000 +`define SUB 4'b1000 +`define XOR 4'b0100 +`define OR 4'b0110 +`define AND 4'b0111 +`define SLL 4'b0001 +`define SRL 4'b0101 +`define SRA 4'b1101 +`define SLT 4'b0010 +`define SLTU 4'b0011 +`define NONE 4'b1111 + +`endif diff --git a/verilog/alu/v4/crab.pcf b/verilog/alu/v4/crab.pcf new file mode 100644 index 0000000..c0d91c5 --- /dev/null +++ b/verilog/alu/v4/crab.pcf @@ -0,0 +1,254 @@ +LOCATE COMP "clk48" SITE "A9"; +IOBUF PORT "clk48" IO_TYPE=LVCMOS33; +FREQUENCY PORT "clk48" 48.0 MHz; + +LOCATE COMP "ddram_a[0]" SITE "C4"; +IOBUF PORT "ddram_a[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[0]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[1]" SITE "D2"; +IOBUF PORT "ddram_a[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[1]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[2]" SITE "D3"; +IOBUF PORT "ddram_a[2]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[2]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[3]" SITE "A3"; +IOBUF PORT "ddram_a[3]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[3]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[4]" SITE "A4"; +IOBUF PORT "ddram_a[4]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[4]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[5]" SITE "D4"; +IOBUF PORT "ddram_a[5]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[5]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[6]" SITE "C3"; +IOBUF PORT "ddram_a[6]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[6]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[7]" SITE "B2"; +IOBUF PORT "ddram_a[7]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[7]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[8]" SITE "B1"; +IOBUF PORT "ddram_a[8]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[8]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[9]" SITE "D1"; +IOBUF PORT "ddram_a[9]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[9]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[10]" SITE "A7"; +IOBUF PORT "ddram_a[10]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[10]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[11]" SITE "C2"; +IOBUF PORT "ddram_a[11]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[11]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[12]" SITE "B6"; +IOBUF PORT "ddram_a[12]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[12]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[13]" SITE "C1"; +IOBUF PORT "ddram_a[13]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[13]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[14]" SITE "A2"; +IOBUF PORT "ddram_a[14]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[14]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[15]" SITE "C7"; +IOBUF PORT "ddram_a[15]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[15]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_ba[0]" SITE "D6"; +IOBUF PORT "ddram_ba[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_ba[0]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_ba[1]" SITE "B7"; +IOBUF PORT "ddram_ba[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_ba[1]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_ba[2]" SITE "A6"; +IOBUF PORT "ddram_ba[2]" SLEWRATE=FAST; +IOBUF PORT "ddram_ba[2]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_ras_n" SITE "C12"; +IOBUF PORT "ddram_ras_n" SLEWRATE=FAST; +IOBUF PORT "ddram_ras_n" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_cas_n" SITE "D13"; +IOBUF PORT "ddram_cas_n" SLEWRATE=FAST; +IOBUF PORT "ddram_cas_n" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_we_n" SITE "B12"; +IOBUF PORT "ddram_we_n" SLEWRATE=FAST; +IOBUF PORT "ddram_we_n" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_cs_n" SITE "A12"; +IOBUF PORT "ddram_cs_n" SLEWRATE=FAST; +IOBUF PORT "ddram_cs_n" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_dm[0]" SITE "D16"; +IOBUF PORT "ddram_dm[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_dm[0]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_dm[1]" SITE "G16"; +IOBUF PORT "ddram_dm[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_dm[1]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_dq[0]" SITE "C17"; +IOBUF PORT "ddram_dq[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[0]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[0]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[1]" SITE "D15"; +IOBUF PORT "ddram_dq[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[1]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[1]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[2]" SITE "B17"; +IOBUF PORT "ddram_dq[2]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[2]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[2]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[3]" SITE "C16"; +IOBUF PORT "ddram_dq[3]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[3]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[3]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[4]" SITE "A15"; +IOBUF PORT "ddram_dq[4]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[4]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[4]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[5]" SITE "B13"; +IOBUF PORT "ddram_dq[5]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[5]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[5]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[6]" SITE "A17"; +IOBUF PORT "ddram_dq[6]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[6]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[6]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[7]" SITE "A13"; +IOBUF PORT "ddram_dq[7]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[7]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[7]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[8]" SITE "F17"; +IOBUF PORT "ddram_dq[8]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[8]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[8]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[9]" SITE "F16"; +IOBUF PORT "ddram_dq[9]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[9]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[9]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[10]" SITE "G15"; +IOBUF PORT "ddram_dq[10]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[10]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[10]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[11]" SITE "F15"; +IOBUF PORT "ddram_dq[11]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[11]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[11]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[12]" SITE "J16"; +IOBUF PORT "ddram_dq[12]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[12]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[12]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[13]" SITE "C18"; +IOBUF PORT "ddram_dq[13]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[13]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[13]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[14]" SITE "H16"; +IOBUF PORT "ddram_dq[14]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[14]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[14]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[15]" SITE "F18"; +IOBUF PORT "ddram_dq[15]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[15]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[15]" TERMINATION=OFF; +LOCATE COMP "ddram_dqs_p[0]" SITE "B15"; +IOBUF PORT "ddram_dqs_p[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_dqs_p[0]" IO_TYPE=SSTL135D_I; +IOBUF PORT "ddram_dqs_p[0]" TERMINATION=OFF; +IOBUF PORT "ddram_dqs_p[0]" DIFFRESISTOR=100; +LOCATE COMP "ddram_dqs_p[1]" SITE "G18"; +IOBUF PORT "ddram_dqs_p[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_dqs_p[1]" IO_TYPE=SSTL135D_I; +IOBUF PORT "ddram_dqs_p[1]" TERMINATION=OFF; +IOBUF PORT "ddram_dqs_p[1]" DIFFRESISTOR=100; +LOCATE COMP "ddram_clk_p" SITE "J18"; +IOBUF PORT "ddram_clk_p" SLEWRATE=FAST; +IOBUF PORT "ddram_clk_p" IO_TYPE=SSTL135D_I; +LOCATE COMP "ddram_cke" SITE "D18"; +IOBUF PORT "ddram_cke" SLEWRATE=FAST; +IOBUF PORT "ddram_cke" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_odt" SITE "C13"; +IOBUF PORT "ddram_odt" SLEWRATE=FAST; +IOBUF PORT "ddram_odt" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_reset_n" SITE "L18"; +IOBUF PORT "ddram_reset_n" SLEWRATE=FAST; +IOBUF PORT "ddram_reset_n" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_vccio[0]" SITE "K16"; +IOBUF PORT "ddram_vccio[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[0]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_vccio[1]" SITE "D17"; +IOBUF PORT "ddram_vccio[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[1]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_vccio[2]" SITE "K15"; +IOBUF PORT "ddram_vccio[2]" SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[2]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_vccio[3]" SITE "K17"; +IOBUF PORT "ddram_vccio[3]" SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[3]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_vccio[4]" SITE "B18"; +IOBUF PORT "ddram_vccio[4]" SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[4]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_vccio[5]" SITE "C6"; +IOBUF PORT "ddram_vccio[5]" SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[5]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_gnd[0]" SITE "L15"; +IOBUF PORT "ddram_gnd[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_gnd[0]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_gnd[1]" SITE "L16"; +IOBUF PORT "ddram_gnd[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_gnd[1]" IO_TYPE=SSTL135_II; +LOCATE COMP "rgb_led0_r" SITE "K4"; +IOBUF PORT "rgb_led0_r" IO_TYPE=LVCMOS33; +LOCATE COMP "rgb_led0_g" SITE "M3"; +IOBUF PORT "rgb_led0_g" IO_TYPE=LVCMOS33; +LOCATE COMP "rgb_led0_b" SITE "J3"; +IOBUF PORT "rgb_led0_b" IO_TYPE=LVCMOS33; +LOCATE COMP "gpio_0" SITE "N17"; +IOBUF PORT "gpio_0" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_0" PULLMODE=DOWN; +LOCATE COMP "gpio_1" SITE "M18"; +IOBUF PORT "gpio_1" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_1" PULLMODE=DOWN; +LOCATE COMP "gpio_5" SITE "B10"; +IOBUF PORT "gpio_5" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_5" PULLMODE=DOWN; +LOCATE COMP "gpio_6" SITE "B9"; +IOBUF PORT "gpio_6" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_6" PULLMODE=DOWN; +LOCATE COMP "gpio_9" SITE "C8"; +IOBUF PORT "gpio_9" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_9" PULLMODE=DOWN; +LOCATE COMP "gpio_10" SITE "B8"; +IOBUF PORT "gpio_10" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_10" PULLMODE=DOWN; +LOCATE COMP "gpio_11" SITE "A8"; +IOBUF PORT "gpio_11" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_11" PULLMODE=DOWN; +LOCATE COMP "gpio_12" SITE "H2"; +IOBUF PORT "gpio_12" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_12" PULLMODE=DOWN; +LOCATE COMP "gpio_13" SITE "J2"; +IOBUF PORT "gpio_13" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_13" PULLMODE=DOWN; +LOCATE COMP "gpio_a0" SITE "L4"; +IOBUF PORT "gpio_a0" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_a0" PULLMODE=DOWN; +LOCATE COMP "gpio_a1" SITE "N3"; +IOBUF PORT "gpio_a1" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_a1" PULLMODE=DOWN; +LOCATE COMP "gpio_a2" SITE "N4"; +IOBUF PORT "gpio_a2" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_a2" PULLMODE=DOWN; +LOCATE COMP "gpio_a3" SITE "H4"; +IOBUF PORT "gpio_a3" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_a3" PULLMODE=DOWN; +LOCATE COMP "usr_btn" SITE "J17"; +IOBUF PORT "usr_btn" IO_TYPE=SSTL135_I; +LOCATE COMP "rst_n" SITE "V17"; +IOBUF PORT "rst_n" IO_TYPE=LVCMOS33; +LOCATE COMP "spiflash4x_cs_n" SITE "U17"; +IOBUF PORT "spiflash4x_cs_n" IO_TYPE=LVCMOS33; +LOCATE COMP "spiflash4x_dq[0]" SITE "U18"; +IOBUF PORT "spiflash4x_dq[0]" IO_TYPE=LVCMOS33; +LOCATE COMP "spiflash4x_dq[1]" SITE "T18"; +IOBUF PORT "spiflash4x_dq[1]" IO_TYPE=LVCMOS33; +LOCATE COMP "spiflash4x_dq[2]" SITE "R18"; +IOBUF PORT "spiflash4x_dq[2]" IO_TYPE=LVCMOS33; +LOCATE COMP "spiflash4x_dq[3]" SITE "N18"; +IOBUF PORT "spiflash4x_dq[3]" IO_TYPE=LVCMOS33; +LOCATE COMP "usb_d_p" SITE "N1"; +IOBUF PORT "usb_d_p" IO_TYPE=LVCMOS33; +LOCATE COMP "usb_d_n" SITE "M2"; +IOBUF PORT "usb_d_n" IO_TYPE=LVCMOS33; +LOCATE COMP "usb_pullup" SITE "N2"; +IOBUF PORT "usb_pullup" IO_TYPE=LVCMOS33; diff --git a/verilog/alu/v4/tbalu.cpp b/verilog/alu/v4/tbalu.cpp new file mode 100644 index 0000000..b3947f8 --- /dev/null +++ b/verilog/alu/v4/tbalu.cpp @@ -0,0 +1,45 @@ +#include <stdlib.h> +#include <iostream> +#include <verilated.h> +#include <verilated_vcd_c.h> +#include "Valu.h" +#include "aluOp.h" +#define OP SRA +#define OPSTR "SRA" +#define SIGN "SRA" +#define LOWER -10 +#define UPPER 0 + +vluint64_t sim_time = 0; + +int main(int argc, char** argv, char** env) { + Valu *dut = new Valu; + + Verilated::traceEverOn(true); + VerilatedVcdC *m_trace = new VerilatedVcdC; + dut->trace(m_trace, 5); + m_trace->open("waveform.vcd"); + + dut->op = OP; + for (dut->in1 = LOWER; (int) dut->in1 < UPPER; dut->in1++) { + for (dut->in2 = 0; (int) dut->in2 < 10; dut->in2++) { + dut->eval(); + std::cout << OPSTR << ": " << (int) dut->in1 << " " << SIGN << " " << (int) dut->in2 << " = " << (int) dut->out << "\n"; + sim_time++; + m_trace->dump(sim_time); + } + } + + for (dut->in1 = 1; (int) dut->in1 < 10; dut->in1++) { + for (dut->in2 = 0; (int) dut->in2 < 10; dut->in2++) { + dut->eval(); + std::cout << OPSTR << ": " << dut->in1 << " " << SIGN << " " << dut->in2 << " = " << dut->out << "\n"; + sim_time++; + m_trace->dump(sim_time); + } + } + + m_trace->close(); + delete dut; + exit(EXIT_SUCCESS); +} diff --git a/verilog/alu/v5/Makefile b/verilog/alu/v5/Makefile new file mode 100644 index 0000000..bb659a4 --- /dev/null +++ b/verilog/alu/v5/Makefile @@ -0,0 +1,35 @@ +PROJ=alu5 +VERION:=r0.2 +RM = rm -rf +COPY = cp -a +PATH_SEP = / + + +crab: ${PROJ}.dfu + +dfu: ${PROJ}.dfu + dfu-util -D $< + + +%.json: %.v + yosys -p "read_verilog $<; synth_ecp5 -top ${PROJ} -json $@" + +%_out.config: %.json + nextpnr-ecp5 --json $< --textcfg $@ --25k --package CSFBGA285 --lpf crab.pcf + +%.bit: %_out.config + ecppack --compress --freq 38.8 --input $< --bit $@ + +%.dfu : %.bit + $(COPY) $< $@ + dfu-suffix -v 1209 -p 5af0 -a $@ + +sim: + verilator -Wall --cc --exe --build tbalu.cpp alu.v --trace && ./obj_dir/Valu > out +simclean: + rm -rf obj_dir/* out + +clean: + $(RM) -f ${PROJ}.bit ${PROJ}_out.config ${PROJ}.json ${PROJ}.dfu + +.PHONY: prog clean diff --git a/verilog/alu/v5/alu5.v b/verilog/alu/v5/alu5.v new file mode 100644 index 0000000..4670c19 --- /dev/null +++ b/verilog/alu/v5/alu5.v @@ -0,0 +1,30 @@ +`default_nettype none +`timescale 1us/1ns + +`include "aluOp.vh" + +module alu5 +( +input wire [31:0] alu_in_1, +input wire[31:0] alu_in_2, +input wire[3:0] alu_op_i, +output wire[31:0] alu_output +); + + +wire [31:0] diff = alu_in_1 - alu_in_2; + +assign alu_output = + alu_op_i == `NONE ? alu_in_1 : + alu_op_i == `ADD ? alu_in_1 + alu_in_2 : + alu_op_i == `SUB ? diff : + alu_op_i == `XOR ? alu_in_1 ^ alu_in_2 : + alu_op_i == `OR ? alu_in_1 | alu_in_2 : + alu_op_i == `AND ? alu_in_1 & alu_in_2 : + alu_op_i == `SLTU ? (alu_in_1 < alu_in_2 ? 32'b1 : 32'b0) : + alu_op_i == `SLT ? (alu_in_1[31] == alu_in_2[31] ? {31'b0, diff[31]} : {31'b0, alu_in_1[31]}) : + alu_op_i == `SLL ? alu_in_1 << alu_in_2 : + alu_op_i == `SRL ? alu_in_1 >> alu_in_2 : + alu_op_i == `SRA ? (alu_in_1 >> alu_in_2) | (alu_in_1[31] == 1'b0 ? 32'b0 : (32'hFFFFFFFF << {~alu_in_2[4], ~alu_in_2[3], ~alu_in_2[2], ~alu_in_2[1], ~alu_in_2[0]})) : + 32'b0; +endmodule diff --git a/verilog/alu/v5/aluOp.h b/verilog/alu/v5/aluOp.h new file mode 100644 index 0000000..999dac2 --- /dev/null +++ b/verilog/alu/v5/aluOp.h @@ -0,0 +1,16 @@ +#ifndef ALU_OP +#define ALU_OP + +#define ADD 0 +#define SUB 8 +#define XOR 4 +#define OR 6 +#define AND 7 +#define SLL 1 +#define SRL 5 +#define SRA 13 +#define SLT 2 +#define SLTU 3 +#define NONE 15 + +#endif diff --git a/verilog/alu/v5/aluOp.vh b/verilog/alu/v5/aluOp.vh new file mode 100644 index 0000000..b6e916f --- /dev/null +++ b/verilog/alu/v5/aluOp.vh @@ -0,0 +1,16 @@ +`ifndef ALU_OP +`define ALU_OP + +`define ADD 4'b0000 +`define SUB 4'b1000 +`define XOR 4'b0100 +`define OR 4'b0110 +`define AND 4'b0111 +`define SLL 4'b0001 +`define SRL 4'b0101 +`define SRA 4'b1101 +`define SLT 4'b0010 +`define SLTU 4'b0011 +`define NONE 4'b1111 + +`endif diff --git a/verilog/alu/v5/crab.pcf b/verilog/alu/v5/crab.pcf new file mode 100644 index 0000000..c0d91c5 --- /dev/null +++ b/verilog/alu/v5/crab.pcf @@ -0,0 +1,254 @@ +LOCATE COMP "clk48" SITE "A9"; +IOBUF PORT "clk48" IO_TYPE=LVCMOS33; +FREQUENCY PORT "clk48" 48.0 MHz; + +LOCATE COMP "ddram_a[0]" SITE "C4"; +IOBUF PORT "ddram_a[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[0]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[1]" SITE "D2"; +IOBUF PORT "ddram_a[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[1]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[2]" SITE "D3"; +IOBUF PORT "ddram_a[2]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[2]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[3]" SITE "A3"; +IOBUF PORT "ddram_a[3]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[3]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[4]" SITE "A4"; +IOBUF PORT "ddram_a[4]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[4]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[5]" SITE "D4"; +IOBUF PORT "ddram_a[5]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[5]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[6]" SITE "C3"; +IOBUF PORT "ddram_a[6]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[6]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[7]" SITE "B2"; +IOBUF PORT "ddram_a[7]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[7]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[8]" SITE "B1"; +IOBUF PORT "ddram_a[8]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[8]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[9]" SITE "D1"; +IOBUF PORT "ddram_a[9]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[9]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[10]" SITE "A7"; +IOBUF PORT "ddram_a[10]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[10]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[11]" SITE "C2"; +IOBUF PORT "ddram_a[11]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[11]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[12]" SITE "B6"; +IOBUF PORT "ddram_a[12]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[12]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[13]" SITE "C1"; +IOBUF PORT "ddram_a[13]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[13]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[14]" SITE "A2"; +IOBUF PORT "ddram_a[14]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[14]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[15]" SITE "C7"; +IOBUF PORT "ddram_a[15]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[15]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_ba[0]" SITE "D6"; +IOBUF PORT "ddram_ba[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_ba[0]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_ba[1]" SITE "B7"; +IOBUF PORT "ddram_ba[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_ba[1]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_ba[2]" SITE "A6"; +IOBUF PORT "ddram_ba[2]" SLEWRATE=FAST; +IOBUF PORT "ddram_ba[2]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_ras_n" SITE "C12"; +IOBUF PORT "ddram_ras_n" SLEWRATE=FAST; +IOBUF PORT "ddram_ras_n" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_cas_n" SITE "D13"; +IOBUF PORT "ddram_cas_n" SLEWRATE=FAST; +IOBUF PORT "ddram_cas_n" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_we_n" SITE "B12"; +IOBUF PORT "ddram_we_n" SLEWRATE=FAST; +IOBUF PORT "ddram_we_n" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_cs_n" SITE "A12"; +IOBUF PORT "ddram_cs_n" SLEWRATE=FAST; +IOBUF PORT "ddram_cs_n" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_dm[0]" SITE "D16"; +IOBUF PORT "ddram_dm[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_dm[0]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_dm[1]" SITE "G16"; +IOBUF PORT "ddram_dm[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_dm[1]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_dq[0]" SITE "C17"; +IOBUF PORT "ddram_dq[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[0]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[0]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[1]" SITE "D15"; +IOBUF PORT "ddram_dq[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[1]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[1]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[2]" SITE "B17"; +IOBUF PORT "ddram_dq[2]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[2]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[2]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[3]" SITE "C16"; +IOBUF PORT "ddram_dq[3]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[3]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[3]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[4]" SITE "A15"; +IOBUF PORT "ddram_dq[4]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[4]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[4]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[5]" SITE "B13"; +IOBUF PORT "ddram_dq[5]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[5]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[5]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[6]" SITE "A17"; +IOBUF PORT "ddram_dq[6]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[6]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[6]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[7]" SITE "A13"; +IOBUF PORT "ddram_dq[7]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[7]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[7]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[8]" SITE "F17"; +IOBUF PORT "ddram_dq[8]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[8]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[8]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[9]" SITE "F16"; +IOBUF PORT "ddram_dq[9]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[9]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[9]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[10]" SITE "G15"; +IOBUF PORT "ddram_dq[10]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[10]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[10]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[11]" SITE "F15"; +IOBUF PORT "ddram_dq[11]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[11]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[11]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[12]" SITE "J16"; +IOBUF PORT "ddram_dq[12]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[12]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[12]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[13]" SITE "C18"; +IOBUF PORT "ddram_dq[13]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[13]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[13]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[14]" SITE "H16"; +IOBUF PORT "ddram_dq[14]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[14]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[14]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[15]" SITE "F18"; +IOBUF PORT "ddram_dq[15]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[15]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[15]" TERMINATION=OFF; +LOCATE COMP "ddram_dqs_p[0]" SITE "B15"; +IOBUF PORT "ddram_dqs_p[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_dqs_p[0]" IO_TYPE=SSTL135D_I; +IOBUF PORT "ddram_dqs_p[0]" TERMINATION=OFF; +IOBUF PORT "ddram_dqs_p[0]" DIFFRESISTOR=100; +LOCATE COMP "ddram_dqs_p[1]" SITE "G18"; +IOBUF PORT "ddram_dqs_p[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_dqs_p[1]" IO_TYPE=SSTL135D_I; +IOBUF PORT "ddram_dqs_p[1]" TERMINATION=OFF; +IOBUF PORT "ddram_dqs_p[1]" DIFFRESISTOR=100; +LOCATE COMP "ddram_clk_p" SITE "J18"; +IOBUF PORT "ddram_clk_p" SLEWRATE=FAST; +IOBUF PORT "ddram_clk_p" IO_TYPE=SSTL135D_I; +LOCATE COMP "ddram_cke" SITE "D18"; +IOBUF PORT "ddram_cke" SLEWRATE=FAST; +IOBUF PORT "ddram_cke" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_odt" SITE "C13"; +IOBUF PORT "ddram_odt" SLEWRATE=FAST; +IOBUF PORT "ddram_odt" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_reset_n" SITE "L18"; +IOBUF PORT "ddram_reset_n" SLEWRATE=FAST; +IOBUF PORT "ddram_reset_n" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_vccio[0]" SITE "K16"; +IOBUF PORT "ddram_vccio[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[0]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_vccio[1]" SITE "D17"; +IOBUF PORT "ddram_vccio[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[1]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_vccio[2]" SITE "K15"; +IOBUF PORT "ddram_vccio[2]" SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[2]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_vccio[3]" SITE "K17"; +IOBUF PORT "ddram_vccio[3]" SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[3]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_vccio[4]" SITE "B18"; +IOBUF PORT "ddram_vccio[4]" SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[4]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_vccio[5]" SITE "C6"; +IOBUF PORT "ddram_vccio[5]" SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[5]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_gnd[0]" SITE "L15"; +IOBUF PORT "ddram_gnd[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_gnd[0]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_gnd[1]" SITE "L16"; +IOBUF PORT "ddram_gnd[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_gnd[1]" IO_TYPE=SSTL135_II; +LOCATE COMP "rgb_led0_r" SITE "K4"; +IOBUF PORT "rgb_led0_r" IO_TYPE=LVCMOS33; +LOCATE COMP "rgb_led0_g" SITE "M3"; +IOBUF PORT "rgb_led0_g" IO_TYPE=LVCMOS33; +LOCATE COMP "rgb_led0_b" SITE "J3"; +IOBUF PORT "rgb_led0_b" IO_TYPE=LVCMOS33; +LOCATE COMP "gpio_0" SITE "N17"; +IOBUF PORT "gpio_0" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_0" PULLMODE=DOWN; +LOCATE COMP "gpio_1" SITE "M18"; +IOBUF PORT "gpio_1" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_1" PULLMODE=DOWN; +LOCATE COMP "gpio_5" SITE "B10"; +IOBUF PORT "gpio_5" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_5" PULLMODE=DOWN; +LOCATE COMP "gpio_6" SITE "B9"; +IOBUF PORT "gpio_6" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_6" PULLMODE=DOWN; +LOCATE COMP "gpio_9" SITE "C8"; +IOBUF PORT "gpio_9" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_9" PULLMODE=DOWN; +LOCATE COMP "gpio_10" SITE "B8"; +IOBUF PORT "gpio_10" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_10" PULLMODE=DOWN; +LOCATE COMP "gpio_11" SITE "A8"; +IOBUF PORT "gpio_11" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_11" PULLMODE=DOWN; +LOCATE COMP "gpio_12" SITE "H2"; +IOBUF PORT "gpio_12" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_12" PULLMODE=DOWN; +LOCATE COMP "gpio_13" SITE "J2"; +IOBUF PORT "gpio_13" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_13" PULLMODE=DOWN; +LOCATE COMP "gpio_a0" SITE "L4"; +IOBUF PORT "gpio_a0" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_a0" PULLMODE=DOWN; +LOCATE COMP "gpio_a1" SITE "N3"; +IOBUF PORT "gpio_a1" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_a1" PULLMODE=DOWN; +LOCATE COMP "gpio_a2" SITE "N4"; +IOBUF PORT "gpio_a2" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_a2" PULLMODE=DOWN; +LOCATE COMP "gpio_a3" SITE "H4"; +IOBUF PORT "gpio_a3" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_a3" PULLMODE=DOWN; +LOCATE COMP "usr_btn" SITE "J17"; +IOBUF PORT "usr_btn" IO_TYPE=SSTL135_I; +LOCATE COMP "rst_n" SITE "V17"; +IOBUF PORT "rst_n" IO_TYPE=LVCMOS33; +LOCATE COMP "spiflash4x_cs_n" SITE "U17"; +IOBUF PORT "spiflash4x_cs_n" IO_TYPE=LVCMOS33; +LOCATE COMP "spiflash4x_dq[0]" SITE "U18"; +IOBUF PORT "spiflash4x_dq[0]" IO_TYPE=LVCMOS33; +LOCATE COMP "spiflash4x_dq[1]" SITE "T18"; +IOBUF PORT "spiflash4x_dq[1]" IO_TYPE=LVCMOS33; +LOCATE COMP "spiflash4x_dq[2]" SITE "R18"; +IOBUF PORT "spiflash4x_dq[2]" IO_TYPE=LVCMOS33; +LOCATE COMP "spiflash4x_dq[3]" SITE "N18"; +IOBUF PORT "spiflash4x_dq[3]" IO_TYPE=LVCMOS33; +LOCATE COMP "usb_d_p" SITE "N1"; +IOBUF PORT "usb_d_p" IO_TYPE=LVCMOS33; +LOCATE COMP "usb_d_n" SITE "M2"; +IOBUF PORT "usb_d_n" IO_TYPE=LVCMOS33; +LOCATE COMP "usb_pullup" SITE "N2"; +IOBUF PORT "usb_pullup" IO_TYPE=LVCMOS33; diff --git a/verilog/alu/v5/tbalu.cpp b/verilog/alu/v5/tbalu.cpp new file mode 100644 index 0000000..b3947f8 --- /dev/null +++ b/verilog/alu/v5/tbalu.cpp @@ -0,0 +1,45 @@ +#include <stdlib.h> +#include <iostream> +#include <verilated.h> +#include <verilated_vcd_c.h> +#include "Valu.h" +#include "aluOp.h" +#define OP SRA +#define OPSTR "SRA" +#define SIGN "SRA" +#define LOWER -10 +#define UPPER 0 + +vluint64_t sim_time = 0; + +int main(int argc, char** argv, char** env) { + Valu *dut = new Valu; + + Verilated::traceEverOn(true); + VerilatedVcdC *m_trace = new VerilatedVcdC; + dut->trace(m_trace, 5); + m_trace->open("waveform.vcd"); + + dut->op = OP; + for (dut->in1 = LOWER; (int) dut->in1 < UPPER; dut->in1++) { + for (dut->in2 = 0; (int) dut->in2 < 10; dut->in2++) { + dut->eval(); + std::cout << OPSTR << ": " << (int) dut->in1 << " " << SIGN << " " << (int) dut->in2 << " = " << (int) dut->out << "\n"; + sim_time++; + m_trace->dump(sim_time); + } + } + + for (dut->in1 = 1; (int) dut->in1 < 10; dut->in1++) { + for (dut->in2 = 0; (int) dut->in2 < 10; dut->in2++) { + dut->eval(); + std::cout << OPSTR << ": " << dut->in1 << " " << SIGN << " " << dut->in2 << " = " << dut->out << "\n"; + sim_time++; + m_trace->dump(sim_time); + } + } + + m_trace->close(); + delete dut; + exit(EXIT_SUCCESS); +} diff --git a/verilog/alu/v6/LUTS b/verilog/alu/v6/LUTS new file mode 100644 index 0000000..ec716bd --- /dev/null +++ b/verilog/alu/v6/LUTS @@ -0,0 +1,172 @@ + +ADD SUB no share + + Number of wires: 233 + Number of wire bits: 644 + Number of public wires: 233 + Number of public wire bits: 644 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 256 + CCU2C 32 + L6MUX21 32 + LUT4 128 + PFUMX 64 + + + +ADD SUB Sharing + + Number of wires: 12 + Number of wire bits: 356 + Number of public wires: 12 + Number of public wire bits: 356 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 128 + CCU2C 32 + LUT4 96 + +XOR + + Number of wires: 204 + Number of wire bits: 548 + Number of public wires: 204 + Number of public wire bits: 548 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 320 + CCU2C 32 + L6MUX21 32 + LUT4 192 + PFUMX 64 + + +AND + OR + + Number of wires: 204 + Number of wire bits: 548 + Number of public wires: 204 + Number of public wire bits: 548 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 320 + CCU2C 32 + L6MUX21 32 + LUT4 192 + PFUMX 64 + + + Number of wires: 212 + Number of wire bits: 556 + Number of public wires: 212 + Number of public wire bits: 556 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 328 + CCU2C 32 + L6MUX21 34 + LUT4 196 + PFUMX 66 + + +=== alu6 === + + Number of wires: 529 + Number of wire bits: 1122 + Number of public wires: 529 + Number of public wire bits: 1122 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 731 + CCU2C 32 + L6MUX21 66 + LUT4 475 + PFUMX 158 + +=== alu6 === Shift left + + Number of wires: 526 + Number of wire bits: 1100 + Number of public wires: 526 + Number of public wire bits: 1100 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 730 + CCU2C 32 + L6MUX21 67 + LUT4 473 + PFUMX 158 + +Shift right + + Number of wires: 1161 + Number of wire bits: 2070 + Number of public wires: 1161 + Number of public wire bits: 2070 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 1456 + CCU2C 32 + L6MUX21 174 + LUT4 923 + PFUMX 327 + +Shift right muxed + +=== alu6 === + + Number of wires: 843 + Number of wire bits: 1731 + Number of public wires: 843 + Number of public wire bits: 1731 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 1134 + CCU2C 32 + L6MUX21 103 + LUT4 756 + PFUMX 243 + +Set less than signed + +=== alu6 === + + Number of wires: 843 + Number of wire bits: 1731 + Number of public wires: 843 + Number of public wire bits: 1731 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 1134 + CCU2C 32 + L6MUX21 103 + LUT4 756 + PFUMX 243 + +Set less than unsigned + +=== alu6 === + + Number of wires: 871 + Number of wire bits: 1857 + Number of public wires: 871 + Number of public wire bits: 1857 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 1183 + CCU2C 48 + L6MUX21 109 + LUT4 778 + PFUMX 248 diff --git a/verilog/alu/v6/Makefile b/verilog/alu/v6/Makefile new file mode 100644 index 0000000..437e09f --- /dev/null +++ b/verilog/alu/v6/Makefile @@ -0,0 +1,40 @@ +PROJ=alu6 +VERION:=r0.2 +RM = rm -rf +COPY = cp -a +PATH_SEP = / + + +crab: ${PROJ}.dfu + +dfu: ${PROJ}.dfu + dfu-util -D $< + + +%.json: %.v + yosys -p "read_verilog $<; synth_ecp5 -top ${PROJ} -json $@" + +%_out.config: %.json + nextpnr-ecp5 --json $< --textcfg $@ --25k --package CSFBGA285 --lpf crab.pcf + +%.bit: %_out.config + ecppack --compress --freq 38.8 --input $< --bit $@ + +%.dfu : %.bit + $(COPY) $< $@ + dfu-suffix -v 1209 -p 5af0 -a $@ + +sim: + verilator -Wall --cc --exe --build tbalu.cpp alu6.v --trace && ./obj_dir/Valu6 > out +simgate: + yosys -p "read_verilog ${PROJ}.v; synth_ecp5 -top ${PROJ} -blif ${PROJ}.blif" + yosys -o synth_${PROJ}.v ${PROJ}.blif + verilator -Wall --cc --exe --build tbalu.cpp synth_alu6.v --trace && ./obj_dir/Valu6 > out + +simclean: + rm -rf obj_dir/* out + +clean: + $(RM) -f ${PROJ}.bit ${PROJ}_out.config ${PROJ}.json ${PROJ}.dfu + +.PHONY: prog clean diff --git a/verilog/alu/v6/alu6.blif b/verilog/alu/v6/alu6.blif new file mode 100644 index 0000000..33840f9 --- /dev/null +++ b/verilog/alu/v6/alu6.blif @@ -0,0 +1,6128 @@ +# Generated by Yosys 0.15+70 (git sha1 48d7a6c47, gcc 11.2.0 -march=x86-64 -mtune=generic -O2 -fno-plt -fexceptions -fstack-clash-protection -fcf-protection -fPIC -Os) + +.model alu6 +.inputs alu_in_1[0] alu_in_1[1] alu_in_1[2] alu_in_1[3] alu_in_1[4] alu_in_1[5] alu_in_1[6] alu_in_1[7] alu_in_1[8] alu_in_1[9] alu_in_1[10] alu_in_1[11] alu_in_1[12] alu_in_1[13] alu_in_1[14] alu_in_1[15] alu_in_1[16] alu_in_1[17] alu_in_1[18] alu_in_1[19] alu_in_1[20] alu_in_1[21] alu_in_1[22] alu_in_1[23] alu_in_1[24] alu_in_1[25] alu_in_1[26] alu_in_1[27] alu_in_1[28] alu_in_1[29] alu_in_1[30] alu_in_1[31] alu_in_2[0] alu_in_2[1] alu_in_2[2] alu_in_2[3] alu_in_2[4] alu_in_2[5] alu_in_2[6] alu_in_2[7] alu_in_2[8] alu_in_2[9] alu_in_2[10] alu_in_2[11] alu_in_2[12] alu_in_2[13] alu_in_2[14] alu_in_2[15] alu_in_2[16] alu_in_2[17] alu_in_2[18] alu_in_2[19] alu_in_2[20] alu_in_2[21] alu_in_2[22] alu_in_2[23] alu_in_2[24] alu_in_2[25] alu_in_2[26] alu_in_2[27] alu_in_2[28] alu_in_2[29] alu_in_2[30] alu_in_2[31] alu_op_i[0] alu_op_i[1] alu_op_i[2] alu_op_i[3] +.outputs alu_output[0] alu_output[1] alu_output[2] alu_output[3] alu_output[4] alu_output[5] alu_output[6] alu_output[7] alu_output[8] alu_output[9] alu_output[10] alu_output[11] alu_output[12] alu_output[13] alu_output[14] alu_output[15] alu_output[16] alu_output[17] alu_output[18] alu_output[19] alu_output[20] alu_output[21] alu_output[22] alu_output[23] alu_output[24] alu_output[25] alu_output[26] alu_output[27] alu_output[28] alu_output[29] alu_output[30] alu_output[31] +.names $false +.names $true +1 +.names $undef +.gate L6MUX21 D0=alu_output_L6MUX21_Z_D0 D1=alu_output_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[5] Z=alu_output[24] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate L6MUX21 D0=alu_output_L6MUX21_Z_1_D0 D1=alu_output_L6MUX21_Z_1_D1 SD=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[5] Z=alu_output[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_L6MUX21_Z_1_D0_PFUMX_Z_ALUT BLUT=alu_output_L6MUX21_Z_1_D0_PFUMX_Z_BLUT C0=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[4] Z=alu_output_L6MUX21_Z_1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_L6MUX21_Z_1_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111111111111 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_L6MUX21_Z_1_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111111111111 +.gate PFUMX ALUT=alu_output_L6MUX21_Z_1_D1_PFUMX_Z_ALUT BLUT=alu_output_L6MUX21_Z_1_D1_PFUMX_Z_BLUT C0=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[4] Z=alu_output_L6MUX21_Z_1_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_L6MUX21_Z_1_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111111111111 +.gate LUT4 A=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[0] B=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[1] C=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] D=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[3] Z=alu_output_L6MUX21_Z_1_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111000001000000 +.gate L6MUX21 D0=alu_output_L6MUX21_Z_2_D0 D1=alu_output_L6MUX21_Z_2_D1 SD=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] Z=alu_output[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D0 D1=alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[5] Z=alu_output_L6MUX21_Z_2_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[4] Z=alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 1111111111111111 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 1111111111111111 +.gate PFUMX ALUT=alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[4] Z=alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 1111111111111111 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D0 D1=alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[5] Z=alu_output_L6MUX21_Z_2_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[4] Z=alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 1111111111111111 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 1111111111111111 +.gate PFUMX ALUT=alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[4] Z=alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 1111111111111111 +.gate LUT4 A=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[0] B=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] C=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[2] D=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[3] Z=alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0100111101000100 +.gate L6MUX21 D0=alu_output_L6MUX21_Z_3_D0 D1=alu_output_L6MUX21_Z_3_D1 SD=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[5] Z=alu_output[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_L6MUX21_Z_3_D0_PFUMX_Z_ALUT BLUT=alu_output_L6MUX21_Z_3_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[4] Z=alu_output_L6MUX21_Z_3_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_L6MUX21_Z_3_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111111111111 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_L6MUX21_Z_3_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111111111111 +.gate PFUMX ALUT=alu_output_L6MUX21_Z_3_D1_PFUMX_Z_ALUT BLUT=alu_output_L6MUX21_Z_3_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[4] Z=alu_output_L6MUX21_Z_3_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_L6MUX21_Z_3_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111111111111 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[0] B=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] C=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] D=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[3] Z=alu_output_L6MUX21_Z_3_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111000001000000 +.gate PFUMX ALUT=alu_output_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[4] Z=alu_output_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111111111111 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111111111111 +.gate PFUMX ALUT=alu_output_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[4] Z=alu_output_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111111111111 +.gate LUT4 A=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[0] B=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[1] C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[2] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] Z=alu_output_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111110 +.gate LUT4 A=alu_output_LUT4_Z_A[0] B=alu_output_LUT4_Z_A[1] C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] D=alu_output_LUT4_Z_A[3] Z=alu_output[29] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000101111111111 +.gate LUT4 A=$false B=alu_output_LUT4_Z_1_B[0] C=alu_output_LUT4_Z_1_B[1] D=alu_output_LUT4_Z_1_B[2] Z=alu_output[28] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1111110011111111 +.gate LUT4 A=$false B=alu_output_LUT4_Z_10_B[0] C=alu_output_LUT4_Z_10_B[1] D=alu_output_LUT4_Z_10_B[2] Z=alu_output[8] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1111110011111111 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] B=sum[8] C=alu_output_LUT4_Z_10_B_LUT4_Z_C[2] D=alu_output_LUT4_Z_10_B_LUT4_Z_C[3] Z=alu_output_LUT4_Z_10_B[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000000000111 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] B=alu_output_LUT4_Z_10_B_LUT4_Z_1_B[1] C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B[2] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] Z=alu_output_LUT4_Z_10_B[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1111000100000000 +.gate LUT4 A=alu_output_LUT4_Z_10_B_LUT4_Z_1_B[1] B=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_B_Z[0] C=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] D=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1111010111110011 +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] D=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 1111000000000000 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] B=sum[16] C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z_LUT4_Z_1_C[2] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z_LUT4_Z_1_C[3] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000000000111 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] C=alu_in_1[16] D=alu_in_2[16] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z_LUT4_Z_1_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100000000000000 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[16] D=alu_in_2[16] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z_LUT4_Z_1_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] B=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[1] C=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[2] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000010111111 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] B=alu_output_LUT4_Z_10_B_LUT4_Z_1_B[1] C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B[2] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[5] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1111000100000000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] C=alu_op_i[3] D=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0000000000111111 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] B=sum[24] C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_LUT4_Z_1_C[2] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_LUT4_Z_1_C[3] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000000000111 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] C=alu_in_1[24] D=alu_in_2[24] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_LUT4_Z_1_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100000000000000 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[24] D=alu_in_2[24] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_LUT4_Z_1_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_B_Z[0] D=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 0000111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_PFUMX_Z_1_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_PFUMX_Z_1_BLUT C0=alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_A_L6MUX21_Z_SD[0] B=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] C=alu_output_LUT4_Z_A_L6MUX21_Z_SD[2] D=alu_in_2[2] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_PFUMX_Z_1_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1111001110101010 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_PFUMX_Z_1_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[2] B=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[3] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000001100000101 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] B=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[1] D=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0100000000000000 +.gate LUT4 A=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A[3] B=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A[0] C=alu_in_2[2] D=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0101001100000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1 SD=alu_in_2[1] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[0] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[3] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[4] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[0] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[1] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[2] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A[3] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100001111 +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[1] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111000000000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0 D1=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z SD=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0 D1=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1 SD=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[5] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_PFUMX_Z_BLUT C0=alu_in_2[2] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_PFUMX_Z_BLUT C0=alu_in_2[2] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[0] C=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] D=alu_in_2[5] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000111111001111 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_L6MUX21_Z_SD[2] C=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] D=alu_in_2[5] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000111111001111 +.gate L6MUX21 D0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 1111111111111111 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 1111111111111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 1111111111111111 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 1111111111111111 +.gate L6MUX21 D0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[2] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[3] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[0] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[1] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] C=alu_in_2[5] D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0011111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A[0] B=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A[1] C=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] D=alu_in_2[2] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1010111111001111 +.gate L6MUX21 D0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D1 SD=alu_in_2[1] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate L6MUX21 D0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0 D1=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D1 SD=alu_in_2[31] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[0] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=alu_in_1[0] B=alu_op_i[1] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000010 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[0] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=alu_in_1[0] B=alu_op_i[1] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 1111111111111110 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 1111111111111111 +.gate L6MUX21 D0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D1 SD=alu_in_2[31] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[0] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=alu_op_i[1] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 1111111111111100 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 1111111111111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[0] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=alu_op_i[1] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 1111111111111100 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 1111111111111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[31] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111111111111 +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[31] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111011111111 +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111011111111 +.gate LUT4 A=$false B=alu_in_1[1] C=alu_in_1[2] D=alu_in_2[0] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=alu_output_LUT4_Z_10_B_LUT4_Z_2_A[0] B=alu_output_LUT4_Z_10_B_LUT4_Z_2_A[1] C=alu_output_LUT4_Z_10_B_LUT4_Z_2_A[2] D=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] Z=alu_output_LUT4_Z_10_B[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1111010000000000 +.gate LUT4 A=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[0] B=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[1] C=alu_in_2[2] D=alu_in_2[3] Z=alu_output_LUT4_Z_10_B_LUT4_Z_2_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100101000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_2_A_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_2_A_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_10_B_LUT4_Z_2_A[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_2_A_PFUMX_Z_1_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_2_A_PFUMX_Z_1_BLUT C0=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] Z=alu_output_LUT4_Z_10_B_LUT4_Z_2_A[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[2] B=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[3] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_LUT4_Z_10_B_LUT4_Z_2_A_PFUMX_Z_1_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000001100000101 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_10_B_LUT4_Z_2_A_PFUMX_Z_1_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[0] B=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[1] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_LUT4_Z_10_B_LUT4_Z_2_A_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1111001111110101 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_10_B_LUT4_Z_2_A_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[8] D=alu_in_2[8] Z=alu_output_LUT4_Z_10_B_LUT4_Z_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] C=alu_in_1[8] D=alu_in_2[8] Z=alu_output_LUT4_Z_10_B_LUT4_Z_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100000000000000 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] B=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[0] C=alu_output_LUT4_Z_11_C[2] D=alu_output_LUT4_Z_11_C[3] Z=alu_output[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1111001011111111 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] B=sum[5] C=alu_output_LUT4_Z_11_C_LUT4_Z_C[2] D=alu_output_LUT4_Z_11_C_LUT4_Z_C[3] Z=alu_output_LUT4_Z_11_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000000000111 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[5] D=alu_in_2[5] Z=alu_output_LUT4_Z_11_C_LUT4_Z_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] C=alu_in_1[5] D=alu_in_2[5] Z=alu_output_LUT4_Z_11_C_LUT4_Z_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_11_C_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] Z=alu_output_LUT4_Z_11_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A[0] B=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] C=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A[2] D=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A[3] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0100111101000100 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[1] B=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B[0] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000110000001010 +.gate L6MUX21 D0=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[11] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[9] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[12] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[10] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B[0] C=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B[1] D=alu_in_2[2] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1111000011001100 +.gate L6MUX21 D0=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[7] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[5] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[8] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[6] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A[0] B=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[2] C=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A[2] D=alu_in_2[3] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111010111110011 +.gate LUT4 A=$false B=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[0] C=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[1] D=alu_in_2[2] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_1_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1111000011001100 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[0] C=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[1] D=alu_in_2[2] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1111000011001100 +.gate PFUMX ALUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[2] B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[3] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000001100000101 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z BLUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_BLUT C0=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A[2] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_D0 D1=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z SD=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[9] D=alu_in_2[9] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[3] B=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[2] C=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] D=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_1_D[3] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000000011111 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] C=alu_in_1[9] D=alu_in_2[9] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_1_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100000000000000 +.gate LUT4 A=$false B=alu_op_i[0] C=alu_op_i[1] D=alu_op_i[2] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0000000000000011 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[2] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z BLUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_1_Z C0=alu_in_2[3] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] B=sum[1] C=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_C[2] D=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_C[3] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000000000111 +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[1] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 1111000000000000 +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[0] D=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 0000111100000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D1 SD=alu_in_2[2] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[3] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[2] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[0] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[3] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[3] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[1] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[17] D=alu_in_2[17] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=alu_in_1[17] B=alu_in_2[17] C=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] D=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_LUT4_Z_1_D[3] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000001111111 +.gate LUT4 A=alu_op_i[0] B=alu_op_i[1] C=alu_op_i[2] D=sum[17] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_LUT4_Z_1_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000100000000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] C=alu_in_1[1] D=alu_in_2[1] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100000000000000 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[1] D=alu_in_2[1] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate PFUMX ALUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=$false B=alu_in_1[3] C=alu_in_1[4] D=alu_in_2[0] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000111100110011 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z_D[2] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=alu_in_1[1] C=alu_in_1[2] D=alu_in_2[0] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1111000011001100 +.gate PFUMX ALUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate PFUMX ALUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_1_ALUT BLUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_1_BLUT C0=alu_in_2[2] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[2] D=alu_in_2[3] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_1_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1111111111110000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[1] C=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[3] D=alu_in_2[3] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_1_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1111000011001100 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[0] B=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B[1] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0101111100111111 +.gate L6MUX21 D0=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[15] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[13] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[16] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[14] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[0] B=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B[1] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000101000001100 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[3] B=alu_in_2[2] C=alu_in_2[3] D=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[1] B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[2] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0011111101011111 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_11_C_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] B=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[0] C=alu_output_LUT4_Z_12_C[2] D=alu_output_LUT4_Z_12_C[3] Z=alu_output[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1111100011111111 +.gate L6MUX21 D0=alu_output_LUT4_Z_12_C_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_12_C_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] Z=alu_output_LUT4_Z_12_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_12_C_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_12_C_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[4] Z=alu_output_LUT4_Z_12_C_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_12_C_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_12_C_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_12_C_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_12_C_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[4] Z=alu_output_LUT4_Z_12_C_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_5_B_LUT4_Z_A[2] D=alu_in_2[5] Z=alu_output_LUT4_Z_12_C_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000000001111 +.gate LUT4 A=$false B=alu_output_LUT4_Z_5_B_LUT4_Z_A[0] C=alu_output_LUT4_Z_5_B_LUT4_Z_A[1] D=alu_in_2[5] Z=alu_output_LUT4_Z_12_C_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000000000011 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] B=sum[2] C=alu_output_LUT4_Z_12_C_LUT4_Z_C[2] D=alu_output_LUT4_Z_12_C_LUT4_Z_C[3] Z=alu_output_LUT4_Z_12_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000000000111 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] C=alu_in_1[2] D=alu_in_2[2] Z=alu_output_LUT4_Z_12_C_LUT4_Z_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100000000000000 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[2] D=alu_in_2[2] Z=alu_output_LUT4_Z_12_C_LUT4_Z_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate L6MUX21 D0=alu_output_LUT4_Z_1_B_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_1_B_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] Z=alu_output_LUT4_Z_1_B[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[5] Z=alu_output_LUT4_Z_1_B_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] Z=alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 1111111111111111 +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[1] Z=alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 1111000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] Z=alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 1111111111111111 +.gate LUT4 A=alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] B=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[1] C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[2] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[3] Z=alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 1111111111111000 +.gate L6MUX21 D0=alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[5] Z=alu_output_LUT4_Z_1_B_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] Z=alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] Z=alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] B=sum[28] C=alu_output_LUT4_Z_1_B_LUT4_Z_C[2] D=alu_output_LUT4_Z_1_B_LUT4_Z_C[3] Z=alu_output_LUT4_Z_1_B[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000000000111 +.gate LUT4 A=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[3] B=alu_in_2[2] C=alu_in_2[3] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] Z=alu_output_LUT4_Z_1_B[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000100000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate L6MUX21 D0=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D0 D1=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[26] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[24] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[27] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[25] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate L6MUX21 D0=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D0 D1=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[22] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[20] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[23] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[21] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate L6MUX21 D0=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D0 D1=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[18] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[16] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[19] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[17] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[30] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[28] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[31] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[29] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] C=alu_in_1[28] D=alu_in_2[28] Z=alu_output_LUT4_Z_1_B_LUT4_Z_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100000000000000 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[28] D=alu_in_2[28] Z=alu_output_LUT4_Z_1_B_LUT4_Z_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=alu_output_LUT4_Z_2_A[0] B=alu_output_LUT4_Z_2_A[1] C=alu_output_LUT4_Z_2_A[2] D=alu_output_LUT4_Z_2_A[3] Z=alu_output[25] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1111111011111111 +.gate L6MUX21 D0=alu_output_LUT4_Z_2_A_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_2_A_L6MUX21_Z_D1 SD=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] Z=alu_output_LUT4_Z_2_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] Z=alu_output_LUT4_Z_2_A_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[4] Z=alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[0] D=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[1] Z=alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000001111 +.gate PFUMX ALUT=alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[4] Z=alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] Z=alu_output_LUT4_Z_2_A_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[4] Z=alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[2] D=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[3] Z=alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 1111111111110000 +.gate PFUMX ALUT=alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[4] Z=alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[25] D=alu_in_2[25] Z=alu_output_LUT4_Z_2_A[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate PFUMX ALUT=alu_output_LUT4_Z_2_A_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_2_A_PFUMX_Z_BLUT C0=sum[25] Z=alu_output_LUT4_Z_2_A[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate PFUMX ALUT=alu_output_LUT4_Z_2_A_PFUMX_Z_1_ALUT BLUT=alu_output_LUT4_Z_2_A_PFUMX_Z_1_BLUT C0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] Z=alu_output_LUT4_Z_2_A[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[2] B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[3] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_LUT4_Z_2_A_PFUMX_Z_1_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000001100000101 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_2_A_PFUMX_Z_1_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_in_2[25] B=alu_in_1[25] C=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] D=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] Z=alu_output_LUT4_Z_2_A_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000000001111111 +.gate LUT4 A=$false B=alu_in_2[25] C=alu_in_1[25] D=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] Z=alu_output_LUT4_Z_2_A_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0011111111111111 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] B=sum[20] C=alu_output_LUT4_Z_3_C[2] D=alu_output_LUT4_Z_3_C[3] Z=alu_output[20] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1111100011111111 +.gate L6MUX21 D0=alu_output_LUT4_Z_3_C_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[4] Z=alu_output_LUT4_Z_3_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[2] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000011111111 +.gate LUT4 A=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[0] B=alu_output_LUT4_Z_A_L6MUX21_Z_SD[2] C=alu_in_2[2] D=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0101001100000000 +.gate LUT4 A=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A[0] B=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A[1] C=alu_in_2[2] D=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0101001100000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D1 SD=alu_in_2[1] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate L6MUX21 D0=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D0 D1=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D1 SD=alu_in_2[1] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D0_PFUMX_Z_BLUT C0=alu_in_2[0] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[7] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[8] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D1_PFUMX_Z_BLUT C0=alu_in_2[0] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[5] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[6] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[0] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[11] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[12] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[0] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[9] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[10] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1 SD=alu_in_2[3] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D0 D1=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D1 SD=alu_in_2[1] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D0_PFUMX_Z_BLUT C0=alu_in_2[0] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[15] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[16] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D1_PFUMX_Z_BLUT C0=alu_in_2[0] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[13] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[14] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_in_2[4] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[31] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[31] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 1111111011111111 +.gate L6MUX21 D0=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_in_2[4] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[31] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000100000000 +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[31] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A[1] B=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[0] C=alu_in_2[2] D=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_B_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0101001100000000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] C=alu_in_2[5] D=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[5] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0011111100000000 +.gate LUT4 A=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[1] B=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[2] C=alu_in_2[1] D=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1010110011111111 +.gate LUT4 A=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z_LUT4_Z_1_A[0] B=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[0] C=alu_in_2[1] D=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1010110011111111 +.gate LUT4 A=$false B=alu_in_1[19] C=alu_in_1[20] D=alu_in_2[0] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z_LUT4_Z_1_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[0] D=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[1] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000000001111 +.gate LUT4 A=alu_output_LUT4_Z_3_C_LUT4_Z_A[0] B=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] C=alu_output_LUT4_Z_3_C_LUT4_Z_C[2] D=alu_output_LUT4_Z_3_C_LUT4_Z_C[3] Z=alu_output_LUT4_Z_3_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000000001011 +.gate LUT4 A=alu_output_LUT4_Z_3_C_LUT4_Z_A[0] B=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] C=alu_output_LUT4_Z_3_C_LUT4_Z_A[2] D=alu_output_LUT4_Z_3_C_LUT4_Z_A[3] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0100111101000100 +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z BLUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_BLUT C0=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A[3] C=alu_in_2[2] D=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0000001100000000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[1] C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0011111100000000 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] B=sum[4] C=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[2] D=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[3] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000000000111 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[4] D=alu_in_2[4] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] C=alu_in_1[4] D=alu_in_2[4] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100000000000000 +.gate LUT4 A=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[0] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000110000001010 +.gate L6MUX21 D0=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate L6MUX21 D0=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0 D1=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D1 SD=alu_in_2[1] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[2] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[0] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[2] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[2] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 1111111100000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D1 SD=alu_in_2[1] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[2] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[1] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[2] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[3] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[6] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[4] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[7] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[5] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate LUT4 A=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A[0] B=alu_in_2[2] C=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A[2] D=alu_in_2[3] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000000001011 +.gate L6MUX21 D0=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1 SD=alu_in_2[2] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[3] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[2] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[0] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[3] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[3] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[1] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=alu_in_2[5] D=alu_in_2[4] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 0000111100000000 +.gate LUT4 A=$false B=alu_op_i[1] C=alu_op_i[0] D=alu_op_i[2] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0011000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[0] B=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[1] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0011111101011111 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_PFUMX_Z_1_ALUT BLUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_PFUMX_Z_1_BLUT C0=alu_in_2[2] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[2] D=alu_in_2[3] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_PFUMX_Z_1_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1111111111110000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[1] C=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[3] D=alu_in_2[3] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_PFUMX_Z_1_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1111000011001100 +.gate LUT4 A=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[0] B=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[1] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0101111100111111 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] C=alu_in_1[20] D=alu_in_2[20] Z=alu_output_LUT4_Z_3_C_LUT4_Z_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100000000000000 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[20] D=alu_in_2[20] Z=alu_output_LUT4_Z_3_C_LUT4_Z_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[0] B=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] C=alu_output_LUT4_Z_4_C[2] D=alu_output_LUT4_Z_4_C[3] Z=alu_output[19] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1111010011111111 +.gate L6MUX21 D0=alu_output_LUT4_Z_4_C_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_4_C_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[4] Z=alu_output_LUT4_Z_4_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_4_C_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_4_C_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_4_C_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_4_C_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_4_C_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_4_C_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_4_C_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_4_C_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=alu_output_LUT4_Z_9_B_LUT4_Z_1_B[0] C=alu_output_LUT4_Z_9_B_LUT4_Z_1_B[2] D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] Z=alu_output_LUT4_Z_4_C_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111000011110011 +.gate LUT4 A=$false B=alu_output_LUT4_Z_9_B_LUT4_Z_1_B[1] C=alu_output_LUT4_Z_9_B_LUT4_Z_1_B[2] D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] Z=alu_output_LUT4_Z_4_C_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111000011110011 +.gate PFUMX ALUT=alu_output_LUT4_Z_4_C_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_4_C_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_4_C_PFUMX_Z_C0[4] Z=alu_output_LUT4_Z_4_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_4_C_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] B=alu_output_LUT4_Z_4_C_PFUMX_Z_C0[1] C=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] D=sum[19] Z=alu_output_LUT4_Z_4_C_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000011101110111 +.gate LUT4 A=$false B=$false C=alu_in_1[19] D=alu_in_2[19] Z=alu_output_LUT4_Z_4_C_PFUMX_Z_C0[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 1111000000000000 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[19] D=alu_in_2[19] Z=alu_output_LUT4_Z_4_C_PFUMX_Z_C0[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_5_B[0] C=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[4] D=alu_output_LUT4_Z_5_B[2] Z=alu_output[18] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0011000011111111 +.gate LUT4 A=alu_output_LUT4_Z_5_B_LUT4_Z_A[2] B=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] C=alu_output_LUT4_Z_5_B_LUT4_Z_C[2] D=alu_output_LUT4_Z_5_B_LUT4_Z_C[3] Z=alu_output_LUT4_Z_5_B[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1011000000000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D1 SD=alu_in_2[2] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[3] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[2] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[0] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[3] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[3] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[1] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate LUT4 A=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z[1] B=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B[1] C=alu_in_2[2] D=alu_in_2[3] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100101000000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[16] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[14] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[17] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[15] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[0] C=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B[1] D=alu_in_2[2] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate L6MUX21 D0=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[12] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[10] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[13] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[11] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT C0=alu_in_2[2] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B[2] D=alu_in_2[3] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000000011110000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B[0] C=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B[1] D=alu_in_2[3] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000011 +.gate L6MUX21 D0=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[8] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[6] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[9] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[7] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate LUT4 A=alu_in_1[4] B=alu_in_1[5] C=alu_in_2[0] D=alu_in_2[1] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100101000000000 +.gate LUT4 A=alu_in_1[2] B=alu_in_1[3] C=alu_in_2[1] D=alu_in_2[0] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000110000001010 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] C=alu_in_1[18] D=alu_in_2[18] Z=alu_output_LUT4_Z_5_B_LUT4_Z_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0101001100111111 +.gate LUT4 A=$false B=alu_output_LUT4_Z_5_B_LUT4_Z_C_LUT4_Z_1_B[0] C=alu_in_2[18] D=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] Z=alu_output_LUT4_Z_5_B_LUT4_Z_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0000111100110011 +.gate LUT4 A=alu_op_i[0] B=alu_op_i[1] C=alu_op_i[2] D=sum[18] Z=alu_output_LUT4_Z_5_B_LUT4_Z_C_LUT4_Z_1_B[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_5_B_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_5_B_PFUMX_Z_BLUT C0=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] Z=alu_output_LUT4_Z_5_B[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=$false B=$false C=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[0] D=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_5_B_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1111111100001111 +.gate LUT4 A=$false B=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[1] C=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[2] D=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_5_B_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1100110011110000 +.gate LUT4 A=alu_output_LUT4_Z_6_A[0] B=alu_output_LUT4_Z_6_A[1] C=alu_output_LUT4_Z_6_A[2] D=alu_output_LUT4_Z_6_A[3] Z=alu_output[15] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1111111011111111 +.gate L6MUX21 D0=alu_output_LUT4_Z_6_A_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] Z=alu_output_LUT4_Z_6_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_6_A_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_6_A_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] B=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] C=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[2] D=alu_in_2[3] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111010111110011 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[2] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[0] C=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[1] D=alu_in_2[2] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B[0] C=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[0] D=alu_in_2[2] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1111000011001100 +.gate L6MUX21 D0=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[25] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[23] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[26] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[24] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate L6MUX21 D0=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[21] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[19] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[22] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[20] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[0] C=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B[0] D=alu_in_2[2] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1111000011001100 +.gate L6MUX21 D0=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[29] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[27] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[30] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[28] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=alu_in_2[0] C=alu_in_2[1] D=alu_in_1[31] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0000001100000000 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[15] D=alu_in_2[15] Z=alu_output_LUT4_Z_6_A[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=alu_output_PFUMX_Z_C0_LUT4_Z_A[1] B=alu_output_PFUMX_Z_C0_LUT4_Z_B[0] C=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] Z=alu_output_LUT4_Z_6_A[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0101001100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_6_A_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_6_A_PFUMX_Z_BLUT C0=sum[15] Z=alu_output_LUT4_Z_6_A[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_in_2[15] B=alu_in_1[15] C=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] D=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] Z=alu_output_LUT4_Z_6_A_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000000001111111 +.gate LUT4 A=$false B=alu_in_2[15] C=alu_in_1[15] D=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] Z=alu_output_LUT4_Z_6_A_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0011111111111111 +.gate LUT4 A=alu_output_LUT4_Z_7_A[0] B=alu_output_LUT4_Z_7_A[1] C=alu_output_LUT4_Z_7_A[2] D=alu_output_LUT4_Z_7_A[3] Z=alu_output[13] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1111111011111111 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[13] D=alu_in_2[13] Z=alu_output_LUT4_Z_7_A[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z[0] B=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z[1] C=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z[2] D=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] Z=alu_output_LUT4_Z_7_A[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1111010000000000 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[0] B=alu_output_LUT4_Z_A_LUT4_Z_1_B[1] C=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] Z=alu_output_LUT4_Z_7_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0101001100000000 +.gate LUT4 A=$false B=$false C=alu_op_i[0] D=alu_op_i[2] Z=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 0000111100000000 +.gate LUT4 A=$false B=alu_op_i[0] C=alu_op_i[1] D=alu_op_i[2] Z=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0011000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_7_A_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_7_A_PFUMX_Z_BLUT C0=sum[13] Z=alu_output_LUT4_Z_7_A[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_in_2[13] B=alu_in_1[13] C=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] D=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] Z=alu_output_LUT4_Z_7_A_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000000001111111 +.gate LUT4 A=$false B=alu_in_2[13] C=alu_in_1[13] D=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] Z=alu_output_LUT4_Z_7_A_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0011111111111111 +.gate LUT4 A=alu_output_LUT4_Z_8_A[0] B=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] C=alu_output_LUT4_Z_8_A[2] D=alu_output_LUT4_Z_8_A[3] Z=alu_output[12] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1111010011111111 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] B=sum[12] C=alu_output_LUT4_Z_8_A_LUT4_Z_C[2] D=alu_output_LUT4_Z_8_A_LUT4_Z_C[3] Z=alu_output_LUT4_Z_8_A[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000000000111 +.gate LUT4 A=alu_output_LUT4_Z_8_A_LUT4_Z_1_A[0] B=alu_output_LUT4_Z_8_A_LUT4_Z_1_A[1] C=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] D=alu_output_LUT4_Z_8_A_LUT4_Z_1_A[3] Z=alu_output_LUT4_Z_8_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000011101111 +.gate LUT4 A=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[1] B=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[2] C=alu_in_2[2] D=alu_in_2[3] Z=alu_output_LUT4_Z_8_A_LUT4_Z_1_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100101000000000 +.gate LUT4 A=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[0] B=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[1] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_LUT4_Z_8_A_LUT4_Z_1_A[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000101000001100 +.gate LUT4 A=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[3] B=alu_in_2[2] C=alu_in_2[3] D=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] Z=alu_output_LUT4_Z_8_A_LUT4_Z_1_A[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000100000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate L6MUX21 D0=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D0 D1=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[10] Z=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[8] Z=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[11] Z=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[9] Z=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[14] Z=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[12] Z=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[15] Z=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[13] Z=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=alu_in_2[4] D=alu_in_2[5] Z=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 0000000000001111 +.gate LUT4 A=$false B=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[2] C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[3] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] Z=alu_output_LUT4_Z_8_A[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1111110000000000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] C=alu_in_1[12] D=alu_in_2[12] Z=alu_output_LUT4_Z_8_A_LUT4_Z_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100000000000000 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[12] D=alu_in_2[12] Z=alu_output_LUT4_Z_8_A_LUT4_Z_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_9_B[0] C=alu_output_LUT4_Z_9_B[1] D=alu_output_LUT4_Z_9_B[2] Z=alu_output[11] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1111110011111111 +.gate L6MUX21 D0=alu_output_LUT4_Z_9_B_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] Z=alu_output_LUT4_Z_9_B[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[2] B=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] C=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[2] D=alu_in_2[3] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111010111110011 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[2] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] C=alu_in_2[3] D=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0011111100000000 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] B=sum[3] C=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_C[2] D=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_C[3] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000000000111 +.gate LUT4 A=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A[0] B=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A[0] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000110000001010 +.gate PFUMX ALUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=$false B=alu_in_1[5] C=alu_in_1[6] D=alu_in_2[0] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000111100110011 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_BLUT_LUT4_Z_D[2] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=alu_in_1[3] C=alu_in_1[4] D=alu_in_2[0] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_BLUT_LUT4_Z_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1111000011001100 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[3] D=alu_in_2[3] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] C=alu_in_1[3] D=alu_in_2[3] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate PFUMX ALUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_Z_1_ALUT BLUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_Z_1_BLUT C0=alu_in_2[3] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=$false B=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[0] C=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[1] D=alu_in_2[2] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_Z_1_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000111111001100 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[2] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_Z_1_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1111111100000000 +.gate LUT4 A=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[0] B=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] C=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] D=alu_in_2[1] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000010100000011 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[0] C=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[1] D=alu_in_2[2] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1111000011001100 +.gate L6MUX21 D0=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate L6MUX21 D0=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D0 D1=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[13] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[11] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[14] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[12] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[17] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[15] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[18] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[16] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[0] B=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[1] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000110000000101 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] B=sum[11] C=alu_output_LUT4_Z_9_B_LUT4_Z_C[2] D=alu_output_LUT4_Z_9_B_LUT4_Z_C[3] Z=alu_output_LUT4_Z_9_B[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000000000111 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] B=alu_output_LUT4_Z_9_B_LUT4_Z_1_B[0] C=alu_output_LUT4_Z_9_B_LUT4_Z_1_C[2] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] Z=alu_output_LUT4_Z_9_B[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1111000100000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[0] Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_B[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate L6MUX21 D0=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_1_D0 D1=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_1_D1 SD=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_B[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate L6MUX21 D0=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_2_D0 D1=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_2_D1 SD=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_B[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_2_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_2_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_2_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[3] Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_2_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_2_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[2] B=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[1] C=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] D=alu_in_2[1] Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1010111111001111 +.gate L6MUX21 D0=alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[2] B=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[1] C=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] D=alu_in_2[1] Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1010111111001111 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[11] D=alu_in_2[11] Z=alu_output_LUT4_Z_9_B_LUT4_Z_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] C=alu_in_1[11] D=alu_in_2[11] Z=alu_output_LUT4_Z_9_B_LUT4_Z_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100000000000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] Z=alu_output_LUT4_Z_A[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_A_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] D=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[3] Z=alu_output_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111100001111 +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] D=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[3] Z=alu_output_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100001111 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_A_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[0] C=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] D=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[3] Z=alu_output_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1100110000001100 +.gate LUT4 A=$false B=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[1] C=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] D=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[3] Z=alu_output_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0011001100000011 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D1 SD=alu_in_2[1] Z=alu_output_LUT4_Z_A_L6MUX21_Z_SD[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[0] Z=alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[19] Z=alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[20] Z=alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[0] Z=alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[17] Z=alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[18] Z=alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate LUT4 A=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[0] B=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[1] C=alu_in_2[1] D=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_LUT4_Z_A_L6MUX21_Z_SD[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1010110011111111 +.gate LUT4 A=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] B=alu_in_2[5] C=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] Z=alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000000000111 +.gate LUT4 A=$false B=alu_in_1[4] C=alu_in_1[5] D=alu_in_2[0] Z=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_1[2] C=alu_in_1[3] D=alu_in_2[0] Z=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_1[0] C=alu_in_1[1] D=alu_in_2[0] Z=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000100000000 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] C=alu_output_LUT4_Z_A_LUT4_Z_A[2] D=alu_output_LUT4_Z_A_LUT4_Z_A[3] Z=alu_output_LUT4_Z_A[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000011100000000 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[0] B=alu_output_LUT4_Z_A_LUT4_Z_1_B[1] C=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[5] Z=alu_output_LUT4_Z_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0101001100000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111100000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1 SD=alu_op_i[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[11] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000000000011 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[10] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000000000011 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_1_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_1_Z_PFUMX_BLUT_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_1_Z C0=alu_in_2[1] Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_2_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_C[3] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_1_Z_PFUMX_BLUT_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_1_Z C0=alu_in_2[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_1_Z_PFUMX_ALUT_Z D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z SD=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_C[3] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[3] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] B=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[1] C=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] D=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000010100000011 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1 SD=alu_in_2[4] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D1 SD=alu_op_i[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D0_PFUMX_Z_BLUT C0=alu_op_i[2] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D1_PFUMX_Z_BLUT C0=alu_op_i[2] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=alu_op_i[3] D=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011110000 +.gate LUT4 A=$false B=alu_in_2[5] C=alu_in_2[6] D=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000000000011 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_in_2[3] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[31] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[31] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 1111111011111111 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_in_2[3] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[31] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000100000000 +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[31] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] C=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[4] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0000001100000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D1 SD=alu_in_2[2] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[31] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[31] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000100000000 +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000100000000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B[0] C=alu_op_i[2] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B[2] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1111110000000000 +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[1] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 1111000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_1_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_1_BLUT C0=alu_op_i[2] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_op_i[1] B=alu_op_i[0] C=alu_in_1[0] D=alu_in_2[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_1_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0101110011001111 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_1_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1111111111111111 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B[0] C=sum[31] D=alu_op_i[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1100110000001111 +.gate CCU2C A0=alu_in_1[30] A1=alu_in_1[31] B0=alu_in_2[30] B1=alu_in_2[31] C0=$true C1=$true CIN=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[30] COUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B[0] D0=$true D1=$true S0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[30] S1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[31] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[8] A1=alu_in_1[9] B0=alu_in_2[8] B1=alu_in_2[9] C0=$true C1=$true CIN=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[8] COUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[10] D0=$true D1=$true S0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[8] S1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[9] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[6] A1=alu_in_1[7] B0=alu_in_2[6] B1=alu_in_2[7] C0=$true C1=$true CIN=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[6] COUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[8] D0=$true D1=$true S0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[6] S1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[16] A1=alu_in_1[17] B0=alu_in_2[16] B1=alu_in_2[17] C0=$true C1=$true CIN=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[16] COUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[18] D0=$true D1=$true S0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[16] S1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[17] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[14] A1=alu_in_1[15] B0=alu_in_2[14] B1=alu_in_2[15] C0=$true C1=$true CIN=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[14] COUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[16] D0=$true D1=$true S0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[14] S1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[15] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[12] A1=alu_in_1[13] B0=alu_in_2[12] B1=alu_in_2[13] C0=$true C1=$true CIN=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[12] COUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[14] D0=$true D1=$true S0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[12] S1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[13] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[10] A1=alu_in_1[11] B0=alu_in_2[10] B1=alu_in_2[11] C0=$true C1=$true CIN=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[10] COUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[12] D0=$true D1=$true S0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[10] S1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[11] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[0] A1=alu_in_1[1] B0=alu_in_2[0] B1=alu_in_2[1] C0=$true C1=$true CIN=$true COUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[2] D0=$true D1=$true S0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[0] S1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[4] A1=alu_in_1[5] B0=alu_in_2[4] B1=alu_in_2[5] C0=$true C1=$true CIN=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[4] COUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[6] D0=$true D1=$true S0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[4] S1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[2] A1=alu_in_1[3] B0=alu_in_2[2] B1=alu_in_2[3] C0=$true C1=$true CIN=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[2] COUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[4] D0=$true D1=$true S0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[2] S1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[28] A1=alu_in_1[29] B0=alu_in_2[28] B1=alu_in_2[29] C0=$true C1=$true CIN=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[28] COUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[30] D0=$true D1=$true S0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[28] S1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[29] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[26] A1=alu_in_1[27] B0=alu_in_2[26] B1=alu_in_2[27] C0=$true C1=$true CIN=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[26] COUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[28] D0=$true D1=$true S0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[26] S1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[27] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[24] A1=alu_in_1[25] B0=alu_in_2[24] B1=alu_in_2[25] C0=$true C1=$true CIN=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[24] COUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[26] D0=$true D1=$true S0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[24] S1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[25] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[22] A1=alu_in_1[23] B0=alu_in_2[22] B1=alu_in_2[23] C0=$true C1=$true CIN=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[22] COUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[24] D0=$true D1=$true S0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[22] S1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[23] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[20] A1=alu_in_1[21] B0=alu_in_2[20] B1=alu_in_2[21] C0=$true C1=$true CIN=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[20] COUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[22] D0=$true D1=$true S0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[20] S1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[21] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[18] A1=alu_in_1[19] B0=alu_in_2[18] B1=alu_in_2[19] C0=$true C1=$true CIN=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[18] COUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[20] D0=$true D1=$true S0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[18] S1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[19] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate LUT4 A=$false B=$false C=sum[0] D=alu_op_i[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1111111100001111 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[0] B=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] C=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[2] D=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[3] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0100111101000100 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[0] B=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] C=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[2] D=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[3] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000101100000000 +.gate LUT4 A=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] B=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[2] C=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000110100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1 SD=alu_op_i[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[13] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000000000011 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[12] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000000000011 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_1_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z C0=alu_in_2[1] Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_1_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111100000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1 SD=alu_op_i[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1 SD=alu_op_i[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[5] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000000000011 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[4] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000000000011 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[7] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000000000011 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[6] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000000000011 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_C[3] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_1_B[1] B=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[3] C=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] D=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1111010111110011 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[0] C=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[2] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000111100110011 +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[1] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100001111 +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[4] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 0000111100000000 +.gate LUT4 A=$false B=$false C=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[4] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 0000111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0[4] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A[0] B=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] C=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] D=sum[21] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000101110111011 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0_PFUMX_Z_BLUT C0=alu_op_i[2] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_op_i[1] B=alu_op_i[0] C=alu_in_1[21] D=alu_in_2[21] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0101110011001111 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1111111111111111 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1 SD=alu_op_i[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D1 SD=alu_in_2[3] Z=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D0_PFUMX_Z_BLUT C0=alu_in_2[31] Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D1_PFUMX_Z_BLUT C0=alu_in_2[31] Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000100000000 +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000100000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[9] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000000000011 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[8] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000000000011 +.gate LUT4 A=alu_in_1[29] B=alu_in_2[29] C=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] D=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_D[3] Z=alu_output_LUT4_Z_A_LUT4_Z_A[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000001111111 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[29] D=alu_in_2[29] Z=alu_output_LUT4_Z_A_LUT4_Z_A[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[3] C=alu_in_2[2] D=alu_in_2[3] Z=alu_output_LUT4_Z_A_LUT4_Z_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0000000000000011 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[23] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[21] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[24] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[22] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[19] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[17] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[20] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[18] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[27] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[25] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[28] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[26] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_PFUMX_Z_BLUT C0=alu_in_2[0] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=$false B=$false C=alu_in_1[30] D=alu_in_2[1] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1111111100001111 +.gate LUT4 A=$false B=alu_in_1[29] C=alu_in_1[31] D=alu_in_2[1] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000111100110011 +.gate LUT4 A=$false B=alu_op_i[0] C=alu_op_i[1] D=alu_op_i[2] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100000000000000 +.gate LUT4 A=alu_op_i[0] B=alu_op_i[1] C=alu_op_i[2] D=sum[29] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000100000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_BLUT C0=alu_output_PFUMX_Z_C0[4] Z=alu_output[31] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate PFUMX ALUT=alu_output_PFUMX_Z_1_ALUT BLUT=alu_output_PFUMX_Z_1_BLUT C0=alu_output_PFUMX_Z_1_C0[4] Z=alu_output[30] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate PFUMX ALUT=alu_output_PFUMX_Z_10_ALUT BLUT=alu_output_PFUMX_Z_10_BLUT C0=alu_output_PFUMX_Z_10_C0[4] Z=alu_output[10] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_PFUMX_Z_10_C0[0] B=alu_output_PFUMX_Z_10_C0[1] C=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] D=alu_output_PFUMX_Z_10_C0[3] Z=alu_output_PFUMX_Z_10_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1111111111100000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_10_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1111111111111111 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] B=sum[10] C=alu_output_PFUMX_Z_10_C0_LUT4_Z_C[2] D=alu_output_PFUMX_Z_10_C0_LUT4_Z_C[3] Z=alu_output_PFUMX_Z_10_C0[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000000000111 +.gate LUT4 A=alu_output_PFUMX_Z_10_C0_LUT4_Z_1_A[0] B=alu_output_PFUMX_Z_10_C0_LUT4_Z_1_A[1] C=alu_in_2[3] D=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] Z=alu_output_PFUMX_Z_10_C0[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0101001100000000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z[1] C=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B[1] D=alu_in_2[2] Z=alu_output_PFUMX_Z_10_C0_LUT4_Z_1_A[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1111000011001100 +.gate LUT4 A=$false B=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[0] C=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[1] D=alu_in_2[2] Z=alu_output_PFUMX_Z_10_C0_LUT4_Z_1_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1111000011001100 +.gate LUT4 A=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[0] B=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[1] C=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] Z=alu_output_PFUMX_Z_10_C0[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1010001100000000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] C=alu_in_1[10] D=alu_in_2[10] Z=alu_output_PFUMX_Z_10_C0_LUT4_Z_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100000000000000 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[10] D=alu_in_2[10] Z=alu_output_PFUMX_Z_10_C0_LUT4_Z_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_10_C0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_10_C0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] Z=alu_output_PFUMX_Z_10_C0[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[2] B=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[3] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_PFUMX_Z_10_C0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000110000000101 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_10_C0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_11_ALUT BLUT=alu_output_PFUMX_Z_11_BLUT C0=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[4] Z=alu_output[9] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] B=sum[9] C=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[2] D=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[3] Z=alu_output_PFUMX_Z_11_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1111111111111000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_11_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1111111111111111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_12_ALUT BLUT=alu_output_PFUMX_Z_12_BLUT C0=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] Z=alu_output[6] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D[0] B=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] C=alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D[2] D=alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_12_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1111010011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_12_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000011111111 +.gate LUT4 A=alu_output_PFUMX_Z_9_C0_LUT4_Z_A[0] B=alu_output_PFUMX_Z_9_C0_LUT4_Z_A[1] C=alu_in_2[3] D=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] Z=alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100010100000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D_PFUMX_Z_BLUT C0=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[4] Z=alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate PFUMX ALUT=alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D_PFUMX_Z_1_ALUT BLUT=alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D_PFUMX_Z_1_BLUT C0=alu_in_2[3] Z=alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z[2] Z=alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D_PFUMX_Z_1_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B[2] C=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z[1] D=alu_in_2[2] Z=alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D_PFUMX_Z_1_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1111000011001100 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] B=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[1] C=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[2] D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[3] Z=alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_13_ALUT BLUT=alu_output_PFUMX_Z_13_BLUT C0=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[4] Z=alu_output[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[0] B=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[1] C=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] D=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[3] Z=alu_output_PFUMX_Z_13_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1111111100010000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_13_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1111111111111111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_14_ALUT BLUT=alu_output_PFUMX_Z_14_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[4] Z=alu_output[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] B=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] C=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[2] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[3] Z=alu_output_PFUMX_Z_14_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1111111101000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_14_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1111111111111111 +.gate LUT4 A=alu_output_PFUMX_Z_1_C0[0] B=alu_output_PFUMX_Z_1_C0[1] C=alu_output_PFUMX_Z_1_C0[2] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] Z=alu_output_PFUMX_Z_1_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000000011111110 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_1_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1111111111111111 +.gate LUT4 A=alu_output_PFUMX_Z_1_C0_LUT4_Z_A[0] B=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] C=alu_output_PFUMX_Z_1_C0_LUT4_Z_C[2] D=alu_output_PFUMX_Z_1_C0_LUT4_Z_C[3] Z=alu_output_PFUMX_Z_1_C0[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000011100000000 +.gate LUT4 A=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[1] B=alu_in_2[2] C=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C[2] D=alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] Z=alu_output_PFUMX_Z_1_C0[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000101100000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[3] B=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_B[1] C=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] D=alu_in_2[1] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000010100000011 +.gate LUT4 A=$false B=alu_in_1[27] C=alu_in_1[28] D=alu_in_2[0] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_1[25] C=alu_in_1[26] D=alu_in_2[0] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_1[23] C=alu_in_1[24] D=alu_in_2[0] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_1[21] C=alu_in_1[22] D=alu_in_2[0] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_1[29] C=alu_in_1[30] D=alu_in_2[0] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_B[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A[0] B=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[0] C=alu_in_2[2] D=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] Z=alu_output_PFUMX_Z_1_C0[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1010110000000000 +.gate LUT4 A=$false B=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A[0] C=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[0] D=alu_in_2[2] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0011001100001111 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[1] C=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[1] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0000000000111111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z_PFUMX_Z_BLUT C0=alu_output_PFUMX_Z_9_C0_LUT4_Z_A[4] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_PFUMX_Z_9_C0_LUT4_Z_A[0] B=alu_output_PFUMX_Z_9_C0_LUT4_Z_A[1] C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] D=alu_in_2[3] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0011111110101111 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[2] B=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[3] C=alu_in_2[1] D=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1010110011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[2] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A_LUT4_D_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[3] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A_LUT4_D_1_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A_LUT4_D_Z BLUT=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A_LUT4_D_1_Z C0=alu_in_2[1] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A_LUT4_D_Z_PFUMX_ALUT_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate L6MUX21 D0=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A_LUT4_D_Z_PFUMX_ALUT_Z D1=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z SD=alu_in_2[2] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate LUT4 A=$false B=alu_in_1[17] C=alu_in_1[18] D=alu_in_2[0] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_1[15] C=alu_in_1[16] D=alu_in_2[0] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[1] B=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B[0] C=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[5] Z=alu_output_PFUMX_Z_1_C0[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1010001100000000 +.gate LUT4 A=$false B=alu_in_2[2] C=alu_in_2[3] D=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0000001100000000 +.gate LUT4 A=alu_in_1[30] B=alu_in_2[30] C=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] D=alu_output_PFUMX_Z_1_C0_LUT4_Z_C_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000001111111 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[30] D=alu_in_2[30] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=alu_op_i[0] B=alu_op_i[1] C=alu_op_i[2] D=sum[30] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_C_LUT4_Z_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000100000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_ALUT BLUT=alu_output_PFUMX_Z_2_BLUT C0=alu_output_PFUMX_Z_2_C0[4] Z=alu_output[27] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_PFUMX_Z_2_C0[0] B=alu_output_PFUMX_Z_2_C0[1] C=alu_output_PFUMX_Z_2_C0[2] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] Z=alu_output_PFUMX_Z_2_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000000011111110 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1111111111111111 +.gate LUT4 A=$false B=alu_output_PFUMX_Z_2_C0_LUT4_Z_B[0] C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] D=alu_output_PFUMX_Z_2_C0_LUT4_Z_B[2] Z=alu_output_PFUMX_Z_2_C0[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0011111100000000 +.gate LUT4 A=alu_output_PFUMX_Z_C0_LUT4_Z_1_A[1] B=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B[1] C=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] D=alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] Z=alu_output_PFUMX_Z_2_C0[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0101001100000000 +.gate LUT4 A=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A[0] B=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] C=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[3] D=alu_in_2[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1111000001000100 +.gate LUT4 A=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A[0] B=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_B[2] C=alu_in_2[1] D=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1010110011111111 +.gate LUT4 A=$false B=alu_in_1[28] C=alu_in_1[29] D=alu_in_2[0] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_B[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111100000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1 SD=alu_op_i[0] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[19] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000000000011 +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[18] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000000000011 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1 SD=alu_op_i[0] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[21] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000000000011 +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[20] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000000000011 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z C0=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_D1 SD=alu_in_2[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 1111111100000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z SD=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1 SD=alu_in_2[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[3] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[2] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 1111111100000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1 SD=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D1 SD=alu_in_2[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_C[3] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000011111111 +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1 SD=alu_in_2[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000011111111 +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] D=alu_in_2[5] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 1111000000000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] B=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[2] C=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] D=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000110100000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1 SD=alu_op_i[0] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[17] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000000000011 +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[16] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000000000011 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_1_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z C0=alu_in_2[1] Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[2] C=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[3] D=alu_in_2[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_1[26] C=alu_in_1[27] D=alu_in_2[0] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_9_B_LUT4_Z_1_B[1] D=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] Z=alu_output_PFUMX_Z_2_C0[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 0000111100000000 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] B=alu_output_LUT4_Z_9_B_LUT4_Z_1_B[0] C=alu_output_LUT4_Z_9_B_LUT4_Z_1_C[2] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[5] Z=alu_output_PFUMX_Z_2_C0[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1111000100000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D1 SD=alu_op_i[2] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_B[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[27] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=sum[27] C=alu_op_i[1] D=alu_op_i[0] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111111110011 +.gate LUT4 A=$false B=sum[27] C=alu_op_i[1] D=alu_op_i[0] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111111110011 +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[27] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=alu_op_i[1] C=alu_op_i[0] D=alu_in_1[27] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0011001111110000 +.gate LUT4 A=$false B=$false C=alu_op_i[0] D=alu_in_1[27] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111000011111111 +.gate LUT4 A=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[0] B=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[1] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_B[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000110000000101 +.gate PFUMX ALUT=alu_output_PFUMX_Z_3_ALUT BLUT=alu_output_PFUMX_Z_3_BLUT C0=alu_output_PFUMX_Z_3_C0[4] Z=alu_output[26] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_PFUMX_Z_3_C0[0] B=alu_output_PFUMX_Z_3_C0[1] C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] D=alu_output_PFUMX_Z_3_C0[3] Z=alu_output_PFUMX_Z_3_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1111111100001011 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_3_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1111111111111111 +.gate L6MUX21 D0=alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] Z=alu_output_PFUMX_Z_3_C0[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[2] Z=alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111100001111 +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[2] Z=alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100001111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[0] C=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[2] Z=alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0011001100000011 +.gate LUT4 A=$false B=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[1] C=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[2] Z=alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0011001100000011 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] B=sum[26] C=alu_output_PFUMX_Z_3_C0_LUT4_Z_C[2] D=alu_output_PFUMX_Z_3_C0_LUT4_Z_C[3] Z=alu_output_PFUMX_Z_3_C0[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000000000111 +.gate LUT4 A=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[0] B=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[1] C=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[5] Z=alu_output_PFUMX_Z_3_C0[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1010001100000000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] C=alu_in_1[26] D=alu_in_2[26] Z=alu_output_PFUMX_Z_3_C0_LUT4_Z_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100000000000000 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[26] D=alu_in_2[26] Z=alu_output_PFUMX_Z_3_C0_LUT4_Z_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_3_C0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_3_C0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] Z=alu_output_PFUMX_Z_3_C0[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[2] B=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[3] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_PFUMX_Z_3_C0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000110000000101 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_3_C0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_4_ALUT BLUT=alu_output_PFUMX_Z_4_BLUT C0=alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z[4] Z=alu_output[23] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z[3] Z=alu_output_PFUMX_Z_4_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000000011111111 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] B=alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z[1] C=alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z[2] D=alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z[3] Z=alu_output_PFUMX_Z_4_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0001111111111111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_5_ALUT BLUT=alu_output_PFUMX_Z_5_BLUT C0=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z[4] Z=alu_output[22] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z[3] Z=alu_output_PFUMX_Z_5_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000000011111111 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] B=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z[1] C=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z[2] D=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z[3] Z=alu_output_PFUMX_Z_5_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0001111111111111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_6_ALUT BLUT=alu_output_PFUMX_Z_6_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[4] Z=alu_output[21] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[0] B=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[1] C=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[3] Z=alu_output_PFUMX_Z_6_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1111010011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[3] Z=alu_output_PFUMX_Z_6_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_7_ALUT BLUT=alu_output_PFUMX_Z_7_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[4] Z=alu_output[17] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[0] B=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[1] C=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[2] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[3] Z=alu_output_PFUMX_Z_7_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1111100011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[3] Z=alu_output_PFUMX_Z_7_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_8_ALUT BLUT=alu_output_PFUMX_Z_8_BLUT C0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[4] Z=alu_output[16] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[0] B=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[1] C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] D=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[0] Z=alu_output_PFUMX_Z_8_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0100010011110100 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_8_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1111111111111111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_ALUT BLUT=alu_output_PFUMX_Z_9_BLUT C0=alu_output_PFUMX_Z_9_C0[4] Z=alu_output[14] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_PFUMX_Z_9_C0[0] B=alu_output_PFUMX_Z_9_C0[1] C=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] D=alu_output_PFUMX_Z_9_C0[3] Z=alu_output_PFUMX_Z_9_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1111111111100000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_9_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1111111111111111 +.gate LUT4 A=alu_output_PFUMX_Z_9_C0_LUT4_Z_A[0] B=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z[2] C=alu_in_2[3] D=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] Z=alu_output_PFUMX_Z_9_C0[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0101001100000000 +.gate LUT4 A=$false B=$false C=alu_output_PFUMX_Z_1_C0_LUT4_Z_A[0] D=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] Z=alu_output_PFUMX_Z_9_C0[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 1111000000000000 +.gate LUT4 A=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[1] B=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B[0] C=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] Z=alu_output_PFUMX_Z_9_C0[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1010001100000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_in_2[2] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_in_2[2] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[2] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[2] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_1_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_1_Z C0=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=alu_in_1[13] C=alu_in_1[14] D=alu_in_2[0] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_1[11] C=alu_in_1[12] D=alu_in_2[0] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] C=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] D=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0011001100001111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z C0=alu_in_2[2] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[2] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate L6MUX21 D0=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D1 SD=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[0] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[5] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[6] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[0] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[3] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[4] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[2] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[2] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_1_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_1_Z C0=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate L6MUX21 D0=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z D1=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_D1 SD=alu_in_2[2] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[2] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 1111111100000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0 D1=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z SD=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1 SD=alu_in_2[2] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 1111111111111111 +.gate LUT4 A=$false B=$false C=alu_in_2[31] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 1111111111110000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 1111111111111111 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 1111111111111111 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] C=alu_in_2[6] D=alu_in_1[6] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100000000000000 +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] D=sum[6] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 1111000000000000 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_2[6] D=alu_in_1[6] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0 D1=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z SD=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0_PFUMX_Z_BLUT C0=alu_in_2[2] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z SD=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0 D1=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1 SD=alu_in_2[4] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_PFUMX_Z_BLUT C0=alu_in_2[31] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111011111111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_PFUMX_Z_BLUT C0=alu_in_2[31] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000100000000 +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000100000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_in_2[2] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=$false B=alu_op_i[2] C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[2] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000000011111100 +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[1] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000011110000 +.gate LUT4 A=$false B=alu_in_1[9] C=alu_in_1[10] D=alu_in_2[0] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_1[7] C=alu_in_1[8] D=alu_in_2[0] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B[0] C=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0000000011001111 +.gate L6MUX21 D0=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D1 SD=alu_op_i[2] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[22] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=sum[22] C=alu_op_i[1] D=alu_op_i[0] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111111110011 +.gate LUT4 A=$false B=sum[22] C=alu_op_i[1] D=alu_op_i[0] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111111110011 +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[22] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=alu_op_i[1] C=alu_op_i[0] D=alu_in_1[22] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0011001111110000 +.gate LUT4 A=$false B=$false C=alu_op_i[0] D=alu_in_1[22] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111000011111111 +.gate LUT4 A=$false B=$false C=alu_in_2[2] D=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 0000111100000000 +.gate LUT4 A=$false B=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[1] C=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[2] D=alu_in_2[2] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1111000011001100 +.gate L6MUX21 D0=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate L6MUX21 D0=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D0 D1=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D1 SD=alu_in_2[0] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[24] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[22] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[25] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[23] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate L6MUX21 D0=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D0 D1=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D1 SD=alu_in_2[0] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[20] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[18] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[21] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[19] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[28] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[26] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[29] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[27] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate LUT4 A=alu_in_1[30] B=alu_in_1[31] C=alu_in_2[1] D=alu_in_2[0] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000110000001010 +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_PFUMX_Z_BLUT C0=alu_output_PFUMX_Z_9_C0_PFUMX_Z_C0[4] Z=alu_output_PFUMX_Z_9_C0[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_9_C0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] B=alu_output_PFUMX_Z_9_C0_PFUMX_Z_C0[1] C=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] D=sum[14] Z=alu_output_PFUMX_Z_9_C0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000011101110111 +.gate LUT4 A=$false B=$false C=alu_in_1[14] D=alu_in_2[14] Z=alu_output_PFUMX_Z_9_C0_PFUMX_Z_C0[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 1111000000000000 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[14] D=alu_in_2[14] Z=alu_output_PFUMX_Z_9_C0_PFUMX_Z_C0[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=alu_output_PFUMX_Z_C0[0] B=alu_output_PFUMX_Z_C0[1] C=alu_output_PFUMX_Z_C0[2] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] Z=alu_output_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000000011111110 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1111111111111111 +.gate LUT4 A=alu_output_PFUMX_Z_C0_LUT4_Z_A[1] B=alu_output_PFUMX_Z_C0_LUT4_Z_B[0] C=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[5] Z=alu_output_PFUMX_Z_C0[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0101001100000000 +.gate LUT4 A=alu_output_PFUMX_Z_C0_LUT4_Z_1_A[0] B=alu_output_PFUMX_Z_C0_LUT4_Z_1_A[1] C=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] D=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] Z=alu_output_PFUMX_Z_C0[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0101001100000000 +.gate LUT4 A=$false B=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] C=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[2] D=alu_in_2[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] C=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] D=alu_in_2[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1 SD=alu_op_i[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1 SD=alu_op_i[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[23] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000000000011 +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[22] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000000000011 +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[25] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000000000011 +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[24] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000000000011 +.gate LUT4 A=$false B=alu_output_PFUMX_Z_C0_LUT4_Z_2_B[0] C=alu_output_PFUMX_Z_C0_LUT4_Z_2_B[1] D=alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] Z=alu_output_PFUMX_Z_C0[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0000001100000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_PFUMX_Z_C0_LUT4_Z_2_B[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] Z=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] Z=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_B[2] Z=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[30] C=alu_in_1[31] D=alu_in_2[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0011001100001111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_2_B[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A[0] B=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] C=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[3] D=alu_in_2[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1111000001000100 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_in_2[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 1111111111111111 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 1111111100000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_in_2[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 1111111100000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1 SD=alu_op_i[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[3] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000000000011 +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[2] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000000000011 +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[2] D=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 0000111100000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[2] D=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000111100000000 +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[2] D=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000111100000000 +.gate LUT4 A=$false B=$false C=alu_output_PFUMX_Z_C0_LUT4_Z_A[1] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 0000111100000000 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] B=sum[7] C=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_C[2] D=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_C[3] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000000000111 +.gate LUT4 A=$false B=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] C=alu_in_2[3] D=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0011111100000000 +.gate LUT4 A=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A[0] B=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[0] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000110000001010 +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_ALUT_LUT4_Z_D[2] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=alu_in_1[9] C=alu_in_1[10] D=alu_in_2[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_ALUT_LUT4_Z_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1111000011001100 +.gate LUT4 A=$false B=alu_in_1[7] C=alu_in_1[8] D=alu_in_2[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000111100110011 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] C=alu_in_1[7] D=alu_in_2[7] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100000000000000 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[7] D=alu_in_2[7] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1 SD=alu_op_i[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[15] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000000000011 +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[14] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000000000011 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_1_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_1_Z BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_1_Z C0=alu_in_2[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_1_Z_PFUMX_ALUT_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_C[3] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=alu_output_PFUMX_Z_C0_LUT4_Z_B[0] C=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0000000011001111 +.gate LUT4 A=$false B=alu_output_PFUMX_Z_C0_LUT4_Z_1_A[0] C=alu_output_PFUMX_Z_C0_LUT4_Z_1_A[1] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[1] C=alu_output_PFUMX_Z_C0_LUT4_Z_A[1] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0000000011110011 +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT C0=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[4] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] B=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[1] C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] D=alu_in_2[3] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0011111110101111 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_PFUMX_Z_BLUT C0=alu_output_PFUMX_Z_C0_PFUMX_Z_C0[4] Z=alu_output_PFUMX_Z_C0[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] B=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[1] C=alu_in_2[3] D=alu_output_PFUMX_Z_C0_PFUMX_Z_C0[3] Z=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000000011110111 +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1 SD=alu_op_i[2] Z=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[23] Z=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=sum[23] C=alu_op_i[1] D=alu_op_i[0] Z=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111111110011 +.gate LUT4 A=$false B=sum[23] C=alu_op_i[1] D=alu_op_i[0] Z=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111111110011 +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[23] Z=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=alu_op_i[1] C=alu_op_i[0] D=alu_in_1[23] Z=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0011001111110000 +.gate LUT4 A=$false B=$false C=alu_op_i[0] D=alu_in_1[23] Z=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111000011111111 +.gate LUT4 A=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] B=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[1] C=alu_in_2[3] D=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100010100000000 +.gate LUT4 A=$false B=alu_in_2[3] C=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[1] D=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0011000000000000 +.gate LUT4 A=alu_in_2[0] B=alu_in_2[1] C=alu_in_2[2] D=alu_in_1[31] Z=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000100000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_in_1[31] B=alu_in_2[31] C=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] D=alu_output_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_C0_PFUMX_Z_C0[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000001111111 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[31] D=alu_in_2[31] Z=alu_output_PFUMX_Z_C0_PFUMX_Z_C0[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=alu_op_i[0] B=alu_op_i[1] C=alu_op_i[2] D=sum[31] Z=alu_output_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000100000000 +.gate CCU2C A0=$false A1=$false B0=complement2_CCU2C_S0_B0[8] B1=complement2_CCU2C_S0_B0[9] C0=$false C1=$false CIN=complement2_CCU2C_S0_COUT[8] COUT=complement2_CCU2C_S0_COUT[10] D0=$true D1=$true S0=complement2[8] S1=complement2[9] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=$false A1=$false B0=complement2_CCU2C_S0_B0[6] B1=complement2_CCU2C_S0_B0[7] C0=$false C1=$false CIN=complement2_CCU2C_S0_COUT[6] COUT=complement2_CCU2C_S0_COUT[8] D0=$true D1=$true S0=complement2[6] S1=complement2[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=$false A1=$false B0=complement2_CCU2C_S0_B0[18] B1=complement2_CCU2C_S0_B0[19] C0=$false C1=$false CIN=complement2_CCU2C_S0_COUT[18] COUT=complement2_CCU2C_S0_COUT[20] D0=$true D1=$true S0=complement2[18] S1=complement2[19] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=$false A1=$false B0=complement2_CCU2C_S0_B0[16] B1=complement2_CCU2C_S0_B0[17] C0=$false C1=$false CIN=complement2_CCU2C_S0_COUT[16] COUT=complement2_CCU2C_S0_COUT[18] D0=$true D1=$true S0=complement2[16] S1=complement2[17] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=$false A1=$false B0=complement2_CCU2C_S0_B0[14] B1=complement2_CCU2C_S0_B0[15] C0=$false C1=$false CIN=complement2_CCU2C_S0_COUT[14] COUT=complement2_CCU2C_S0_COUT[16] D0=$true D1=$true S0=complement2[14] S1=complement2[15] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=$false A1=$false B0=complement2_CCU2C_S0_B0[12] B1=complement2_CCU2C_S0_B0[13] C0=$false C1=$false CIN=complement2_CCU2C_S0_COUT[12] COUT=complement2_CCU2C_S0_COUT[14] D0=$true D1=$true S0=complement2[12] S1=complement2[13] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=$false A1=$false B0=complement2_CCU2C_S0_B0[10] B1=complement2_CCU2C_S0_B0[11] C0=$false C1=$false CIN=complement2_CCU2C_S0_COUT[10] COUT=complement2_CCU2C_S0_COUT[12] D0=$true D1=$true S0=complement2[10] S1=complement2[11] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=$true A1=$false B0=complement2_CCU2C_S0_B0[0] B1=complement2_CCU2C_S0_B0[1] C0=$false C1=$false CIN=$false COUT=complement2_CCU2C_S0_COUT[2] D0=$true D1=$true S0=complement2[0] S1=complement2[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=$false A1=$false B0=complement2_CCU2C_S0_B0[4] B1=complement2_CCU2C_S0_B0[5] C0=$false C1=$false CIN=complement2_CCU2C_S0_COUT[4] COUT=complement2_CCU2C_S0_COUT[6] D0=$true D1=$true S0=complement2[4] S1=complement2[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=$false A1=$false B0=complement2_CCU2C_S0_B0[30] B1=complement2_CCU2C_S0_B0[31] C0=$false C1=$false CIN=complement2_CCU2C_S0_COUT[30] COUT=complement2_CCU2C_S0_3_COUT[31] D0=$true D1=$true S0=complement2[30] S1=complement2[31] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=$false A1=$false B0=complement2_CCU2C_S0_B0[2] B1=complement2_CCU2C_S0_B0[3] C0=$false C1=$false CIN=complement2_CCU2C_S0_COUT[2] COUT=complement2_CCU2C_S0_COUT[4] D0=$true D1=$true S0=complement2[2] S1=complement2[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=$false A1=$false B0=complement2_CCU2C_S0_B0[28] B1=complement2_CCU2C_S0_B0[29] C0=$false C1=$false CIN=complement2_CCU2C_S0_COUT[28] COUT=complement2_CCU2C_S0_COUT[30] D0=$true D1=$true S0=complement2[28] S1=complement2[29] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=$false A1=$false B0=complement2_CCU2C_S0_B0[26] B1=complement2_CCU2C_S0_B0[27] C0=$false C1=$false CIN=complement2_CCU2C_S0_COUT[26] COUT=complement2_CCU2C_S0_COUT[28] D0=$true D1=$true S0=complement2[26] S1=complement2[27] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=$false A1=$false B0=complement2_CCU2C_S0_B0[24] B1=complement2_CCU2C_S0_B0[25] C0=$false C1=$false CIN=complement2_CCU2C_S0_COUT[24] COUT=complement2_CCU2C_S0_COUT[26] D0=$true D1=$true S0=complement2[24] S1=complement2[25] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=$false A1=$false B0=complement2_CCU2C_S0_B0[22] B1=complement2_CCU2C_S0_B0[23] C0=$false C1=$false CIN=complement2_CCU2C_S0_COUT[22] COUT=complement2_CCU2C_S0_COUT[24] D0=$true D1=$true S0=complement2[22] S1=complement2[23] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=$false A1=$false B0=complement2_CCU2C_S0_B0[20] B1=complement2_CCU2C_S0_B0[21] C0=$false C1=$false CIN=complement2_CCU2C_S0_COUT[20] COUT=complement2_CCU2C_S0_COUT[22] D0=$true D1=$true S0=complement2[20] S1=complement2[21] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[29] Z=complement2_CCU2C_S0_B0[29] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[31] Z=complement2_CCU2C_S0_B0[31] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[21] Z=complement2_CCU2C_S0_B0[21] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[20] Z=complement2_CCU2C_S0_B0[20] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[19] Z=complement2_CCU2C_S0_B0[19] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[18] Z=complement2_CCU2C_S0_B0[18] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[17] Z=complement2_CCU2C_S0_B0[17] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[16] Z=complement2_CCU2C_S0_B0[16] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[15] Z=complement2_CCU2C_S0_B0[15] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[14] Z=complement2_CCU2C_S0_B0[14] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[13] Z=complement2_CCU2C_S0_B0[13] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[12] Z=complement2_CCU2C_S0_B0[12] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[30] Z=complement2_CCU2C_S0_B0[30] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[11] Z=complement2_CCU2C_S0_B0[11] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[10] Z=complement2_CCU2C_S0_B0[10] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[9] Z=complement2_CCU2C_S0_B0[9] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[8] Z=complement2_CCU2C_S0_B0[8] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[7] Z=complement2_CCU2C_S0_B0[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[6] Z=complement2_CCU2C_S0_B0[6] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[5] Z=complement2_CCU2C_S0_B0[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[4] Z=complement2_CCU2C_S0_B0[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[3] Z=complement2_CCU2C_S0_B0[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[2] Z=complement2_CCU2C_S0_B0[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[28] Z=complement2_CCU2C_S0_B0[28] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[1] Z=complement2_CCU2C_S0_B0[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[0] Z=complement2_CCU2C_S0_B0[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[27] Z=complement2_CCU2C_S0_B0[27] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[26] Z=complement2_CCU2C_S0_B0[26] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[25] Z=complement2_CCU2C_S0_B0[25] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[24] Z=complement2_CCU2C_S0_B0[24] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[23] Z=complement2_CCU2C_S0_B0[23] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[22] Z=complement2_CCU2C_S0_B0[22] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=alu_in_2[31] C=complement2[31] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[31] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[30] C=complement2[30] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[30] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[21] C=complement2[21] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[21] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[20] C=complement2[20] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[20] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[19] C=complement2[19] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[19] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[18] C=complement2[18] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[18] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[17] C=complement2[17] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[17] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[16] C=complement2[16] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[16] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[15] C=complement2[15] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[15] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[14] C=complement2[14] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[14] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[13] C=complement2[13] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[13] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[12] C=complement2[12] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[12] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[29] C=complement2[29] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[29] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[11] C=complement2[11] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[11] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[10] C=complement2[10] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[10] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[9] C=complement2[9] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[9] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[8] C=complement2[8] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[8] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[7] C=complement2[7] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[6] C=complement2[6] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[6] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[5] C=complement2[5] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[4] C=complement2[4] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[3] C=complement2[3] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[2] C=complement2[2] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[28] C=complement2[28] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[28] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[1] C=complement2[1] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[0] C=complement2[0] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[27] C=complement2[27] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[27] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[26] C=complement2[26] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[26] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[25] C=complement2[25] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[25] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[24] C=complement2[24] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[24] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[23] C=complement2[23] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[23] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[22] C=complement2[22] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[22] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_op_i[0] C=alu_op_i[1] D=alu_op_i[3] Z=complement2_LUT4_C_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0000000011001111 +.gate CCU2C A0=alu_in_1[8] A1=alu_in_1[9] B0=sum_CCU2C_S0_B0[8] B1=sum_CCU2C_S0_B0[9] C0=$false C1=$false CIN=sum_CCU2C_S0_COUT[8] COUT=sum_CCU2C_S0_COUT[10] D0=$true D1=$true S0=sum[8] S1=sum[9] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[6] A1=alu_in_1[7] B0=sum_CCU2C_S0_B0[6] B1=sum_CCU2C_S0_B0[7] C0=$false C1=$false CIN=sum_CCU2C_S0_COUT[6] COUT=sum_CCU2C_S0_COUT[8] D0=$true D1=$true S0=sum[6] S1=sum[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[18] A1=alu_in_1[19] B0=sum_CCU2C_S0_B0[18] B1=sum_CCU2C_S0_B0[19] C0=$false C1=$false CIN=sum_CCU2C_S0_COUT[18] COUT=sum_CCU2C_S0_COUT[20] D0=$true D1=$true S0=sum[18] S1=sum[19] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[16] A1=alu_in_1[17] B0=sum_CCU2C_S0_B0[16] B1=sum_CCU2C_S0_B0[17] C0=$false C1=$false CIN=sum_CCU2C_S0_COUT[16] COUT=sum_CCU2C_S0_COUT[18] D0=$true D1=$true S0=sum[16] S1=sum[17] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[14] A1=alu_in_1[15] B0=sum_CCU2C_S0_B0[14] B1=sum_CCU2C_S0_B0[15] C0=$false C1=$false CIN=sum_CCU2C_S0_COUT[14] COUT=sum_CCU2C_S0_COUT[16] D0=$true D1=$true S0=sum[14] S1=sum[15] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[12] A1=alu_in_1[13] B0=sum_CCU2C_S0_B0[12] B1=sum_CCU2C_S0_B0[13] C0=$false C1=$false CIN=sum_CCU2C_S0_COUT[12] COUT=sum_CCU2C_S0_COUT[14] D0=$true D1=$true S0=sum[12] S1=sum[13] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[10] A1=alu_in_1[11] B0=sum_CCU2C_S0_B0[10] B1=sum_CCU2C_S0_B0[11] C0=$false C1=$false CIN=sum_CCU2C_S0_COUT[10] COUT=sum_CCU2C_S0_COUT[12] D0=$true D1=$true S0=sum[10] S1=sum[11] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[0] A1=alu_in_1[1] B0=sum_CCU2C_S0_B0[0] B1=sum_CCU2C_S0_B0[1] C0=$false C1=$false CIN=$false COUT=sum_CCU2C_S0_COUT[2] D0=$true D1=$true S0=sum[0] S1=sum[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[4] A1=alu_in_1[5] B0=sum_CCU2C_S0_B0[4] B1=sum_CCU2C_S0_B0[5] C0=$false C1=$false CIN=sum_CCU2C_S0_COUT[4] COUT=sum_CCU2C_S0_COUT[6] D0=$true D1=$true S0=sum[4] S1=sum[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[30] A1=alu_in_1[31] B0=sum_CCU2C_S0_B0[30] B1=sum_CCU2C_S0_B0[31] C0=$false C1=$false CIN=sum_CCU2C_S0_COUT[30] COUT=sum_CCU2C_S0_3_COUT[31] D0=$true D1=$true S0=sum[30] S1=sum[31] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[2] A1=alu_in_1[3] B0=sum_CCU2C_S0_B0[2] B1=sum_CCU2C_S0_B0[3] C0=$false C1=$false CIN=sum_CCU2C_S0_COUT[2] COUT=sum_CCU2C_S0_COUT[4] D0=$true D1=$true S0=sum[2] S1=sum[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[28] A1=alu_in_1[29] B0=sum_CCU2C_S0_B0[28] B1=sum_CCU2C_S0_B0[29] C0=$false C1=$false CIN=sum_CCU2C_S0_COUT[28] COUT=sum_CCU2C_S0_COUT[30] D0=$true D1=$true S0=sum[28] S1=sum[29] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[26] A1=alu_in_1[27] B0=sum_CCU2C_S0_B0[26] B1=sum_CCU2C_S0_B0[27] C0=$false C1=$false CIN=sum_CCU2C_S0_COUT[26] COUT=sum_CCU2C_S0_COUT[28] D0=$true D1=$true S0=sum[26] S1=sum[27] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[24] A1=alu_in_1[25] B0=sum_CCU2C_S0_B0[24] B1=sum_CCU2C_S0_B0[25] C0=$false C1=$false CIN=sum_CCU2C_S0_COUT[24] COUT=sum_CCU2C_S0_COUT[26] D0=$true D1=$true S0=sum[24] S1=sum[25] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[22] A1=alu_in_1[23] B0=sum_CCU2C_S0_B0[22] B1=sum_CCU2C_S0_B0[23] C0=$false C1=$false CIN=sum_CCU2C_S0_COUT[22] COUT=sum_CCU2C_S0_COUT[24] D0=$true D1=$true S0=sum[22] S1=sum[23] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[20] A1=alu_in_1[21] B0=sum_CCU2C_S0_B0[20] B1=sum_CCU2C_S0_B0[21] C0=$false C1=$false CIN=sum_CCU2C_S0_COUT[20] COUT=sum_CCU2C_S0_COUT[22] D0=$true D1=$true S0=sum[20] S1=sum[21] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.names alu_output_LUT4_Z_A_LUT4_Z_1_C[4] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B[1] +1 1 +.names alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B[2] +1 1 +.names alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[0] +1 1 +.names alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] +1 1 +.names alu_in_2[1] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[4] +1 1 +.names alu_in_2[2] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[5] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[6] +1 1 +.names alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[2] alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] +1 1 +.names alu_in_2[3] alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] +1 1 +.names alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[4] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[5] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD[2] alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[1] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[2] +1 1 +.names alu_in_2[5] alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[3] +1 1 +.names alu_in_2[2] alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[4] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[0] alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[0] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[1] alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_C[4] alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[4] +1 1 +.names alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[5] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[4] alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[6] +1 1 +.names alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[3] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_1_D[0] +1 1 +.names alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[2] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_1_D[1] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_1_D[2] +1 1 +.names alu_in_2[1] alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[4] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[5] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[6] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A[0] alu_output_LUT4_Z_3_C_LUT4_Z_C[0] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] alu_output_LUT4_Z_3_C_LUT4_Z_C[1] +1 1 +.names alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[0] alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B[0] +1 1 +.names alu_in_2[2] alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B[2] +1 1 +.names alu_in_1[7] alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_ALUT_LUT4_Z_D[0] +1 1 +.names alu_in_1[8] alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_ALUT_LUT4_Z_D[1] +1 1 +.names alu_in_2[0] alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_ALUT_LUT4_Z_D[3] +1 1 +.names alu_in_2[1] alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_ALUT_LUT4_Z_D[4] +1 1 +.names alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[0] alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A[1] +1 1 +.names alu_in_2[3] alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A[2] +1 1 +.names alu_in_2[2] alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A[3] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[2] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B[1] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B[1] +1 1 +.names alu_in_2[2] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B[2] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A[0] alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0[0] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0[1] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0[2] +1 1 +.names sum[21] alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0[3] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[2] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A[1] +1 1 +.names alu_in_2[3] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A[3] +1 1 +.names alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A[4] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A[5] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] alu_output_LUT4_Z_A[2] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] alu_output_PFUMX_Z_9_C0_PFUMX_Z_C0[0] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_PFUMX_Z_9_C0_PFUMX_Z_C0[2] +1 1 +.names sum[14] alu_output_PFUMX_Z_9_C0_PFUMX_Z_C0[3] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] alu_output_LUT4_Z_A_LUT4_Z_A[1] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_C[4] alu_output_LUT4_Z_10_B_LUT4_Z_1_B[0] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] alu_output_LUT4_Z_10_B_LUT4_Z_1_B[3] +1 1 +.names alu_in_1[29] alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_D[0] +1 1 +.names alu_in_2[29] alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_D[1] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_D[2] +1 1 +.names sum[9] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[1] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] alu_output_LUT4_Z_10_B_LUT4_Z_2_A[3] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] alu_output_PFUMX_Z_1_C0_LUT4_Z_A[1] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[0] alu_output_LUT4_Z_A_LUT4_Z_1_B[0] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_C[4] alu_output_LUT4_Z_A_LUT4_Z_1_B[2] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[5] alu_output_LUT4_Z_A_LUT4_Z_1_B[3] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[3] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[4] +1 1 +.names alu_in_2[3] alu_output_PFUMX_Z_10_C0_LUT4_Z_1_A[2] +1 1 +.names alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] alu_output_PFUMX_Z_10_C0_LUT4_Z_1_A[3] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[0] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_C[3] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[2] +1 1 +.names alu_in_2[1] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[4] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[5] +1 1 +.names alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[2] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[4] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[5] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] alu_output_PFUMX_Z_10_C0[2] +1 1 +.names alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[0] +1 1 +.names alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] +1 1 +.names alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[2] +1 1 +.names alu_in_2[1] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[4] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[5] +1 1 +.names alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] alu_output_LUT4_Z_8_A_LUT4_Z_1_A[2] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_LUT4_Z_1_B_LUT4_Z_C[0] +1 1 +.names sum[28] alu_output_LUT4_Z_1_B_LUT4_Z_C[1] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[0] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[6] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_LUT4_Z_1_C[0] +1 1 +.names sum[24] alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_LUT4_Z_1_C[1] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] alu_output_PFUMX_Z_9_C0[2] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] alu_output_LUT4_Z_A_L6MUX21_Z_SD[1] +1 1 +.names alu_in_2[2] alu_output_LUT4_Z_A_L6MUX21_Z_SD[3] +1 1 +.names alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[0] alu_output_LUT4_Z_4_C[0] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] alu_output_LUT4_Z_4_C[1] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] alu_output_PFUMX_Z_3_C0[2] +1 1 +.names alu_in_2[2] alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[3] +1 1 +.names alu_in_2[3] alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[4] +1 1 +.names alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_B_Z[1] +1 1 +.names alu_op_i[2] alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[0] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[3] +1 1 +.names alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B[0] alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[1] +1 1 +.names alu_in_2[2] alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[2] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_LUT4_Z_3_C[0] +1 1 +.names sum[20] alu_output_LUT4_Z_3_C[1] +1 1 +.names alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[2] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[2] +1 1 +.names alu_in_2[1] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] +1 1 +.names alu_in_2[2] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[4] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[5] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] alu_output_LUT4_Z_4_C_PFUMX_Z_C0[0] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_LUT4_Z_4_C_PFUMX_Z_C0[2] +1 1 +.names sum[19] alu_output_LUT4_Z_4_C_PFUMX_Z_C0[3] +1 1 +.names alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[2] alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[3] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[4] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[5] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z_LUT4_Z_1_C[0] +1 1 +.names sum[16] alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z_LUT4_Z_1_C[1] +1 1 +.names alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[2] alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[0] +1 1 +.names alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[1] +1 1 +.names alu_in_2[1] alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[4] +1 1 +.names alu_in_2[2] alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[5] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[6] +1 1 +.names alu_in_2[3] alu_output_LUT4_Z_1_B_LUT4_Z_1_A[4] +1 1 +.names alu_in_2[2] alu_output_LUT4_Z_1_B_LUT4_Z_1_A[5] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[0] alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[3] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_LUT4_Z_10_B_LUT4_Z_C[0] +1 1 +.names sum[8] alu_output_LUT4_Z_10_B_LUT4_Z_C[1] +1 1 +.names alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[0] alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z_LUT4_Z_1_A[1] +1 1 +.names alu_in_2[1] alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z_LUT4_Z_1_A[2] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z_LUT4_Z_1_A[3] +1 1 +.names alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[2] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_C[4] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[3] +1 1 +.names alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] alu_output_LUT4_Z_9_B_LUT4_Z_1_B[3] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_C[4] alu_output_LUT4_Z_9_B_LUT4_Z_1_B[4] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[4] alu_output_LUT4_Z_9_B_LUT4_Z_1_B[5] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[5] +1 1 +.names alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[6] +1 1 +.names alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] alu_output_LUT4_Z_A_LUT4_Z_1_C[0] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[3] alu_output_LUT4_Z_A_LUT4_Z_1_C[1] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] alu_output_LUT4_Z_A_LUT4_Z_1_C[2] +1 1 +.names alu_in_2[1] alu_output_LUT4_Z_A_LUT4_Z_1_C[5] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_LUT4_Z_A_LUT4_Z_1_C[6] +1 1 +.names alu_in_2[3] alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] +1 1 +.names alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[4] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[5] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] +1 1 +.names alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[2] +1 1 +.names alu_in_2[1] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[4] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[5] +1 1 +.names alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[0] +1 1 +.names alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[1] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_C[4] alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[4] +1 1 +.names alu_in_2[1] alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[5] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[6] +1 1 +.names sum[31] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B[1] +1 1 +.names sum[0] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B[2] +1 1 +.names alu_op_i[0] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B[3] +1 1 +.names alu_op_i[1] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B[4] +1 1 +.names alu_op_i[2] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B[1] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_C[0] +1 1 +.names sum[3] alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_C[1] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[0] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[1] +1 1 +.names alu_in_2[3] alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[4] +1 1 +.names alu_in_2[2] alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[5] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_LUT4_Z_9_B_LUT4_Z_C[0] +1 1 +.names sum[11] alu_output_LUT4_Z_9_B_LUT4_Z_C[1] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_PFUMX_Z_3_C0_LUT4_Z_C[0] +1 1 +.names sum[26] alu_output_PFUMX_Z_3_C0_LUT4_Z_C[1] +1 1 +.names alu_in_1[26] alu_output_LUT4_Z_7_A_LUT4_Z_A[2] +1 1 +.names alu_in_2[26] alu_output_LUT4_Z_7_A_LUT4_Z_A[3] +1 1 +.names alu_in_2[3] alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B[3] +1 1 +.names alu_in_2[2] alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B[4] +1 1 +.names alu_in_2[5] alu_output_LUT4_Z_5_B_LUT4_Z_A[3] +1 1 +.names alu_in_2[4] alu_output_LUT4_Z_5_B_LUT4_Z_A[4] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] alu_output_LUT4_Z_5_B_LUT4_Z_A[5] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_LUT4_Z_12_C_LUT4_Z_C[0] +1 1 +.names sum[2] alu_output_LUT4_Z_12_C_LUT4_Z_C[1] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] alu_output_LUT4_Z_12_C[0] +1 1 +.names alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[0] alu_output_LUT4_Z_12_C[1] +1 1 +.names alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B[2] alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z[0] +1 1 +.names alu_in_2[2] alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z[3] +1 1 +.names alu_in_2[3] alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z[4] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[2] +1 1 +.names alu_in_2[1] alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[4] +1 1 +.names alu_in_2[13] alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[0] +1 1 +.names alu_in_1[13] alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[1] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[3] +1 1 +.names sum[13] alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[4] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A[0] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[1] alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A[1] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A[2] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A[4] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_C[4] alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A[5] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] alu_output_LUT4_Z_8_A[1] +1 1 +.names alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D[1] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D[4] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_C[0] +1 1 +.names sum[1] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_C[1] +1 1 +.names alu_in_1[17] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_LUT4_Z_1_D[0] +1 1 +.names alu_in_2[17] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_LUT4_Z_1_D[1] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_LUT4_Z_1_D[2] +1 1 +.names alu_in_1[5] alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_BLUT_LUT4_Z_D[0] +1 1 +.names alu_in_1[6] alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_BLUT_LUT4_Z_D[1] +1 1 +.names alu_in_2[0] alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_BLUT_LUT4_Z_D[3] +1 1 +.names alu_in_2[1] alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_BLUT_LUT4_Z_D[4] +1 1 +.names alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A[0] alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A[1] +1 1 +.names alu_in_2[3] alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A[2] +1 1 +.names alu_in_2[2] alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A[3] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_LUT4_Z_11_C_LUT4_Z_C[0] +1 1 +.names sum[5] alu_output_LUT4_Z_11_C_LUT4_Z_C[1] +1 1 +.names alu_in_2[3] alu_output_LUT4_Z_8_A_LUT4_Z_1_C[2] +1 1 +.names alu_in_2[2] alu_output_LUT4_Z_8_A_LUT4_Z_1_C[3] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[0] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B[0] +1 1 +.names alu_in_2[3] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B[2] +1 1 +.names alu_in_2[2] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B[3] +1 1 +.names alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B[4] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[4] alu_output_LUT4_Z_5_B[1] +1 1 +.names alu_in_2[2] alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A[1] +1 1 +.names alu_in_2[3] alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A[3] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A[1] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A[4] +1 1 +.names alu_output_LUT4_Z_5_B_LUT4_Z_A[2] alu_output_LUT4_Z_5_B_LUT4_Z_C[0] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] alu_output_LUT4_Z_5_B_LUT4_Z_C[1] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] alu_output_LUT4_Z_11_C[0] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[0] alu_output_LUT4_Z_11_C[1] +1 1 +.names alu_in_2[3] alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[4] +1 1 +.names alu_in_2[2] alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[5] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A[2] +1 1 +.names alu_in_2[2] alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A[3] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_C[4] alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A[4] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[1] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[6] +1 1 +.names alu_in_1[3] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z_D[0] +1 1 +.names alu_in_1[4] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z_D[1] +1 1 +.names alu_in_2[0] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z_D[3] +1 1 +.names alu_in_2[1] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z_D[4] +1 1 +.names alu_in_2[2] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[3] +1 1 +.names alu_in_2[3] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[4] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z[3] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[0] +1 1 +.names sum[4] alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[1] +1 1 +.names alu_in_2[18] alu_output_LUT4_Z_5_B_LUT4_Z_C_LUT4_Z_1_B[1] +1 1 +.names alu_output_LUT4_Z_7_A_LUT4_Z_A[1] alu_output_LUT4_Z_5_B_LUT4_Z_C_LUT4_Z_1_B[2] +1 1 +.names alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[1] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[2] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_PFUMX_Z_10_C0_LUT4_Z_C[0] +1 1 +.names sum[10] alu_output_PFUMX_Z_10_C0_LUT4_Z_C[1] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] alu_output_LUT4_Z_3_C_LUT4_Z_A[1] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] alu_output_LUT4_Z_3_C_LUT4_Z_A[4] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[2] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_C[4] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[3] +1 1 +.names alu_in_1[31] alu_output_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z_D[0] +1 1 +.names alu_in_2[31] alu_output_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z_D[1] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] alu_output_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z_D[2] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] alu_output_PFUMX_Z_C0_PFUMX_Z_C0[0] +1 1 +.names alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[1] alu_output_PFUMX_Z_C0_PFUMX_Z_C0[1] +1 1 +.names alu_in_2[3] alu_output_PFUMX_Z_C0_PFUMX_Z_C0[2] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] alu_output_PFUMX_Z_2_C0[3] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_C[4] alu_output_LUT4_Z_9_B_LUT4_Z_1_C[0] +1 1 +.names alu_output_LUT4_Z_9_B_LUT4_Z_1_B[0] alu_output_LUT4_Z_9_B_LUT4_Z_1_C[1] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[5] alu_output_LUT4_Z_9_B_LUT4_Z_1_C[3] +1 1 +.names alu_in_2[16] complement2_LUT4_C_D[0] +1 1 +.names complement2[16] complement2_LUT4_C_D[1] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[3] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[0] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[1] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_C[3] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[2] +1 1 +.names alu_in_2[1] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[4] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[5] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[0] +1 1 +.names alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[1] +1 1 +.names alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[2] +1 1 +.names alu_in_2[1] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[4] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[5] +1 1 +.names alu_output_PFUMX_Z_C0_LUT4_Z_1_A[1] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B[0] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B[2] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B[3] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] alu_output_PFUMX_Z_2_C0_LUT4_Z_B[1] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_C[0] +1 1 +.names sum[7] alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_C[1] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_C[4] alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z[0] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_PFUMX_Z_C0_LUT4_Z_1_A[2] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[1] alu_output_PFUMX_Z_C0_LUT4_Z_A[0] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] alu_output_PFUMX_Z_C0_LUT4_Z_A[2] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[2] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[0] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[1] +1 1 +.names alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[2] +1 1 +.names alu_in_2[1] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[5] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[6] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A[1] +1 1 +.names alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[3] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A[2] +1 1 +.names alu_in_2[1] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A[3] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A[4] +1 1 +.names alu_in_1[30] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_B[0] +1 1 +.names alu_in_1[31] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_B[1] +1 1 +.names alu_in_2[0] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_B[3] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_B[4] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_B[5] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_B[6] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] alu_output_PFUMX_Z_C0_LUT4_Z_2_B[2] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] alu_output_PFUMX_Z_C0[3] +1 1 +.names alu_in_1[30] alu_output_PFUMX_Z_1_C0_LUT4_Z_C_LUT4_Z_D[0] +1 1 +.names alu_in_2[30] alu_output_PFUMX_Z_1_C0_LUT4_Z_C_LUT4_Z_D[1] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] alu_output_PFUMX_Z_1_C0_LUT4_Z_C_LUT4_Z_D[2] +1 1 +.names alu_output_PFUMX_Z_1_C0_LUT4_Z_A[0] alu_output_PFUMX_Z_1_C0_LUT4_Z_C[0] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] alu_output_PFUMX_Z_1_C0_LUT4_Z_C[1] +1 1 +.names alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[3] alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_B[0] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_B[2] +1 1 +.names alu_in_2[1] alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_B[3] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_B[4] +1 1 +.names alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[1] alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C[0] +1 1 +.names alu_in_2[2] alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C[1] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C[3] +1 1 +.names alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[0] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[2] +1 1 +.names alu_in_2[3] alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[3] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] alu_output_PFUMX_Z_1_C0[3] +1 1 +.names alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[0] alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B[1] +1 1 +.names alu_in_2[2] alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B[2] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_C[4] alu_output_PFUMX_Z_C0_LUT4_Z_B[1] +1 1 +.names alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] alu_output_PFUMX_Z_C0_LUT4_Z_B[2] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_C[3] alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[0] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[2] +1 1 +.names alu_in_2[1] alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[4] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[5] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_LUT4_Z_8_A_LUT4_Z_C[0] +1 1 +.names sum[12] alu_output_LUT4_Z_8_A_LUT4_Z_C[1] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_C[4] alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z[0] +1 1 +.names alu_in_2[31] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[0] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[2] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[1] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[1] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[3] +1 1 +.names alu_in_2[1] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[4] +1 1 +.names alu_in_2[2] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[5] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[6] +1 1 +.names alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[0] alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A[1] +1 1 +.names alu_in_2[2] alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A[2] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] alu_output_PFUMX_Z_9_C0_LUT4_Z_A[2] +1 1 +.names alu_in_2[3] alu_output_PFUMX_Z_9_C0_LUT4_Z_A[3] +1 1 +.names $true alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[0] +1 1 +.names alu_in_2[2] alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[2] +1 1 +.names $false complement2_CCU2C_S0_COUT[0] +1 1 +.names complement2_CCU2C_S0_B0[0] complement2_CCU2C_S0_COUT[1] +1 1 +.names complement2_CCU2C_S0_B0[0] complement2_CCU2C_S0_3_COUT[0] +1 1 +.names complement2_CCU2C_S0_COUT[2] complement2_CCU2C_S0_3_COUT[1] +1 1 +.names complement2_CCU2C_S0_COUT[3] complement2_CCU2C_S0_3_COUT[2] +1 1 +.names complement2_CCU2C_S0_COUT[4] complement2_CCU2C_S0_3_COUT[3] +1 1 +.names complement2_CCU2C_S0_COUT[5] complement2_CCU2C_S0_3_COUT[4] +1 1 +.names complement2_CCU2C_S0_COUT[6] complement2_CCU2C_S0_3_COUT[5] +1 1 +.names complement2_CCU2C_S0_COUT[7] complement2_CCU2C_S0_3_COUT[6] +1 1 +.names complement2_CCU2C_S0_COUT[8] complement2_CCU2C_S0_3_COUT[7] +1 1 +.names complement2_CCU2C_S0_COUT[9] complement2_CCU2C_S0_3_COUT[8] +1 1 +.names complement2_CCU2C_S0_COUT[10] complement2_CCU2C_S0_3_COUT[9] +1 1 +.names complement2_CCU2C_S0_COUT[11] complement2_CCU2C_S0_3_COUT[10] +1 1 +.names complement2_CCU2C_S0_COUT[12] complement2_CCU2C_S0_3_COUT[11] +1 1 +.names complement2_CCU2C_S0_COUT[13] complement2_CCU2C_S0_3_COUT[12] +1 1 +.names complement2_CCU2C_S0_COUT[14] complement2_CCU2C_S0_3_COUT[13] +1 1 +.names complement2_CCU2C_S0_COUT[15] complement2_CCU2C_S0_3_COUT[14] +1 1 +.names complement2_CCU2C_S0_COUT[16] complement2_CCU2C_S0_3_COUT[15] +1 1 +.names complement2_CCU2C_S0_COUT[17] complement2_CCU2C_S0_3_COUT[16] +1 1 +.names complement2_CCU2C_S0_COUT[18] complement2_CCU2C_S0_3_COUT[17] +1 1 +.names complement2_CCU2C_S0_COUT[19] complement2_CCU2C_S0_3_COUT[18] +1 1 +.names complement2_CCU2C_S0_COUT[20] complement2_CCU2C_S0_3_COUT[19] +1 1 +.names complement2_CCU2C_S0_COUT[21] complement2_CCU2C_S0_3_COUT[20] +1 1 +.names complement2_CCU2C_S0_COUT[22] complement2_CCU2C_S0_3_COUT[21] +1 1 +.names complement2_CCU2C_S0_COUT[23] complement2_CCU2C_S0_3_COUT[22] +1 1 +.names complement2_CCU2C_S0_COUT[24] complement2_CCU2C_S0_3_COUT[23] +1 1 +.names complement2_CCU2C_S0_COUT[25] complement2_CCU2C_S0_3_COUT[24] +1 1 +.names complement2_CCU2C_S0_COUT[26] complement2_CCU2C_S0_3_COUT[25] +1 1 +.names complement2_CCU2C_S0_COUT[27] complement2_CCU2C_S0_3_COUT[26] +1 1 +.names complement2_CCU2C_S0_COUT[28] complement2_CCU2C_S0_3_COUT[27] +1 1 +.names complement2_CCU2C_S0_COUT[29] complement2_CCU2C_S0_3_COUT[28] +1 1 +.names complement2_CCU2C_S0_COUT[30] complement2_CCU2C_S0_3_COUT[29] +1 1 +.names complement2_CCU2C_S0_COUT[31] complement2_CCU2C_S0_3_COUT[30] +1 1 +.names $false sum_CCU2C_S0_COUT[0] +1 1 +.names sum_CCU2C_S0_COUT[1] sum_CCU2C_S0_3_COUT[0] +1 1 +.names sum_CCU2C_S0_COUT[2] sum_CCU2C_S0_3_COUT[1] +1 1 +.names sum_CCU2C_S0_COUT[3] sum_CCU2C_S0_3_COUT[2] +1 1 +.names sum_CCU2C_S0_COUT[4] sum_CCU2C_S0_3_COUT[3] +1 1 +.names sum_CCU2C_S0_COUT[5] sum_CCU2C_S0_3_COUT[4] +1 1 +.names sum_CCU2C_S0_COUT[6] sum_CCU2C_S0_3_COUT[5] +1 1 +.names sum_CCU2C_S0_COUT[7] sum_CCU2C_S0_3_COUT[6] +1 1 +.names sum_CCU2C_S0_COUT[8] sum_CCU2C_S0_3_COUT[7] +1 1 +.names sum_CCU2C_S0_COUT[9] sum_CCU2C_S0_3_COUT[8] +1 1 +.names sum_CCU2C_S0_COUT[10] sum_CCU2C_S0_3_COUT[9] +1 1 +.names sum_CCU2C_S0_COUT[11] sum_CCU2C_S0_3_COUT[10] +1 1 +.names sum_CCU2C_S0_COUT[12] sum_CCU2C_S0_3_COUT[11] +1 1 +.names sum_CCU2C_S0_COUT[13] sum_CCU2C_S0_3_COUT[12] +1 1 +.names sum_CCU2C_S0_COUT[14] sum_CCU2C_S0_3_COUT[13] +1 1 +.names sum_CCU2C_S0_COUT[15] sum_CCU2C_S0_3_COUT[14] +1 1 +.names sum_CCU2C_S0_COUT[16] sum_CCU2C_S0_3_COUT[15] +1 1 +.names sum_CCU2C_S0_COUT[17] sum_CCU2C_S0_3_COUT[16] +1 1 +.names sum_CCU2C_S0_COUT[18] sum_CCU2C_S0_3_COUT[17] +1 1 +.names sum_CCU2C_S0_COUT[19] sum_CCU2C_S0_3_COUT[18] +1 1 +.names sum_CCU2C_S0_COUT[20] sum_CCU2C_S0_3_COUT[19] +1 1 +.names sum_CCU2C_S0_COUT[21] sum_CCU2C_S0_3_COUT[20] +1 1 +.names sum_CCU2C_S0_COUT[22] sum_CCU2C_S0_3_COUT[21] +1 1 +.names sum_CCU2C_S0_COUT[23] sum_CCU2C_S0_3_COUT[22] +1 1 +.names sum_CCU2C_S0_COUT[24] sum_CCU2C_S0_3_COUT[23] +1 1 +.names sum_CCU2C_S0_COUT[25] sum_CCU2C_S0_3_COUT[24] +1 1 +.names sum_CCU2C_S0_COUT[26] sum_CCU2C_S0_3_COUT[25] +1 1 +.names sum_CCU2C_S0_COUT[27] sum_CCU2C_S0_3_COUT[26] +1 1 +.names sum_CCU2C_S0_COUT[28] sum_CCU2C_S0_3_COUT[27] +1 1 +.names sum_CCU2C_S0_COUT[29] sum_CCU2C_S0_3_COUT[28] +1 1 +.names sum_CCU2C_S0_COUT[30] sum_CCU2C_S0_3_COUT[29] +1 1 +.names sum_CCU2C_S0_COUT[31] sum_CCU2C_S0_3_COUT[30] +1 1 +.end diff --git a/verilog/alu/v6/alu6.v b/verilog/alu/v6/alu6.v new file mode 100644 index 0000000..2f0f00c --- /dev/null +++ b/verilog/alu/v6/alu6.v @@ -0,0 +1,30 @@ +`default_nettype none +`timescale 1us/1ns + +`include "aluOp.vh" + +module alu6 +( +input wire [31:0] alu_in_1, +input wire[31:0] alu_in_2, +input wire[3:0] alu_op_i, +output wire[31:0] alu_output +); + +wire [31:0] complement2 = ~alu_in_2 + 1'b1; +wire [31:0] sum = alu_in_1 + (alu_op_i[3] | (alu_op_i[1] & ~alu_op_i[0]) == 1'b1 ? complement2 : alu_in_2); +wire [31:0] right = alu_in_1 >> alu_in_2[5:0] | (alu_op_i[3] == 0 ? 32'b0 : + (32'hFFFFFFFF << (alu_in_2[31] == 1'b1 ? 5'b0 : {~alu_in_2[4] , ~alu_in_2[3], ~alu_in_2[2], ~alu_in_2[1], ~alu_in_2[0]}))); + +assign alu_output = + alu_op_i[2:0] == `ADDSUB ? sum : + alu_op_i[2:0] == `XOR ? alu_in_1 ^ alu_in_2 : + alu_op_i[2:0] == `OR ? alu_in_1 | alu_in_2 : + alu_op_i[2:0] == `AND ? alu_in_1 & alu_in_2 : + alu_op_i[2:0] == `SLL ? alu_in_2[6] == 1 ? 32'b0 : alu_in_1 << alu_in_2[5:0] : + alu_op_i[2:0] == `SR ? right : + alu_op_i[2:0] == `SLT ? {31'b0, sum[31]} : + alu_op_i[2:0] == `SLTU ? (alu_in_1 < alu_in_2 ? 32'b1 : 32'b0) : + 32'b0; +endmodule + diff --git a/verilog/alu/v6/aluOp.h b/verilog/alu/v6/aluOp.h new file mode 100644 index 0000000..999dac2 --- /dev/null +++ b/verilog/alu/v6/aluOp.h @@ -0,0 +1,16 @@ +#ifndef ALU_OP +#define ALU_OP + +#define ADD 0 +#define SUB 8 +#define XOR 4 +#define OR 6 +#define AND 7 +#define SLL 1 +#define SRL 5 +#define SRA 13 +#define SLT 2 +#define SLTU 3 +#define NONE 15 + +#endif diff --git a/verilog/alu/v6/aluOp.vh b/verilog/alu/v6/aluOp.vh new file mode 100644 index 0000000..0e8c41a --- /dev/null +++ b/verilog/alu/v6/aluOp.vh @@ -0,0 +1,14 @@ +`ifndef ALU_OP +`define ALU_OP +// 1st bit that is no longer there == SUB/SRA/NONE +`define ADDSUB 3'b000 +`define XOR 3'b100 +`define OR 3'b110 +`define AND 3'b111 +`define SLL 3'b001 +`define SR 3'b101 +`define SLT 3'b010 +`define SLTU 3'b011 +`define NONE 3'b111 + +`endif diff --git a/verilog/alu/v6/crab.pcf b/verilog/alu/v6/crab.pcf new file mode 100644 index 0000000..c0d91c5 --- /dev/null +++ b/verilog/alu/v6/crab.pcf @@ -0,0 +1,254 @@ +LOCATE COMP "clk48" SITE "A9"; +IOBUF PORT "clk48" IO_TYPE=LVCMOS33; +FREQUENCY PORT "clk48" 48.0 MHz; + +LOCATE COMP "ddram_a[0]" SITE "C4"; +IOBUF PORT "ddram_a[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[0]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[1]" SITE "D2"; +IOBUF PORT "ddram_a[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[1]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[2]" SITE "D3"; +IOBUF PORT "ddram_a[2]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[2]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[3]" SITE "A3"; +IOBUF PORT "ddram_a[3]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[3]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[4]" SITE "A4"; +IOBUF PORT "ddram_a[4]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[4]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[5]" SITE "D4"; +IOBUF PORT "ddram_a[5]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[5]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[6]" SITE "C3"; +IOBUF PORT "ddram_a[6]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[6]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[7]" SITE "B2"; +IOBUF PORT "ddram_a[7]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[7]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[8]" SITE "B1"; +IOBUF PORT "ddram_a[8]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[8]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[9]" SITE "D1"; +IOBUF PORT "ddram_a[9]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[9]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[10]" SITE "A7"; +IOBUF PORT "ddram_a[10]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[10]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[11]" SITE "C2"; +IOBUF PORT "ddram_a[11]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[11]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[12]" SITE "B6"; +IOBUF PORT "ddram_a[12]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[12]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[13]" SITE "C1"; +IOBUF PORT "ddram_a[13]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[13]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[14]" SITE "A2"; +IOBUF PORT "ddram_a[14]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[14]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_a[15]" SITE "C7"; +IOBUF PORT "ddram_a[15]" SLEWRATE=FAST; +IOBUF PORT "ddram_a[15]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_ba[0]" SITE "D6"; +IOBUF PORT "ddram_ba[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_ba[0]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_ba[1]" SITE "B7"; +IOBUF PORT "ddram_ba[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_ba[1]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_ba[2]" SITE "A6"; +IOBUF PORT "ddram_ba[2]" SLEWRATE=FAST; +IOBUF PORT "ddram_ba[2]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_ras_n" SITE "C12"; +IOBUF PORT "ddram_ras_n" SLEWRATE=FAST; +IOBUF PORT "ddram_ras_n" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_cas_n" SITE "D13"; +IOBUF PORT "ddram_cas_n" SLEWRATE=FAST; +IOBUF PORT "ddram_cas_n" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_we_n" SITE "B12"; +IOBUF PORT "ddram_we_n" SLEWRATE=FAST; +IOBUF PORT "ddram_we_n" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_cs_n" SITE "A12"; +IOBUF PORT "ddram_cs_n" SLEWRATE=FAST; +IOBUF PORT "ddram_cs_n" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_dm[0]" SITE "D16"; +IOBUF PORT "ddram_dm[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_dm[0]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_dm[1]" SITE "G16"; +IOBUF PORT "ddram_dm[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_dm[1]" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_dq[0]" SITE "C17"; +IOBUF PORT "ddram_dq[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[0]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[0]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[1]" SITE "D15"; +IOBUF PORT "ddram_dq[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[1]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[1]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[2]" SITE "B17"; +IOBUF PORT "ddram_dq[2]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[2]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[2]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[3]" SITE "C16"; +IOBUF PORT "ddram_dq[3]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[3]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[3]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[4]" SITE "A15"; +IOBUF PORT "ddram_dq[4]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[4]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[4]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[5]" SITE "B13"; +IOBUF PORT "ddram_dq[5]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[5]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[5]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[6]" SITE "A17"; +IOBUF PORT "ddram_dq[6]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[6]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[6]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[7]" SITE "A13"; +IOBUF PORT "ddram_dq[7]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[7]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[7]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[8]" SITE "F17"; +IOBUF PORT "ddram_dq[8]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[8]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[8]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[9]" SITE "F16"; +IOBUF PORT "ddram_dq[9]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[9]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[9]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[10]" SITE "G15"; +IOBUF PORT "ddram_dq[10]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[10]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[10]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[11]" SITE "F15"; +IOBUF PORT "ddram_dq[11]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[11]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[11]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[12]" SITE "J16"; +IOBUF PORT "ddram_dq[12]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[12]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[12]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[13]" SITE "C18"; +IOBUF PORT "ddram_dq[13]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[13]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[13]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[14]" SITE "H16"; +IOBUF PORT "ddram_dq[14]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[14]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[14]" TERMINATION=OFF; +LOCATE COMP "ddram_dq[15]" SITE "F18"; +IOBUF PORT "ddram_dq[15]" SLEWRATE=FAST; +IOBUF PORT "ddram_dq[15]" IO_TYPE=SSTL135_I; +IOBUF PORT "ddram_dq[15]" TERMINATION=OFF; +LOCATE COMP "ddram_dqs_p[0]" SITE "B15"; +IOBUF PORT "ddram_dqs_p[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_dqs_p[0]" IO_TYPE=SSTL135D_I; +IOBUF PORT "ddram_dqs_p[0]" TERMINATION=OFF; +IOBUF PORT "ddram_dqs_p[0]" DIFFRESISTOR=100; +LOCATE COMP "ddram_dqs_p[1]" SITE "G18"; +IOBUF PORT "ddram_dqs_p[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_dqs_p[1]" IO_TYPE=SSTL135D_I; +IOBUF PORT "ddram_dqs_p[1]" TERMINATION=OFF; +IOBUF PORT "ddram_dqs_p[1]" DIFFRESISTOR=100; +LOCATE COMP "ddram_clk_p" SITE "J18"; +IOBUF PORT "ddram_clk_p" SLEWRATE=FAST; +IOBUF PORT "ddram_clk_p" IO_TYPE=SSTL135D_I; +LOCATE COMP "ddram_cke" SITE "D18"; +IOBUF PORT "ddram_cke" SLEWRATE=FAST; +IOBUF PORT "ddram_cke" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_odt" SITE "C13"; +IOBUF PORT "ddram_odt" SLEWRATE=FAST; +IOBUF PORT "ddram_odt" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_reset_n" SITE "L18"; +IOBUF PORT "ddram_reset_n" SLEWRATE=FAST; +IOBUF PORT "ddram_reset_n" IO_TYPE=SSTL135_I; +LOCATE COMP "ddram_vccio[0]" SITE "K16"; +IOBUF PORT "ddram_vccio[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[0]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_vccio[1]" SITE "D17"; +IOBUF PORT "ddram_vccio[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[1]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_vccio[2]" SITE "K15"; +IOBUF PORT "ddram_vccio[2]" SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[2]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_vccio[3]" SITE "K17"; +IOBUF PORT "ddram_vccio[3]" SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[3]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_vccio[4]" SITE "B18"; +IOBUF PORT "ddram_vccio[4]" SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[4]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_vccio[5]" SITE "C6"; +IOBUF PORT "ddram_vccio[5]" SLEWRATE=FAST; +IOBUF PORT "ddram_vccio[5]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_gnd[0]" SITE "L15"; +IOBUF PORT "ddram_gnd[0]" SLEWRATE=FAST; +IOBUF PORT "ddram_gnd[0]" IO_TYPE=SSTL135_II; +LOCATE COMP "ddram_gnd[1]" SITE "L16"; +IOBUF PORT "ddram_gnd[1]" SLEWRATE=FAST; +IOBUF PORT "ddram_gnd[1]" IO_TYPE=SSTL135_II; +LOCATE COMP "rgb_led0_r" SITE "K4"; +IOBUF PORT "rgb_led0_r" IO_TYPE=LVCMOS33; +LOCATE COMP "rgb_led0_g" SITE "M3"; +IOBUF PORT "rgb_led0_g" IO_TYPE=LVCMOS33; +LOCATE COMP "rgb_led0_b" SITE "J3"; +IOBUF PORT "rgb_led0_b" IO_TYPE=LVCMOS33; +LOCATE COMP "gpio_0" SITE "N17"; +IOBUF PORT "gpio_0" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_0" PULLMODE=DOWN; +LOCATE COMP "gpio_1" SITE "M18"; +IOBUF PORT "gpio_1" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_1" PULLMODE=DOWN; +LOCATE COMP "gpio_5" SITE "B10"; +IOBUF PORT "gpio_5" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_5" PULLMODE=DOWN; +LOCATE COMP "gpio_6" SITE "B9"; +IOBUF PORT "gpio_6" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_6" PULLMODE=DOWN; +LOCATE COMP "gpio_9" SITE "C8"; +IOBUF PORT "gpio_9" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_9" PULLMODE=DOWN; +LOCATE COMP "gpio_10" SITE "B8"; +IOBUF PORT "gpio_10" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_10" PULLMODE=DOWN; +LOCATE COMP "gpio_11" SITE "A8"; +IOBUF PORT "gpio_11" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_11" PULLMODE=DOWN; +LOCATE COMP "gpio_12" SITE "H2"; +IOBUF PORT "gpio_12" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_12" PULLMODE=DOWN; +LOCATE COMP "gpio_13" SITE "J2"; +IOBUF PORT "gpio_13" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_13" PULLMODE=DOWN; +LOCATE COMP "gpio_a0" SITE "L4"; +IOBUF PORT "gpio_a0" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_a0" PULLMODE=DOWN; +LOCATE COMP "gpio_a1" SITE "N3"; +IOBUF PORT "gpio_a1" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_a1" PULLMODE=DOWN; +LOCATE COMP "gpio_a2" SITE "N4"; +IOBUF PORT "gpio_a2" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_a2" PULLMODE=DOWN; +LOCATE COMP "gpio_a3" SITE "H4"; +IOBUF PORT "gpio_a3" IO_TYPE=LVCMOS33; +IOBUF PORT "gpio_a3" PULLMODE=DOWN; +LOCATE COMP "usr_btn" SITE "J17"; +IOBUF PORT "usr_btn" IO_TYPE=SSTL135_I; +LOCATE COMP "rst_n" SITE "V17"; +IOBUF PORT "rst_n" IO_TYPE=LVCMOS33; +LOCATE COMP "spiflash4x_cs_n" SITE "U17"; +IOBUF PORT "spiflash4x_cs_n" IO_TYPE=LVCMOS33; +LOCATE COMP "spiflash4x_dq[0]" SITE "U18"; +IOBUF PORT "spiflash4x_dq[0]" IO_TYPE=LVCMOS33; +LOCATE COMP "spiflash4x_dq[1]" SITE "T18"; +IOBUF PORT "spiflash4x_dq[1]" IO_TYPE=LVCMOS33; +LOCATE COMP "spiflash4x_dq[2]" SITE "R18"; +IOBUF PORT "spiflash4x_dq[2]" IO_TYPE=LVCMOS33; +LOCATE COMP "spiflash4x_dq[3]" SITE "N18"; +IOBUF PORT "spiflash4x_dq[3]" IO_TYPE=LVCMOS33; +LOCATE COMP "usb_d_p" SITE "N1"; +IOBUF PORT "usb_d_p" IO_TYPE=LVCMOS33; +LOCATE COMP "usb_d_n" SITE "M2"; +IOBUF PORT "usb_d_n" IO_TYPE=LVCMOS33; +LOCATE COMP "usb_pullup" SITE "N2"; +IOBUF PORT "usb_pullup" IO_TYPE=LVCMOS33; diff --git a/verilog/alu/v6/obj_dir/Valu6 b/verilog/alu/v6/obj_dir/Valu6 Binary files differnew file mode 100755 index 0000000..1614e40 --- /dev/null +++ b/verilog/alu/v6/obj_dir/Valu6 diff --git a/verilog/alu/v6/obj_dir/Valu6.cpp b/verilog/alu/v6/obj_dir/Valu6.cpp new file mode 100644 index 0000000..2e02259 --- /dev/null +++ b/verilog/alu/v6/obj_dir/Valu6.cpp @@ -0,0 +1,207 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design implementation internals +// See Valu6.h for the primary calling header + +#include "Valu6.h" +#include "Valu6__Syms.h" + +//========== + +void Valu6::eval_step() { + VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate Valu6::eval\n"); ); + Valu6__Syms* __restrict vlSymsp = this->__VlSymsp; // Setup global symbol table + Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; +#ifdef VL_DEBUG + // Debug assertions + _eval_debug_assertions(); +#endif // VL_DEBUG + // Initialize + if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp); + // Evaluate till stable + int __VclockLoop = 0; + QData __Vchange = 1; + do { + VL_DEBUG_IF(VL_DBG_MSGF("+ Clock loop\n");); + vlSymsp->__Vm_activity = true; + _eval(vlSymsp); + if (VL_UNLIKELY(++__VclockLoop > 100)) { + // About to fail, so enable debug to see what's not settling. + // Note you must run make with OPT=-DVL_DEBUG for debug prints. + int __Vsaved_debug = Verilated::debug(); + Verilated::debug(1); + __Vchange = _change_request(vlSymsp); + Verilated::debug(__Vsaved_debug); + VL_FATAL_MT("alu6.v", 6, "", + "Verilated model didn't converge\n" + "- See DIDNOTCONVERGE in the Verilator manual"); + } else { + __Vchange = _change_request(vlSymsp); + } + } while (VL_UNLIKELY(__Vchange)); +} + +void Valu6::_eval_initial_loop(Valu6__Syms* __restrict vlSymsp) { + vlSymsp->__Vm_didInit = true; + _eval_initial(vlSymsp); + vlSymsp->__Vm_activity = true; + // Evaluate till stable + int __VclockLoop = 0; + QData __Vchange = 1; + do { + _eval_settle(vlSymsp); + _eval(vlSymsp); + if (VL_UNLIKELY(++__VclockLoop > 100)) { + // About to fail, so enable debug to see what's not settling. + // Note you must run make with OPT=-DVL_DEBUG for debug prints. + int __Vsaved_debug = Verilated::debug(); + Verilated::debug(1); + __Vchange = _change_request(vlSymsp); + Verilated::debug(__Vsaved_debug); + VL_FATAL_MT("alu6.v", 6, "", + "Verilated model didn't DC converge\n" + "- See DIDNOTCONVERGE in the Verilator manual"); + } else { + __Vchange = _change_request(vlSymsp); + } + } while (VL_UNLIKELY(__Vchange)); +} + +VL_INLINE_OPT void Valu6::_combo__TOP__1(Valu6__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6::_combo__TOP__1\n"); ); + Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->alu6__DOT__sum = (vlTOPp->alu_in_1 + ((1U + & (((IData)(vlTOPp->alu_op_i) + >> 3U) + | (((IData)(vlTOPp->alu_op_i) + >> 1U) + & (~ (IData)(vlTOPp->alu_op_i))))) + ? + ((IData)(1U) + + + (~ vlTOPp->alu_in_2)) + : vlTOPp->alu_in_2)); + vlTOPp->alu_output = ((0U == (7U & (IData)(vlTOPp->alu_op_i))) + ? vlTOPp->alu6__DOT__sum + : ((4U == (7U & (IData)(vlTOPp->alu_op_i))) + ? (vlTOPp->alu_in_1 + ^ vlTOPp->alu_in_2) + : ((6U == (7U & (IData)(vlTOPp->alu_op_i))) + ? (vlTOPp->alu_in_1 + | vlTOPp->alu_in_2) + : ((7U == (7U & (IData)(vlTOPp->alu_op_i))) + ? (vlTOPp->alu_in_1 + & vlTOPp->alu_in_2) + : ((1U == (7U + & (IData)(vlTOPp->alu_op_i))) + ? ((0x40U + & vlTOPp->alu_in_2) + ? 0U + : ((0x1fU + >= + (0x3fU + & vlTOPp->alu_in_2)) + ? + (vlTOPp->alu_in_1 + << + (0x3fU + & vlTOPp->alu_in_2)) + : 0U)) + : ((5U == + (7U + & (IData)(vlTOPp->alu_op_i))) + ? (( + (0x1fU + >= + (0x3fU + & vlTOPp->alu_in_2)) + ? + (vlTOPp->alu_in_1 + >> + (0x3fU + & vlTOPp->alu_in_2)) + : 0U) + | ((8U + & (IData)(vlTOPp->alu_op_i)) + ? + ((IData)(0xffffffffU) + << + ((0x80000000U + & vlTOPp->alu_in_2) + ? 0U + : + ((0x10U + & ((~ + (vlTOPp->alu_in_2 + >> 4U)) + << 4U)) + | ((8U + & ((~ + (vlTOPp->alu_in_2 + >> 3U)) + << 3U)) + | ((4U + & ((~ + (vlTOPp->alu_in_2 + >> 2U)) + << 2U)) + | ((2U + & ((~ + (vlTOPp->alu_in_2 + >> 1U)) + << 1U)) + | (1U + & (~ vlTOPp->alu_in_2)))))))) + : 0U)) + : ((2U + == + (7U + & (IData)(vlTOPp->alu_op_i))) + ? + (1U + & (vlTOPp->alu6__DOT__sum + >> 0x1fU)) + : + ((3U + == + (7U + & (IData)(vlTOPp->alu_op_i))) + ? + ((vlTOPp->alu_in_1 + < vlTOPp->alu_in_2) + ? 1U + : 0U) + : 0U)))))))); +} + +void Valu6::_eval(Valu6__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6::_eval\n"); ); + Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->_combo__TOP__1(vlSymsp); +} + +VL_INLINE_OPT QData Valu6::_change_request(Valu6__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6::_change_request\n"); ); + Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + return (vlTOPp->_change_request_1(vlSymsp)); +} + +VL_INLINE_OPT QData Valu6::_change_request_1(Valu6__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6::_change_request_1\n"); ); + Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + // Change detection + QData __req = false; // Logically a bool + return __req; +} + +#ifdef VL_DEBUG +void Valu6::_eval_debug_assertions() { + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6::_eval_debug_assertions\n"); ); + // Body + if (VL_UNLIKELY((alu_op_i & 0xf0U))) { + Verilated::overWidthError("alu_op_i");} +} +#endif // VL_DEBUG diff --git a/verilog/alu/v6/obj_dir/Valu6.h b/verilog/alu/v6/obj_dir/Valu6.h new file mode 100644 index 0000000..9cddec9 --- /dev/null +++ b/verilog/alu/v6/obj_dir/Valu6.h @@ -0,0 +1,102 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Primary design header +// +// This header should be included by all source files instantiating the design. +// The class here is then constructed to instantiate the design. +// See the Verilator manual for examples. + +#ifndef _VALU6_H_ +#define _VALU6_H_ // guard + +#include "verilated_heavy.h" + +//========== + +class Valu6__Syms; +class Valu6_VerilatedVcd; + + +//---------- + +VL_MODULE(Valu6) { + public: + + // PORTS + // The application code writes and reads these signals to + // propagate new values into/out from the Verilated model. + VL_IN8(alu_op_i,3,0); + VL_IN(alu_in_1,31,0); + VL_IN(alu_in_2,31,0); + VL_OUT(alu_output,31,0); + + // LOCAL SIGNALS + // Internals; generally not touched by application code + IData/*31:0*/ alu6__DOT__sum; + + // LOCAL VARIABLES + // Internals; generally not touched by application code + CData/*0:0*/ __Vm_traceActivity[1]; + + // INTERNAL VARIABLES + // Internals; generally not touched by application code + Valu6__Syms* __VlSymsp; // Symbol table + + // CONSTRUCTORS + private: + VL_UNCOPYABLE(Valu6); ///< Copying not allowed + public: + /// Construct the model; called by application code + /// The special name may be used to make a wrapper with a + /// single model invisible with respect to DPI scope names. + Valu6(const char* name = "TOP"); + /// Destroy the model; called (often implicitly) by application code + ~Valu6(); + /// Trace signals in the model; called by application code + void trace(VerilatedVcdC* tfp, int levels, int options = 0); + + // API METHODS + /// Evaluate the model. Application must call when inputs change. + void eval() { eval_step(); } + /// Evaluate when calling multiple units/models per time step. + void eval_step(); + /// Evaluate at end of a timestep for tracing, when using eval_step(). + /// Application must call after all eval() and before time changes. + void eval_end_step() {} + /// Simulation complete, run final blocks. Application must call on completion. + void final(); + + // INTERNAL METHODS + static void _eval_initial_loop(Valu6__Syms* __restrict vlSymsp); + void __Vconfigure(Valu6__Syms* symsp, bool first); + private: + static QData _change_request(Valu6__Syms* __restrict vlSymsp); + static QData _change_request_1(Valu6__Syms* __restrict vlSymsp); + public: + static void _combo__TOP__1(Valu6__Syms* __restrict vlSymsp); + private: + void _ctor_var_reset() VL_ATTR_COLD; + public: + static void _eval(Valu6__Syms* __restrict vlSymsp); + private: +#ifdef VL_DEBUG + void _eval_debug_assertions(); +#endif // VL_DEBUG + public: + static void _eval_initial(Valu6__Syms* __restrict vlSymsp) VL_ATTR_COLD; + static void _eval_settle(Valu6__Syms* __restrict vlSymsp) VL_ATTR_COLD; + private: + static void traceChgSub0(void* userp, VerilatedVcd* tracep); + static void traceChgTop0(void* userp, VerilatedVcd* tracep); + static void traceCleanup(void* userp, VerilatedVcd* /*unused*/); + static void traceFullSub0(void* userp, VerilatedVcd* tracep) VL_ATTR_COLD; + static void traceFullTop0(void* userp, VerilatedVcd* tracep) VL_ATTR_COLD; + static void traceInitSub0(void* userp, VerilatedVcd* tracep) VL_ATTR_COLD; + static void traceInitTop(void* userp, VerilatedVcd* tracep) VL_ATTR_COLD; + void traceRegister(VerilatedVcd* tracep) VL_ATTR_COLD; + static void traceInit(void* userp, VerilatedVcd* tracep, uint32_t code) VL_ATTR_COLD; +} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES); + +//---------- + + +#endif // guard diff --git a/verilog/alu/v6/obj_dir/Valu6.mk b/verilog/alu/v6/obj_dir/Valu6.mk new file mode 100644 index 0000000..d782d11 --- /dev/null +++ b/verilog/alu/v6/obj_dir/Valu6.mk @@ -0,0 +1,66 @@ +# Verilated -*- Makefile -*- +# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable +# +# Execute this makefile from the object directory: +# make -f Valu6.mk + +default: Valu6 + +### Constants... +# Perl executable (from $PERL) +PERL = perl +# Path to Verilator kit (from $VERILATOR_ROOT) +VERILATOR_ROOT = /usr/share/verilator +# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE) +SYSTEMC_INCLUDE ?= +# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR) +SYSTEMC_LIBDIR ?= + +### Switches... +# SystemC output mode? 0/1 (from --sc) +VM_SC = 0 +# Legacy or SystemC output mode? 0/1 (from --sc) +VM_SP_OR_SC = $(VM_SC) +# Deprecated +VM_PCLI = 1 +# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH) +VM_SC_TARGET_ARCH = linux + +### Vars... +# Design prefix (from --prefix) +VM_PREFIX = Valu6 +# Module prefix (from --prefix) +VM_MODPREFIX = Valu6 +# User CFLAGS (from -CFLAGS on Verilator command line) +VM_USER_CFLAGS = \ + +# User LDLIBS (from -LDFLAGS on Verilator command line) +VM_USER_LDLIBS = \ + +# User .cpp files (from .cpp's on Verilator command line) +VM_USER_CLASSES = \ + tbalu \ + +# User .cpp directories (from .cpp's on Verilator command line) +VM_USER_DIR = \ + . \ + + +### Default rules... +# Include list of all generated classes +include Valu6_classes.mk +# Include global rules +include $(VERILATOR_ROOT)/include/verilated.mk + +### Executable rules... (from --exe) +VPATH += $(VM_USER_DIR) + +tbalu.o: tbalu.cpp + $(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $< + +### Link rules... (from --exe) +Valu6: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a $(VM_HIER_LIBS) + $(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) $(LIBS) $(SC_LIBS) -o $@ + + +# Verilated -*- Makefile -*- diff --git a/verilog/alu/v6/obj_dir/Valu6__ALL.a b/verilog/alu/v6/obj_dir/Valu6__ALL.a Binary files differnew file mode 100644 index 0000000..b05f397 --- /dev/null +++ b/verilog/alu/v6/obj_dir/Valu6__ALL.a diff --git a/verilog/alu/v6/obj_dir/Valu6__ALL.cpp b/verilog/alu/v6/obj_dir/Valu6__ALL.cpp new file mode 100644 index 0000000..4e6f1a1 --- /dev/null +++ b/verilog/alu/v6/obj_dir/Valu6__ALL.cpp @@ -0,0 +1,9 @@ +// DESCRIPTION: Generated by verilator_includer via makefile +#define VL_INCLUDE_OPT include +#include "Valu6.cpp" +#include "Valu6___024root__DepSet_he7565067__0.cpp" +#include "Valu6__Trace__0.cpp" +#include "Valu6___024root__Slow.cpp" +#include "Valu6___024root__DepSet_he7565067__0__Slow.cpp" +#include "Valu6__Syms.cpp" +#include "Valu6__Trace__0__Slow.cpp" diff --git a/verilog/alu/v6/obj_dir/Valu6__ALL.d b/verilog/alu/v6/obj_dir/Valu6__ALL.d new file mode 100644 index 0000000..0dd5496 --- /dev/null +++ b/verilog/alu/v6/obj_dir/Valu6__ALL.d @@ -0,0 +1,13 @@ +Valu6__ALL.o: Valu6__ALL.cpp Valu6.cpp Valu6.h \ + /usr/share/verilator/include/verilated.h \ + /usr/share/verilator/include/verilatedos.h \ + /usr/share/verilator/include/verilated_config.h \ + /usr/share/verilator/include/verilated_types.h \ + /usr/share/verilator/include/verilated_funcs.h Valu6__Syms.h \ + Valu6___024root.h /usr/share/verilator/include/verilated_vcd_c.h \ + /usr/share/verilator/include/verilated.h \ + /usr/share/verilator/include/verilated_trace.h \ + /usr/share/verilator/include/verilated_trace_defs.h \ + Valu6___024root__DepSet_he7565067__0.cpp Valu6__Trace__0.cpp \ + Valu6___024root__Slow.cpp Valu6___024root__DepSet_he7565067__0__Slow.cpp \ + Valu6__Syms.cpp Valu6__Trace__0__Slow.cpp diff --git a/verilog/alu/v6/obj_dir/Valu6__ALL.o b/verilog/alu/v6/obj_dir/Valu6__ALL.o Binary files differnew file mode 100644 index 0000000..93f9ee6 --- /dev/null +++ b/verilog/alu/v6/obj_dir/Valu6__ALL.o diff --git a/verilog/alu/v6/obj_dir/Valu6__Slow.cpp b/verilog/alu/v6/obj_dir/Valu6__Slow.cpp new file mode 100644 index 0000000..6cd030d --- /dev/null +++ b/verilog/alu/v6/obj_dir/Valu6__Slow.cpp @@ -0,0 +1,61 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design implementation internals +// See Valu6.h for the primary calling header + +#include "Valu6.h" +#include "Valu6__Syms.h" + +//========== + +VL_CTOR_IMP(Valu6) { + Valu6__Syms* __restrict vlSymsp = __VlSymsp = new Valu6__Syms(this, name()); + Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Reset internal values + + // Reset structure values + _ctor_var_reset(); +} + +void Valu6::__Vconfigure(Valu6__Syms* vlSymsp, bool first) { + if (false && first) {} // Prevent unused + this->__VlSymsp = vlSymsp; + if (false && this->__VlSymsp) {} // Prevent unused + Verilated::timeunit(-6); + Verilated::timeprecision(-9); +} + +Valu6::~Valu6() { + VL_DO_CLEAR(delete __VlSymsp, __VlSymsp = nullptr); +} + +void Valu6::_eval_initial(Valu6__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6::_eval_initial\n"); ); + Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; +} + +void Valu6::final() { + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6::final\n"); ); + // Variables + Valu6__Syms* __restrict vlSymsp = this->__VlSymsp; + Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; +} + +void Valu6::_eval_settle(Valu6__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6::_eval_settle\n"); ); + Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->_combo__TOP__1(vlSymsp); +} + +void Valu6::_ctor_var_reset() { + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6::_ctor_var_reset\n"); ); + // Body + alu_in_1 = VL_RAND_RESET_I(32); + alu_in_2 = VL_RAND_RESET_I(32); + alu_op_i = VL_RAND_RESET_I(4); + alu_output = VL_RAND_RESET_I(32); + alu6__DOT__sum = VL_RAND_RESET_I(32); + for (int __Vi0=0; __Vi0<1; ++__Vi0) { + __Vm_traceActivity[__Vi0] = VL_RAND_RESET_I(1); + } +} diff --git a/verilog/alu/v6/obj_dir/Valu6__Syms.cpp b/verilog/alu/v6/obj_dir/Valu6__Syms.cpp new file mode 100644 index 0000000..c9b82af --- /dev/null +++ b/verilog/alu/v6/obj_dir/Valu6__Syms.cpp @@ -0,0 +1,27 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Symbol table implementation internals + +#include "Valu6__Syms.h" +#include "Valu6.h" + + + +// FUNCTIONS +Valu6__Syms::~Valu6__Syms() +{ +} + +Valu6__Syms::Valu6__Syms(Valu6* topp, const char* namep) + // Setup locals + : __Vm_namep(namep) + , __Vm_activity(false) + , __Vm_baseCode(0) + , __Vm_didInit(false) + // Setup submodule names +{ + // Pointer to top level + TOPp = topp; + // Setup each module's pointers to their submodules + // Setup each module's pointer back to symbol table (for public functions) + TOPp->__Vconfigure(this, true); +} diff --git a/verilog/alu/v6/obj_dir/Valu6__Syms.h b/verilog/alu/v6/obj_dir/Valu6__Syms.h new file mode 100644 index 0000000..dcbc3c1 --- /dev/null +++ b/verilog/alu/v6/obj_dir/Valu6__Syms.h @@ -0,0 +1,37 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Symbol table internal header +// +// Internal details; most calling programs do not need this header, +// unless using verilator public meta comments. + +#ifndef _VALU6__SYMS_H_ +#define _VALU6__SYMS_H_ // guard + +#include "verilated_heavy.h" + +// INCLUDE MODULE CLASSES +#include "Valu6.h" + +// SYMS CLASS +class Valu6__Syms : public VerilatedSyms { + public: + + // LOCAL STATE + const char* __Vm_namep; + bool __Vm_activity; ///< Used by trace routines to determine change occurred + uint32_t __Vm_baseCode; ///< Used by trace routines when tracing multiple models + bool __Vm_didInit; + + // SUBCELL STATE + Valu6* TOPp; + + // CREATORS + Valu6__Syms(Valu6* topp, const char* namep); + ~Valu6__Syms(); + + // METHODS + inline const char* name() { return __Vm_namep; } + +} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES); + +#endif // guard diff --git a/verilog/alu/v6/obj_dir/Valu6__Trace.cpp b/verilog/alu/v6/obj_dir/Valu6__Trace.cpp new file mode 100644 index 0000000..e2e3658 --- /dev/null +++ b/verilog/alu/v6/obj_dir/Valu6__Trace.cpp @@ -0,0 +1,76 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Tracing implementation internals +#include "verilated_vcd_c.h" +#include "Valu6__Syms.h" + + +void Valu6::traceChgTop0(void* userp, VerilatedVcd* tracep) { + Valu6__Syms* __restrict vlSymsp = static_cast<Valu6__Syms*>(userp); + Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Variables + if (VL_UNLIKELY(!vlSymsp->__Vm_activity)) return; + // Body + { + vlTOPp->traceChgSub0(userp, tracep); + } +} + +void Valu6::traceChgSub0(void* userp, VerilatedVcd* tracep) { + Valu6__Syms* __restrict vlSymsp = static_cast<Valu6__Syms*>(userp); + Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + vluint32_t* const oldp = tracep->oldp(vlSymsp->__Vm_baseCode + 1); + if (false && oldp) {} // Prevent unused + // Body + { + tracep->chgIData(oldp+0,(vlTOPp->alu_in_1),32); + tracep->chgIData(oldp+1,(vlTOPp->alu_in_2),32); + tracep->chgCData(oldp+2,(vlTOPp->alu_op_i),4); + tracep->chgIData(oldp+3,(vlTOPp->alu_output),32); + tracep->chgIData(oldp+4,(((IData)(1U) + (~ vlTOPp->alu_in_2))),32); + tracep->chgIData(oldp+5,(vlTOPp->alu6__DOT__sum),32); + tracep->chgIData(oldp+6,((((0x1fU >= (0x3fU + & vlTOPp->alu_in_2)) + ? (vlTOPp->alu_in_1 + >> (0x3fU & vlTOPp->alu_in_2)) + : 0U) | ((8U & (IData)(vlTOPp->alu_op_i)) + ? ((IData)(0xffffffffU) + << + ((0x80000000U + & vlTOPp->alu_in_2) + ? 0U + : + ((0x10U + & ((~ + (vlTOPp->alu_in_2 + >> 4U)) + << 4U)) + | ((8U + & ((~ + (vlTOPp->alu_in_2 + >> 3U)) + << 3U)) + | ((4U + & ((~ + (vlTOPp->alu_in_2 + >> 2U)) + << 2U)) + | ((2U + & ((~ + (vlTOPp->alu_in_2 + >> 1U)) + << 1U)) + | (1U + & (~ vlTOPp->alu_in_2)))))))) + : 0U))),32); + } +} + +void Valu6::traceCleanup(void* userp, VerilatedVcd* /*unused*/) { + Valu6__Syms* __restrict vlSymsp = static_cast<Valu6__Syms*>(userp); + Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + { + vlSymsp->__Vm_activity = false; + vlTOPp->__Vm_traceActivity[0U] = 0U; + } +} diff --git a/verilog/alu/v6/obj_dir/Valu6__Trace__0.cpp b/verilog/alu/v6/obj_dir/Valu6__Trace__0.cpp new file mode 100644 index 0000000..b2933ac --- /dev/null +++ b/verilog/alu/v6/obj_dir/Valu6__Trace__0.cpp @@ -0,0 +1,77 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Tracing implementation internals +#include "verilated_vcd_c.h" +#include "Valu6__Syms.h" + + +void Valu6___024root__trace_chg_sub_0(Valu6___024root* vlSelf, VerilatedVcd* tracep); + +void Valu6___024root__trace_chg_top_0(void* voidSelf, VerilatedVcd* tracep) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6___024root__trace_chg_top_0\n"); ); + // Init + Valu6___024root* const __restrict vlSelf VL_ATTR_UNUSED = static_cast<Valu6___024root*>(voidSelf); + Valu6__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; + if (VL_UNLIKELY(!vlSymsp->__Vm_activity)) return; + // Body + Valu6___024root__trace_chg_sub_0((&vlSymsp->TOP), tracep); +} + +void Valu6___024root__trace_chg_sub_0(Valu6___024root* vlSelf, VerilatedVcd* tracep) { + if (false && vlSelf) {} // Prevent unused + Valu6__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6___024root__trace_chg_sub_0\n"); ); + // Init + vluint32_t* const oldp VL_ATTR_UNUSED = tracep->oldp(vlSymsp->__Vm_baseCode + 1); + // Body + tracep->chgIData(oldp+0,(vlSelf->alu_in_1),32); + tracep->chgIData(oldp+1,(vlSelf->alu_in_2),32); + tracep->chgCData(oldp+2,(vlSelf->alu_op_i),4); + tracep->chgIData(oldp+3,(vlSelf->alu_output),32); + tracep->chgIData(oldp+4,(vlSelf->debugsum),32); + tracep->chgCData(oldp+5,(vlSelf->debugop),4); + tracep->chgIData(oldp+6,(((IData)(1U) + (~ vlSelf->alu_in_2))),32); + tracep->chgIData(oldp+7,(vlSelf->alu6__DOT__sum),32); + tracep->chgIData(oldp+8,((((0x1fU >= (0x3fU & vlSelf->alu_in_2)) + ? (vlSelf->alu_in_1 + >> (0x3fU & vlSelf->alu_in_2)) + : 0U) | ((8U & (IData)(vlSelf->alu_op_i)) + ? ((IData)(0xffffffffU) + << ((vlSelf->alu_in_2 + >> 0x1fU) + ? 0U + : + ((0x10U + & ((~ + (vlSelf->alu_in_2 + >> 4U)) + << 4U)) + | ((8U + & ((~ + (vlSelf->alu_in_2 + >> 3U)) + << 3U)) + | ((4U + & ((~ + (vlSelf->alu_in_2 + >> 2U)) + << 2U)) + | ((2U + & ((~ + (vlSelf->alu_in_2 + >> 1U)) + << 1U)) + | (1U + & (~ vlSelf->alu_in_2)))))))) + : 0U))),32); +} + +void Valu6___024root__trace_cleanup(void* voidSelf, VerilatedVcd* /*unused*/) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6___024root__trace_cleanup\n"); ); + // Init + Valu6___024root* const __restrict vlSelf VL_ATTR_UNUSED = static_cast<Valu6___024root*>(voidSelf); + Valu6__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; + VlUnpacked<CData/*0:0*/, 1> __Vm_traceActivity; + // Body + vlSymsp->__Vm_activity = false; + __Vm_traceActivity[0U] = 0U; +} diff --git a/verilog/alu/v6/obj_dir/Valu6__Trace__0__Slow.cpp b/verilog/alu/v6/obj_dir/Valu6__Trace__0__Slow.cpp new file mode 100644 index 0000000..83ce895 --- /dev/null +++ b/verilog/alu/v6/obj_dir/Valu6__Trace__0__Slow.cpp @@ -0,0 +1,113 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Tracing implementation internals +#include "verilated_vcd_c.h" +#include "Valu6__Syms.h" + + +VL_ATTR_COLD void Valu6___024root__trace_init_sub__TOP__0(Valu6___024root* vlSelf, VerilatedVcd* tracep) { + if (false && vlSelf) {} // Prevent unused + Valu6__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6___024root__trace_init_sub__TOP__0\n"); ); + // Init + const int c = vlSymsp->__Vm_baseCode; + // Body + tracep->declBus(c+1,"alu_in_1", false,-1, 31,0); + tracep->declBus(c+2,"alu_in_2", false,-1, 31,0); + tracep->declBus(c+3,"alu_op_i", false,-1, 3,0); + tracep->declBus(c+4,"alu_output", false,-1, 31,0); + tracep->declBus(c+5,"debugsum", false,-1, 31,0); + tracep->declBus(c+6,"debugop", false,-1, 3,0); + tracep->pushNamePrefix("alu6 "); + tracep->declBus(c+1,"alu_in_1", false,-1, 31,0); + tracep->declBus(c+2,"alu_in_2", false,-1, 31,0); + tracep->declBus(c+3,"alu_op_i", false,-1, 3,0); + tracep->declBus(c+4,"alu_output", false,-1, 31,0); + tracep->declBus(c+5,"debugsum", false,-1, 31,0); + tracep->declBus(c+6,"debugop", false,-1, 3,0); + tracep->declBus(c+7,"complement2", false,-1, 31,0); + tracep->declBus(c+8,"sum", false,-1, 31,0); + tracep->declBus(c+9,"right", false,-1, 31,0); + tracep->popNamePrefix(1); +} + +VL_ATTR_COLD void Valu6___024root__trace_init_top(Valu6___024root* vlSelf, VerilatedVcd* tracep) { + if (false && vlSelf) {} // Prevent unused + Valu6__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6___024root__trace_init_top\n"); ); + // Body + Valu6___024root__trace_init_sub__TOP__0(vlSelf, tracep); +} + +VL_ATTR_COLD void Valu6___024root__trace_full_top_0(void* voidSelf, VerilatedVcd* tracep); +void Valu6___024root__trace_chg_top_0(void* voidSelf, VerilatedVcd* tracep); +void Valu6___024root__trace_cleanup(void* voidSelf, VerilatedVcd* /*unused*/); + +VL_ATTR_COLD void Valu6___024root__trace_register(Valu6___024root* vlSelf, VerilatedVcd* tracep) { + if (false && vlSelf) {} // Prevent unused + Valu6__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6___024root__trace_register\n"); ); + // Body + tracep->addFullCb(&Valu6___024root__trace_full_top_0, vlSelf); + tracep->addChgCb(&Valu6___024root__trace_chg_top_0, vlSelf); + tracep->addCleanupCb(&Valu6___024root__trace_cleanup, vlSelf); +} + +VL_ATTR_COLD void Valu6___024root__trace_full_sub_0(Valu6___024root* vlSelf, VerilatedVcd* tracep); + +VL_ATTR_COLD void Valu6___024root__trace_full_top_0(void* voidSelf, VerilatedVcd* tracep) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6___024root__trace_full_top_0\n"); ); + // Init + Valu6___024root* const __restrict vlSelf VL_ATTR_UNUSED = static_cast<Valu6___024root*>(voidSelf); + Valu6__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; + // Body + Valu6___024root__trace_full_sub_0((&vlSymsp->TOP), tracep); +} + +VL_ATTR_COLD void Valu6___024root__trace_full_sub_0(Valu6___024root* vlSelf, VerilatedVcd* tracep) { + if (false && vlSelf) {} // Prevent unused + Valu6__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6___024root__trace_full_sub_0\n"); ); + // Init + vluint32_t* const oldp VL_ATTR_UNUSED = tracep->oldp(vlSymsp->__Vm_baseCode); + // Body + tracep->fullIData(oldp+1,(vlSelf->alu_in_1),32); + tracep->fullIData(oldp+2,(vlSelf->alu_in_2),32); + tracep->fullCData(oldp+3,(vlSelf->alu_op_i),4); + tracep->fullIData(oldp+4,(vlSelf->alu_output),32); + tracep->fullIData(oldp+5,(vlSelf->debugsum),32); + tracep->fullCData(oldp+6,(vlSelf->debugop),4); + tracep->fullIData(oldp+7,(((IData)(1U) + (~ vlSelf->alu_in_2))),32); + tracep->fullIData(oldp+8,(vlSelf->alu6__DOT__sum),32); + tracep->fullIData(oldp+9,((((0x1fU >= (0x3fU & vlSelf->alu_in_2)) + ? (vlSelf->alu_in_1 + >> (0x3fU & vlSelf->alu_in_2)) + : 0U) | ((8U & (IData)(vlSelf->alu_op_i)) + ? ((IData)(0xffffffffU) + << ((vlSelf->alu_in_2 + >> 0x1fU) + ? 0U + : + ((0x10U + & ((~ + (vlSelf->alu_in_2 + >> 4U)) + << 4U)) + | ((8U + & ((~ + (vlSelf->alu_in_2 + >> 3U)) + << 3U)) + | ((4U + & ((~ + (vlSelf->alu_in_2 + >> 2U)) + << 2U)) + | ((2U + & ((~ + (vlSelf->alu_in_2 + >> 1U)) + << 1U)) + | (1U + & (~ vlSelf->alu_in_2)))))))) + : 0U))),32); +} diff --git a/verilog/alu/v6/obj_dir/Valu6__Trace__Slow.cpp b/verilog/alu/v6/obj_dir/Valu6__Trace__Slow.cpp new file mode 100644 index 0000000..89bdf46 --- /dev/null +++ b/verilog/alu/v6/obj_dir/Valu6__Trace__Slow.cpp @@ -0,0 +1,127 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Tracing implementation internals +#include "verilated_vcd_c.h" +#include "Valu6__Syms.h" + + +//====================== + +void Valu6::trace(VerilatedVcdC* tfp, int, int) { + tfp->spTrace()->addInitCb(&traceInit, __VlSymsp); + traceRegister(tfp->spTrace()); +} + +void Valu6::traceInit(void* userp, VerilatedVcd* tracep, uint32_t code) { + // Callback from tracep->open() + Valu6__Syms* __restrict vlSymsp = static_cast<Valu6__Syms*>(userp); + if (!Verilated::calcUnusedSigs()) { + VL_FATAL_MT(__FILE__, __LINE__, __FILE__, + "Turning on wave traces requires Verilated::traceEverOn(true) call before time 0."); + } + vlSymsp->__Vm_baseCode = code; + tracep->module(vlSymsp->name()); + tracep->scopeEscape(' '); + Valu6::traceInitTop(vlSymsp, tracep); + tracep->scopeEscape('.'); +} + +//====================== + + +void Valu6::traceInitTop(void* userp, VerilatedVcd* tracep) { + Valu6__Syms* __restrict vlSymsp = static_cast<Valu6__Syms*>(userp); + Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + { + vlTOPp->traceInitSub0(userp, tracep); + } +} + +void Valu6::traceInitSub0(void* userp, VerilatedVcd* tracep) { + Valu6__Syms* __restrict vlSymsp = static_cast<Valu6__Syms*>(userp); + Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + const int c = vlSymsp->__Vm_baseCode; + if (false && tracep && c) {} // Prevent unused + // Body + { + tracep->declBus(c+1,"alu_in_1", false,-1, 31,0); + tracep->declBus(c+2,"alu_in_2", false,-1, 31,0); + tracep->declBus(c+3,"alu_op_i", false,-1, 3,0); + tracep->declBus(c+4,"alu_output", false,-1, 31,0); + tracep->declBus(c+1,"alu6 alu_in_1", false,-1, 31,0); + tracep->declBus(c+2,"alu6 alu_in_2", false,-1, 31,0); + tracep->declBus(c+3,"alu6 alu_op_i", false,-1, 3,0); + tracep->declBus(c+4,"alu6 alu_output", false,-1, 31,0); + tracep->declBus(c+5,"alu6 complement2", false,-1, 31,0); + tracep->declBus(c+6,"alu6 sum", false,-1, 31,0); + tracep->declBus(c+7,"alu6 right", false,-1, 31,0); + } +} + +void Valu6::traceRegister(VerilatedVcd* tracep) { + // Body + { + tracep->addFullCb(&traceFullTop0, __VlSymsp); + tracep->addChgCb(&traceChgTop0, __VlSymsp); + tracep->addCleanupCb(&traceCleanup, __VlSymsp); + } +} + +void Valu6::traceFullTop0(void* userp, VerilatedVcd* tracep) { + Valu6__Syms* __restrict vlSymsp = static_cast<Valu6__Syms*>(userp); + Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + { + vlTOPp->traceFullSub0(userp, tracep); + } +} + +void Valu6::traceFullSub0(void* userp, VerilatedVcd* tracep) { + Valu6__Syms* __restrict vlSymsp = static_cast<Valu6__Syms*>(userp); + Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + vluint32_t* const oldp = tracep->oldp(vlSymsp->__Vm_baseCode); + if (false && oldp) {} // Prevent unused + // Body + { + tracep->fullIData(oldp+1,(vlTOPp->alu_in_1),32); + tracep->fullIData(oldp+2,(vlTOPp->alu_in_2),32); + tracep->fullCData(oldp+3,(vlTOPp->alu_op_i),4); + tracep->fullIData(oldp+4,(vlTOPp->alu_output),32); + tracep->fullIData(oldp+5,(((IData)(1U) + (~ vlTOPp->alu_in_2))),32); + tracep->fullIData(oldp+6,(vlTOPp->alu6__DOT__sum),32); + tracep->fullIData(oldp+7,((((0x1fU >= (0x3fU + & vlTOPp->alu_in_2)) + ? (vlTOPp->alu_in_1 + >> (0x3fU & vlTOPp->alu_in_2)) + : 0U) | ((8U & (IData)(vlTOPp->alu_op_i)) + ? ((IData)(0xffffffffU) + << + ((0x80000000U + & vlTOPp->alu_in_2) + ? 0U + : + ((0x10U + & ((~ + (vlTOPp->alu_in_2 + >> 4U)) + << 4U)) + | ((8U + & ((~ + (vlTOPp->alu_in_2 + >> 3U)) + << 3U)) + | ((4U + & ((~ + (vlTOPp->alu_in_2 + >> 2U)) + << 2U)) + | ((2U + & ((~ + (vlTOPp->alu_in_2 + >> 1U)) + << 1U)) + | (1U + & (~ vlTOPp->alu_in_2)))))))) + : 0U))),32); + } +} diff --git a/verilog/alu/v6/obj_dir/Valu6___024root.h b/verilog/alu/v6/obj_dir/Valu6___024root.h new file mode 100644 index 0000000..f568bf9 --- /dev/null +++ b/verilog/alu/v6/obj_dir/Valu6___024root.h @@ -0,0 +1,36 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design internal header +// See Valu6.h for the primary calling header + +#ifndef VERILATED_VALU6___024ROOT_H_ +#define VERILATED_VALU6___024ROOT_H_ // guard + +#include "verilated.h" + +class Valu6__Syms; +VL_MODULE(Valu6___024root) { + public: + + // DESIGN SPECIFIC STATE + VL_IN8(alu_op_i,3,0); + VL_OUT8(debugop,3,0); + VL_IN(alu_in_1,31,0); + VL_IN(alu_in_2,31,0); + VL_OUT(alu_output,31,0); + VL_OUT(debugsum,31,0); + IData/*31:0*/ alu6__DOT__sum; + + // INTERNAL VARIABLES + Valu6__Syms* vlSymsp; // Symbol table + + // CONSTRUCTORS + Valu6___024root(const char* name); + ~Valu6___024root(); + VL_UNCOPYABLE(Valu6___024root); + + // INTERNAL METHODS + void __Vconfigure(Valu6__Syms* symsp, bool first); +} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES); + + +#endif // guard diff --git a/verilog/alu/v6/obj_dir/Valu6___024root__DepSet_he7565067__0.cpp b/verilog/alu/v6/obj_dir/Valu6___024root__DepSet_he7565067__0.cpp new file mode 100644 index 0000000..afd43c4 --- /dev/null +++ b/verilog/alu/v6/obj_dir/Valu6___024root__DepSet_he7565067__0.cpp @@ -0,0 +1,137 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design implementation internals +// See Valu6.h for the primary calling header + +#include "verilated.h" + +#include "Valu6___024root.h" + +VL_INLINE_OPT void Valu6___024root___combo__TOP__0(Valu6___024root* vlSelf) { + if (false && vlSelf) {} // Prevent unused + Valu6__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6___024root___combo__TOP__0\n"); ); + // Body + vlSelf->debugop = vlSelf->alu_op_i; + vlSelf->alu6__DOT__sum = (vlSelf->alu_in_1 + ((IData)( + (((IData)(vlSelf->alu_op_i) + >> 3U) + | (2U + == + (3U + & (IData)(vlSelf->alu_op_i))))) + ? + ((IData)(1U) + + + (~ vlSelf->alu_in_2)) + : vlSelf->alu_in_2)); + vlSelf->debugsum = vlSelf->alu6__DOT__sum; + vlSelf->alu_output = ((0U == (7U & (IData)(vlSelf->alu_op_i))) + ? vlSelf->alu6__DOT__sum + : ((4U == (7U & (IData)(vlSelf->alu_op_i))) + ? (vlSelf->alu_in_1 + ^ vlSelf->alu_in_2) + : ((6U == (7U & (IData)(vlSelf->alu_op_i))) + ? (vlSelf->alu_in_1 + | vlSelf->alu_in_2) + : ((7U == (7U & (IData)(vlSelf->alu_op_i))) + ? (vlSelf->alu_in_1 + & vlSelf->alu_in_2) + : ((1U == (7U + & (IData)(vlSelf->alu_op_i))) + ? ((0x40U + & vlSelf->alu_in_2) + ? 0U + : ((0x1fU + >= + (0x3fU + & vlSelf->alu_in_2)) + ? + (vlSelf->alu_in_1 + << + (0x3fU + & vlSelf->alu_in_2)) + : 0U)) + : ((5U == + (7U + & (IData)(vlSelf->alu_op_i))) + ? (( + (0x1fU + >= + (0x3fU + & vlSelf->alu_in_2)) + ? + (vlSelf->alu_in_1 + >> + (0x3fU + & vlSelf->alu_in_2)) + : 0U) + | ((8U + & (IData)(vlSelf->alu_op_i)) + ? + ((IData)(0xffffffffU) + << + ((vlSelf->alu_in_2 + >> 0x1fU) + ? 0U + : + ((0x10U + & ((~ + (vlSelf->alu_in_2 + >> 4U)) + << 4U)) + | ((8U + & ((~ + (vlSelf->alu_in_2 + >> 3U)) + << 3U)) + | ((4U + & ((~ + (vlSelf->alu_in_2 + >> 2U)) + << 2U)) + | ((2U + & ((~ + (vlSelf->alu_in_2 + >> 1U)) + << 1U)) + | (1U + & (~ vlSelf->alu_in_2)))))))) + : 0U)) + : ((2U + == + (7U + & (IData)(vlSelf->alu_op_i))) + ? + (vlSelf->alu6__DOT__sum + >> 0x1fU) + : + ((3U + == + (7U + & (IData)(vlSelf->alu_op_i))) + ? + ((vlSelf->alu_in_1 + < vlSelf->alu_in_2) + ? 1U + : 0U) + : 0U)))))))); +} + +void Valu6___024root___eval(Valu6___024root* vlSelf) { + if (false && vlSelf) {} // Prevent unused + Valu6__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6___024root___eval\n"); ); + // Body + Valu6___024root___combo__TOP__0(vlSelf); +} + +#ifdef VL_DEBUG +void Valu6___024root___eval_debug_assertions(Valu6___024root* vlSelf) { + if (false && vlSelf) {} // Prevent unused + Valu6__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6___024root___eval_debug_assertions\n"); ); + // Body + if (VL_UNLIKELY((vlSelf->alu_op_i & 0xf0U))) { + Verilated::overWidthError("alu_op_i");} +} +#endif // VL_DEBUG diff --git a/verilog/alu/v6/obj_dir/Valu6___024root__DepSet_he7565067__0__Slow.cpp b/verilog/alu/v6/obj_dir/Valu6___024root__DepSet_he7565067__0__Slow.cpp new file mode 100644 index 0000000..896483f --- /dev/null +++ b/verilog/alu/v6/obj_dir/Valu6___024root__DepSet_he7565067__0__Slow.cpp @@ -0,0 +1,43 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design implementation internals +// See Valu6.h for the primary calling header + +#include "verilated.h" + +#include "Valu6___024root.h" + +VL_ATTR_COLD void Valu6___024root___eval_initial(Valu6___024root* vlSelf) { + if (false && vlSelf) {} // Prevent unused + Valu6__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6___024root___eval_initial\n"); ); +} + +void Valu6___024root___combo__TOP__0(Valu6___024root* vlSelf); + +VL_ATTR_COLD void Valu6___024root___eval_settle(Valu6___024root* vlSelf) { + if (false && vlSelf) {} // Prevent unused + Valu6__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6___024root___eval_settle\n"); ); + // Body + Valu6___024root___combo__TOP__0(vlSelf); +} + +VL_ATTR_COLD void Valu6___024root___final(Valu6___024root* vlSelf) { + if (false && vlSelf) {} // Prevent unused + Valu6__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6___024root___final\n"); ); +} + +VL_ATTR_COLD void Valu6___024root___ctor_var_reset(Valu6___024root* vlSelf) { + if (false && vlSelf) {} // Prevent unused + Valu6__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6___024root___ctor_var_reset\n"); ); + // Body + vlSelf->alu_in_1 = VL_RAND_RESET_I(32); + vlSelf->alu_in_2 = VL_RAND_RESET_I(32); + vlSelf->alu_op_i = VL_RAND_RESET_I(4); + vlSelf->alu_output = VL_RAND_RESET_I(32); + vlSelf->debugsum = VL_RAND_RESET_I(32); + vlSelf->debugop = VL_RAND_RESET_I(4); + vlSelf->alu6__DOT__sum = VL_RAND_RESET_I(32); +} diff --git a/verilog/alu/v6/obj_dir/Valu6___024root__Slow.cpp b/verilog/alu/v6/obj_dir/Valu6___024root__Slow.cpp new file mode 100644 index 0000000..9918041 --- /dev/null +++ b/verilog/alu/v6/obj_dir/Valu6___024root__Slow.cpp @@ -0,0 +1,25 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design implementation internals +// See Valu6.h for the primary calling header + +#include "verilated.h" + +#include "Valu6__Syms.h" +#include "Valu6___024root.h" + +void Valu6___024root___ctor_var_reset(Valu6___024root* vlSelf); + +Valu6___024root::Valu6___024root(const char* _vcname__) + : VerilatedModule(_vcname__) + { + // Reset structure values + Valu6___024root___ctor_var_reset(this); +} + +void Valu6___024root::__Vconfigure(Valu6__Syms* _vlSymsp, bool first) { + if (false && first) {} // Prevent unused + this->vlSymsp = _vlSymsp; +} + +Valu6___024root::~Valu6___024root() { +} diff --git a/verilog/alu/v6/obj_dir/Valu6__ver.d b/verilog/alu/v6/obj_dir/Valu6__ver.d new file mode 100644 index 0000000..38bf8e0 --- /dev/null +++ b/verilog/alu/v6/obj_dir/Valu6__ver.d @@ -0,0 +1 @@ +obj_dir/Valu6.cpp obj_dir/Valu6.h obj_dir/Valu6.mk obj_dir/Valu6__Slow.cpp obj_dir/Valu6__Syms.cpp obj_dir/Valu6__Syms.h obj_dir/Valu6__Trace.cpp obj_dir/Valu6__Trace__Slow.cpp obj_dir/Valu6__ver.d obj_dir/Valu6_classes.mk : /usr/bin/verilator_bin /usr/bin/verilator_bin alu6.v aluOp.vh diff --git a/verilog/alu/v6/obj_dir/Valu6__verFiles.dat b/verilog/alu/v6/obj_dir/Valu6__verFiles.dat new file mode 100644 index 0000000..389cc3d --- /dev/null +++ b/verilog/alu/v6/obj_dir/Valu6__verFiles.dat @@ -0,0 +1,16 @@ +# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will. +C "-Wall --cc --exe --build tbalu.cpp alu6.v --trace" +S 7544824 425500 1651977992 501242168 1627086909 0 "/usr/bin/verilator_bin" +S 982 195432 1652382291 705526780 1652382291 704526776 "alu6.v" +S 369 130885 1652206009 461809710 1652206009 461809710 "aluOp.vh" +T 10458 130865 1652382292 927532038 1652382292 927532038 "obj_dir/Valu6.cpp" +T 3600 130864 1652382292 927532038 1652382292 927532038 "obj_dir/Valu6.h" +T 1760 130873 1652382292 927532038 1652382292 927532038 "obj_dir/Valu6.mk" +T 1849 195436 1652382292 927532038 1652382292 927532038 "obj_dir/Valu6__Slow.cpp" +T 617 130862 1652382292 926532034 1652382292 926532034 "obj_dir/Valu6__Syms.cpp" +T 946 130863 1652382292 926532034 1652382292 926532034 "obj_dir/Valu6__Syms.h" +T 3801 195435 1652382292 927532038 1652382292 927532038 "obj_dir/Valu6__Trace.cpp" +T 5706 195434 1652382292 927532038 1652382292 927532038 "obj_dir/Valu6__Trace__Slow.cpp" +T 289 130861 1652382292 927532038 1652382292 927532038 "obj_dir/Valu6__ver.d" +T 0 0 1652382292 927532038 1652382292 927532038 "obj_dir/Valu6__verFiles.dat" +T 1641 130872 1652382292 927532038 1652382292 927532038 "obj_dir/Valu6_classes.mk" diff --git a/verilog/alu/v6/obj_dir/Valu6_classes.mk b/verilog/alu/v6/obj_dir/Valu6_classes.mk new file mode 100644 index 0000000..e08ed68 --- /dev/null +++ b/verilog/alu/v6/obj_dir/Valu6_classes.mk @@ -0,0 +1,52 @@ +# Verilated -*- Makefile -*- +# DESCRIPTION: Verilator output: Make include file with class lists +# +# This file lists generated Verilated files, for including in higher level makefiles. +# See Valu6.mk for the caller. + +### Switches... +# C11 constructs required? 0/1 (always on now) +VM_C11 = 1 +# Coverage output mode? 0/1 (from --coverage) +VM_COVERAGE = 0 +# Parallel builds? 0/1 (from --output-split) +VM_PARALLEL_BUILDS = 0 +# Threaded output mode? 0/1/N threads (from --threads) +VM_THREADS = 0 +# Tracing output mode? 0/1 (from --trace/--trace-fst) +VM_TRACE = 1 +# Tracing output mode in FST format? 0/1 (from --trace-fst) +VM_TRACE_FST = 0 +# Tracing threaded output mode? 0/1/N threads (from --trace-thread) +VM_TRACE_THREADS = 0 +# Separate FST writer thread? 0/1 (from --trace-fst with --trace-thread > 0) +VM_TRACE_FST_WRITER_THREAD = 0 + +### Object file lists... +# Generated module classes, fast-path, compile with highest optimization +VM_CLASSES_FAST += \ + Valu6 \ + +# Generated module classes, non-fast-path, compile with low/medium optimization +VM_CLASSES_SLOW += \ + Valu6__Slow \ + +# Generated support classes, fast-path, compile with highest optimization +VM_SUPPORT_FAST += \ + Valu6__Trace \ + +# Generated support classes, non-fast-path, compile with low/medium optimization +VM_SUPPORT_SLOW += \ + Valu6__Syms \ + Valu6__Trace__Slow \ + +# Global classes, need linked once per executable, fast-path, compile with highest optimization +VM_GLOBAL_FAST += \ + verilated \ + verilated_vcd_c \ + +# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization +VM_GLOBAL_SLOW += \ + + +# Verilated -*- Makefile -*- diff --git a/verilog/alu/v6/obj_dir/tbalu.d b/verilog/alu/v6/obj_dir/tbalu.d new file mode 100644 index 0000000..7d7066c --- /dev/null +++ b/verilog/alu/v6/obj_dir/tbalu.d @@ -0,0 +1,9 @@ +tbalu.o: ../tbalu.cpp /usr/share/verilator/include/verilated.h \ + /usr/share/verilator/include/verilatedos.h \ + /usr/share/verilator/include/verilated_config.h \ + /usr/share/verilator/include/verilated_types.h \ + /usr/share/verilator/include/verilated_funcs.h \ + /usr/share/verilator/include/verilated_vcd_c.h \ + /usr/share/verilator/include/verilated.h \ + /usr/share/verilator/include/verilated_trace.h \ + /usr/share/verilator/include/verilated_trace_defs.h Valu6.h ../aluOp.h diff --git a/verilog/alu/v6/obj_dir/tbalu.o b/verilog/alu/v6/obj_dir/tbalu.o Binary files differnew file mode 100644 index 0000000..f612394 --- /dev/null +++ b/verilog/alu/v6/obj_dir/tbalu.o diff --git a/verilog/alu/v6/obj_dir/verilated.d b/verilog/alu/v6/obj_dir/verilated.d new file mode 100644 index 0000000..7f4c5e4 --- /dev/null +++ b/verilog/alu/v6/obj_dir/verilated.d @@ -0,0 +1,9 @@ +verilated.o: /usr/share/verilator/include/verilated.cpp \ + /usr/share/verilator/include/verilatedos.h \ + /usr/share/verilator/include/verilated_imp.h \ + /usr/share/verilator/include/verilated.h \ + /usr/share/verilator/include/verilated_config.h \ + /usr/share/verilator/include/verilated_types.h \ + /usr/share/verilator/include/verilated_funcs.h \ + /usr/share/verilator/include/verilated_syms.h \ + /usr/share/verilator/include/verilated_sym_props.h diff --git a/verilog/alu/v6/obj_dir/verilated.o b/verilog/alu/v6/obj_dir/verilated.o Binary files differnew file mode 100644 index 0000000..a226a8b --- /dev/null +++ b/verilog/alu/v6/obj_dir/verilated.o diff --git a/verilog/alu/v6/obj_dir/verilated_vcd_c.d b/verilog/alu/v6/obj_dir/verilated_vcd_c.d new file mode 100644 index 0000000..667485f --- /dev/null +++ b/verilog/alu/v6/obj_dir/verilated_vcd_c.d @@ -0,0 +1,11 @@ +verilated_vcd_c.o: /usr/share/verilator/include/verilated_vcd_c.cpp \ + /usr/share/verilator/include/verilatedos.h \ + /usr/share/verilator/include/verilated.h \ + /usr/share/verilator/include/verilated_config.h \ + /usr/share/verilator/include/verilated_types.h \ + /usr/share/verilator/include/verilated_funcs.h \ + /usr/share/verilator/include/verilated_vcd_c.h \ + /usr/share/verilator/include/verilated_trace.h \ + /usr/share/verilator/include/verilated_trace_defs.h \ + /usr/share/verilator/include/verilated_trace_imp.cpp \ + /usr/share/verilator/include/verilated_intrinsics.h diff --git a/verilog/alu/v6/obj_dir/verilated_vcd_c.o b/verilog/alu/v6/obj_dir/verilated_vcd_c.o Binary files differnew file mode 100644 index 0000000..469c75e --- /dev/null +++ b/verilog/alu/v6/obj_dir/verilated_vcd_c.o diff --git a/verilog/alu/v6/out b/verilog/alu/v6/out new file mode 100644 index 0000000..0337062 --- /dev/null +++ b/verilog/alu/v6/out @@ -0,0 +1,1200 @@ +SRA: -10 >>A -10 = -1 +00000000000000000000000000000000 +1101 +SRA: -10 >>A -9 = -1 +11111111111111111111111111111111 +1101 +SRA: -10 >>A -8 = -1 +11111111111111111111111111111110 +1101 +SRA: -10 >>A -7 = -1 +11111111111111111111111111111101 +1101 +SRA: -10 >>A -6 = -1 +11111111111111111111111111111100 +1101 +SRA: -10 >>A -5 = -1 +11111111111111111111111111111011 +1101 +SRA: -10 >>A -4 = -1 +11111111111111111111111111111010 +1101 +SRA: -10 >>A -3 = -1 +11111111111111111111111111111001 +1101 +SRA: -10 >>A -2 = -1 +11111111111111111111111111111000 +1101 +SRA: -10 >>A -1 = -1 +11111111111111111111111111110111 +1101 +SRA: -10 >>A 0 = -10 +11111111111111111111111111110110 +1101 +SRA: -10 >>A 1 = -5 +11111111111111111111111111110101 +1101 +SRA: -10 >>A 2 = -3 +11111111111111111111111111110100 +1101 +SRA: -10 >>A 3 = -2 +11111111111111111111111111110011 +1101 +SRA: -10 >>A 4 = -1 +11111111111111111111111111110010 +1101 +SRA: -10 >>A 5 = -1 +11111111111111111111111111110001 +1101 +SRA: -10 >>A 6 = -1 +11111111111111111111111111110000 +1101 +SRA: -10 >>A 7 = -1 +11111111111111111111111111101111 +1101 +SRA: -10 >>A 8 = -1 +11111111111111111111111111101110 +1101 +SRA: -10 >>A 9 = -1 +11111111111111111111111111101101 +1101 +SRA: -9 >>A -10 = -1 +00000000000000000000000000000001 +1101 +SRA: -9 >>A -9 = -1 +00000000000000000000000000000000 +1101 +SRA: -9 >>A -8 = -1 +11111111111111111111111111111111 +1101 +SRA: -9 >>A -7 = -1 +11111111111111111111111111111110 +1101 +SRA: -9 >>A -6 = -1 +11111111111111111111111111111101 +1101 +SRA: -9 >>A -5 = -1 +11111111111111111111111111111100 +1101 +SRA: -9 >>A -4 = -1 +11111111111111111111111111111011 +1101 +SRA: -9 >>A -3 = -1 +11111111111111111111111111111010 +1101 +SRA: -9 >>A -2 = -1 +11111111111111111111111111111001 +1101 +SRA: -9 >>A -1 = -1 +11111111111111111111111111111000 +1101 +SRA: -9 >>A 0 = -9 +11111111111111111111111111110111 +1101 +SRA: -9 >>A 1 = -5 +11111111111111111111111111110110 +1101 +SRA: -9 >>A 2 = -3 +11111111111111111111111111110101 +1101 +SRA: -9 >>A 3 = -2 +11111111111111111111111111110100 +1101 +SRA: -9 >>A 4 = -1 +11111111111111111111111111110011 +1101 +SRA: -9 >>A 5 = -1 +11111111111111111111111111110010 +1101 +SRA: -9 >>A 6 = -1 +11111111111111111111111111110001 +1101 +SRA: -9 >>A 7 = -1 +11111111111111111111111111110000 +1101 +SRA: -9 >>A 8 = -1 +11111111111111111111111111101111 +1101 +SRA: -9 >>A 9 = -1 +11111111111111111111111111101110 +1101 +SRA: -8 >>A -10 = -1 +00000000000000000000000000000010 +1101 +SRA: -8 >>A -9 = -1 +00000000000000000000000000000001 +1101 +SRA: -8 >>A -8 = -1 +00000000000000000000000000000000 +1101 +SRA: -8 >>A -7 = -1 +11111111111111111111111111111111 +1101 +SRA: -8 >>A -6 = -1 +11111111111111111111111111111110 +1101 +SRA: -8 >>A -5 = -1 +11111111111111111111111111111101 +1101 +SRA: -8 >>A -4 = -1 +11111111111111111111111111111100 +1101 +SRA: -8 >>A -3 = -1 +11111111111111111111111111111011 +1101 +SRA: -8 >>A -2 = -1 +11111111111111111111111111111010 +1101 +SRA: -8 >>A -1 = -1 +11111111111111111111111111111001 +1101 +SRA: -8 >>A 0 = -8 +11111111111111111111111111111000 +1101 +SRA: -8 >>A 1 = -4 +11111111111111111111111111110111 +1101 +SRA: -8 >>A 2 = -2 +11111111111111111111111111110110 +1101 +SRA: -8 >>A 3 = -1 +11111111111111111111111111110101 +1101 +SRA: -8 >>A 4 = -1 +11111111111111111111111111110100 +1101 +SRA: -8 >>A 5 = -1 +11111111111111111111111111110011 +1101 +SRA: -8 >>A 6 = -1 +11111111111111111111111111110010 +1101 +SRA: -8 >>A 7 = -1 +11111111111111111111111111110001 +1101 +SRA: -8 >>A 8 = -1 +11111111111111111111111111110000 +1101 +SRA: -8 >>A 9 = -1 +11111111111111111111111111101111 +1101 +SRA: -7 >>A -10 = -1 +00000000000000000000000000000011 +1101 +SRA: -7 >>A -9 = -1 +00000000000000000000000000000010 +1101 +SRA: -7 >>A -8 = -1 +00000000000000000000000000000001 +1101 +SRA: -7 >>A -7 = -1 +00000000000000000000000000000000 +1101 +SRA: -7 >>A -6 = -1 +11111111111111111111111111111111 +1101 +SRA: -7 >>A -5 = -1 +11111111111111111111111111111110 +1101 +SRA: -7 >>A -4 = -1 +11111111111111111111111111111101 +1101 +SRA: -7 >>A -3 = -1 +11111111111111111111111111111100 +1101 +SRA: -7 >>A -2 = -1 +11111111111111111111111111111011 +1101 +SRA: -7 >>A -1 = -1 +11111111111111111111111111111010 +1101 +SRA: -7 >>A 0 = -7 +11111111111111111111111111111001 +1101 +SRA: -7 >>A 1 = -4 +11111111111111111111111111111000 +1101 +SRA: -7 >>A 2 = -2 +11111111111111111111111111110111 +1101 +SRA: -7 >>A 3 = -1 +11111111111111111111111111110110 +1101 +SRA: -7 >>A 4 = -1 +11111111111111111111111111110101 +1101 +SRA: -7 >>A 5 = -1 +11111111111111111111111111110100 +1101 +SRA: -7 >>A 6 = -1 +11111111111111111111111111110011 +1101 +SRA: -7 >>A 7 = -1 +11111111111111111111111111110010 +1101 +SRA: -7 >>A 8 = -1 +11111111111111111111111111110001 +1101 +SRA: -7 >>A 9 = -1 +11111111111111111111111111110000 +1101 +SRA: -6 >>A -10 = -1 +00000000000000000000000000000100 +1101 +SRA: -6 >>A -9 = -1 +00000000000000000000000000000011 +1101 +SRA: -6 >>A -8 = -1 +00000000000000000000000000000010 +1101 +SRA: -6 >>A -7 = -1 +00000000000000000000000000000001 +1101 +SRA: -6 >>A -6 = -1 +00000000000000000000000000000000 +1101 +SRA: -6 >>A -5 = -1 +11111111111111111111111111111111 +1101 +SRA: -6 >>A -4 = -1 +11111111111111111111111111111110 +1101 +SRA: -6 >>A -3 = -1 +11111111111111111111111111111101 +1101 +SRA: -6 >>A -2 = -1 +11111111111111111111111111111100 +1101 +SRA: -6 >>A -1 = -1 +11111111111111111111111111111011 +1101 +SRA: -6 >>A 0 = -6 +11111111111111111111111111111010 +1101 +SRA: -6 >>A 1 = -3 +11111111111111111111111111111001 +1101 +SRA: -6 >>A 2 = -2 +11111111111111111111111111111000 +1101 +SRA: -6 >>A 3 = -1 +11111111111111111111111111110111 +1101 +SRA: -6 >>A 4 = -1 +11111111111111111111111111110110 +1101 +SRA: -6 >>A 5 = -1 +11111111111111111111111111110101 +1101 +SRA: -6 >>A 6 = -1 +11111111111111111111111111110100 +1101 +SRA: -6 >>A 7 = -1 +11111111111111111111111111110011 +1101 +SRA: -6 >>A 8 = -1 +11111111111111111111111111110010 +1101 +SRA: -6 >>A 9 = -1 +11111111111111111111111111110001 +1101 +SRA: -5 >>A -10 = -1 +00000000000000000000000000000101 +1101 +SRA: -5 >>A -9 = -1 +00000000000000000000000000000100 +1101 +SRA: -5 >>A -8 = -1 +00000000000000000000000000000011 +1101 +SRA: -5 >>A -7 = -1 +00000000000000000000000000000010 +1101 +SRA: -5 >>A -6 = -1 +00000000000000000000000000000001 +1101 +SRA: -5 >>A -5 = -1 +00000000000000000000000000000000 +1101 +SRA: -5 >>A -4 = -1 +11111111111111111111111111111111 +1101 +SRA: -5 >>A -3 = -1 +11111111111111111111111111111110 +1101 +SRA: -5 >>A -2 = -1 +11111111111111111111111111111101 +1101 +SRA: -5 >>A -1 = -1 +11111111111111111111111111111100 +1101 +SRA: -5 >>A 0 = -5 +11111111111111111111111111111011 +1101 +SRA: -5 >>A 1 = -3 +11111111111111111111111111111010 +1101 +SRA: -5 >>A 2 = -2 +11111111111111111111111111111001 +1101 +SRA: -5 >>A 3 = -1 +11111111111111111111111111111000 +1101 +SRA: -5 >>A 4 = -1 +11111111111111111111111111110111 +1101 +SRA: -5 >>A 5 = -1 +11111111111111111111111111110110 +1101 +SRA: -5 >>A 6 = -1 +11111111111111111111111111110101 +1101 +SRA: -5 >>A 7 = -1 +11111111111111111111111111110100 +1101 +SRA: -5 >>A 8 = -1 +11111111111111111111111111110011 +1101 +SRA: -5 >>A 9 = -1 +11111111111111111111111111110010 +1101 +SRA: -4 >>A -10 = -1 +00000000000000000000000000000110 +1101 +SRA: -4 >>A -9 = -1 +00000000000000000000000000000101 +1101 +SRA: -4 >>A -8 = -1 +00000000000000000000000000000100 +1101 +SRA: -4 >>A -7 = -1 +00000000000000000000000000000011 +1101 +SRA: -4 >>A -6 = -1 +00000000000000000000000000000010 +1101 +SRA: -4 >>A -5 = -1 +00000000000000000000000000000001 +1101 +SRA: -4 >>A -4 = -1 +00000000000000000000000000000000 +1101 +SRA: -4 >>A -3 = -1 +11111111111111111111111111111111 +1101 +SRA: -4 >>A -2 = -1 +11111111111111111111111111111110 +1101 +SRA: -4 >>A -1 = -1 +11111111111111111111111111111101 +1101 +SRA: -4 >>A 0 = -4 +11111111111111111111111111111100 +1101 +SRA: -4 >>A 1 = -2 +11111111111111111111111111111011 +1101 +SRA: -4 >>A 2 = -1 +11111111111111111111111111111010 +1101 +SRA: -4 >>A 3 = -1 +11111111111111111111111111111001 +1101 +SRA: -4 >>A 4 = -1 +11111111111111111111111111111000 +1101 +SRA: -4 >>A 5 = -1 +11111111111111111111111111110111 +1101 +SRA: -4 >>A 6 = -1 +11111111111111111111111111110110 +1101 +SRA: -4 >>A 7 = -1 +11111111111111111111111111110101 +1101 +SRA: -4 >>A 8 = -1 +11111111111111111111111111110100 +1101 +SRA: -4 >>A 9 = -1 +11111111111111111111111111110011 +1101 +SRA: -3 >>A -10 = -1 +00000000000000000000000000000111 +1101 +SRA: -3 >>A -9 = -1 +00000000000000000000000000000110 +1101 +SRA: -3 >>A -8 = -1 +00000000000000000000000000000101 +1101 +SRA: -3 >>A -7 = -1 +00000000000000000000000000000100 +1101 +SRA: -3 >>A -6 = -1 +00000000000000000000000000000011 +1101 +SRA: -3 >>A -5 = -1 +00000000000000000000000000000010 +1101 +SRA: -3 >>A -4 = -1 +00000000000000000000000000000001 +1101 +SRA: -3 >>A -3 = -1 +00000000000000000000000000000000 +1101 +SRA: -3 >>A -2 = -1 +11111111111111111111111111111111 +1101 +SRA: -3 >>A -1 = -1 +11111111111111111111111111111110 +1101 +SRA: -3 >>A 0 = -3 +11111111111111111111111111111101 +1101 +SRA: -3 >>A 1 = -2 +11111111111111111111111111111100 +1101 +SRA: -3 >>A 2 = -1 +11111111111111111111111111111011 +1101 +SRA: -3 >>A 3 = -1 +11111111111111111111111111111010 +1101 +SRA: -3 >>A 4 = -1 +11111111111111111111111111111001 +1101 +SRA: -3 >>A 5 = -1 +11111111111111111111111111111000 +1101 +SRA: -3 >>A 6 = -1 +11111111111111111111111111110111 +1101 +SRA: -3 >>A 7 = -1 +11111111111111111111111111110110 +1101 +SRA: -3 >>A 8 = -1 +11111111111111111111111111110101 +1101 +SRA: -3 >>A 9 = -1 +11111111111111111111111111110100 +1101 +SRA: -2 >>A -10 = -1 +00000000000000000000000000001000 +1101 +SRA: -2 >>A -9 = -1 +00000000000000000000000000000111 +1101 +SRA: -2 >>A -8 = -1 +00000000000000000000000000000110 +1101 +SRA: -2 >>A -7 = -1 +00000000000000000000000000000101 +1101 +SRA: -2 >>A -6 = -1 +00000000000000000000000000000100 +1101 +SRA: -2 >>A -5 = -1 +00000000000000000000000000000011 +1101 +SRA: -2 >>A -4 = -1 +00000000000000000000000000000010 +1101 +SRA: -2 >>A -3 = -1 +00000000000000000000000000000001 +1101 +SRA: -2 >>A -2 = -1 +00000000000000000000000000000000 +1101 +SRA: -2 >>A -1 = -1 +11111111111111111111111111111111 +1101 +SRA: -2 >>A 0 = -2 +11111111111111111111111111111110 +1101 +SRA: -2 >>A 1 = -1 +11111111111111111111111111111101 +1101 +SRA: -2 >>A 2 = -1 +11111111111111111111111111111100 +1101 +SRA: -2 >>A 3 = -1 +11111111111111111111111111111011 +1101 +SRA: -2 >>A 4 = -1 +11111111111111111111111111111010 +1101 +SRA: -2 >>A 5 = -1 +11111111111111111111111111111001 +1101 +SRA: -2 >>A 6 = -1 +11111111111111111111111111111000 +1101 +SRA: -2 >>A 7 = -1 +11111111111111111111111111110111 +1101 +SRA: -2 >>A 8 = -1 +11111111111111111111111111110110 +1101 +SRA: -2 >>A 9 = -1 +11111111111111111111111111110101 +1101 +SRA: -1 >>A -10 = -1 +00000000000000000000000000001001 +1101 +SRA: -1 >>A -9 = -1 +00000000000000000000000000001000 +1101 +SRA: -1 >>A -8 = -1 +00000000000000000000000000000111 +1101 +SRA: -1 >>A -7 = -1 +00000000000000000000000000000110 +1101 +SRA: -1 >>A -6 = -1 +00000000000000000000000000000101 +1101 +SRA: -1 >>A -5 = -1 +00000000000000000000000000000100 +1101 +SRA: -1 >>A -4 = -1 +00000000000000000000000000000011 +1101 +SRA: -1 >>A -3 = -1 +00000000000000000000000000000010 +1101 +SRA: -1 >>A -2 = -1 +00000000000000000000000000000001 +1101 +SRA: -1 >>A -1 = -1 +00000000000000000000000000000000 +1101 +SRA: -1 >>A 0 = -1 +11111111111111111111111111111111 +1101 +SRA: -1 >>A 1 = -1 +11111111111111111111111111111110 +1101 +SRA: -1 >>A 2 = -1 +11111111111111111111111111111101 +1101 +SRA: -1 >>A 3 = -1 +11111111111111111111111111111100 +1101 +SRA: -1 >>A 4 = -1 +11111111111111111111111111111011 +1101 +SRA: -1 >>A 5 = -1 +11111111111111111111111111111010 +1101 +SRA: -1 >>A 6 = -1 +11111111111111111111111111111001 +1101 +SRA: -1 >>A 7 = -1 +11111111111111111111111111111000 +1101 +SRA: -1 >>A 8 = -1 +11111111111111111111111111110111 +1101 +SRA: -1 >>A 9 = -1 +11111111111111111111111111110110 +1101 +SRA: 0 >>A -10 = -1 +00000000000000000000000000001010 +1101 +SRA: 0 >>A -9 = -1 +00000000000000000000000000001001 +1101 +SRA: 0 >>A -8 = -1 +00000000000000000000000000001000 +1101 +SRA: 0 >>A -7 = -1 +00000000000000000000000000000111 +1101 +SRA: 0 >>A -6 = -1 +00000000000000000000000000000110 +1101 +SRA: 0 >>A -5 = -1 +00000000000000000000000000000101 +1101 +SRA: 0 >>A -4 = -1 +00000000000000000000000000000100 +1101 +SRA: 0 >>A -3 = -1 +00000000000000000000000000000011 +1101 +SRA: 0 >>A -2 = -1 +00000000000000000000000000000010 +1101 +SRA: 0 >>A -1 = -1 +00000000000000000000000000000001 +1101 +SRA: 0 >>A 0 = -2147483648 +00000000000000000000000000000000 +1101 +SRA: 0 >>A 1 = -1073741824 +11111111111111111111111111111111 +1101 +SRA: 0 >>A 2 = -536870912 +11111111111111111111111111111110 +1101 +SRA: 0 >>A 3 = -268435456 +11111111111111111111111111111101 +1101 +SRA: 0 >>A 4 = -134217728 +11111111111111111111111111111100 +1101 +SRA: 0 >>A 5 = -67108864 +11111111111111111111111111111011 +1101 +SRA: 0 >>A 6 = -33554432 +11111111111111111111111111111010 +1101 +SRA: 0 >>A 7 = -16777216 +11111111111111111111111111111001 +1101 +SRA: 0 >>A 8 = -8388608 +11111111111111111111111111111000 +1101 +SRA: 0 >>A 9 = -4194304 +11111111111111111111111111110111 +1101 +SRA: 1 >>A -10 = -1 +00000000000000000000000000001011 +1101 +SRA: 1 >>A -9 = -1 +00000000000000000000000000001010 +1101 +SRA: 1 >>A -8 = -1 +00000000000000000000000000001001 +1101 +SRA: 1 >>A -7 = -1 +00000000000000000000000000001000 +1101 +SRA: 1 >>A -6 = -1 +00000000000000000000000000000111 +1101 +SRA: 1 >>A -5 = -1 +00000000000000000000000000000110 +1101 +SRA: 1 >>A -4 = -1 +00000000000000000000000000000101 +1101 +SRA: 1 >>A -3 = -1 +00000000000000000000000000000100 +1101 +SRA: 1 >>A -2 = -1 +00000000000000000000000000000011 +1101 +SRA: 1 >>A -1 = -1 +00000000000000000000000000000010 +1101 +SRA: 1 >>A 0 = -2147483647 +00000000000000000000000000000001 +1101 +SRA: 1 >>A 1 = -1073741824 +00000000000000000000000000000000 +1101 +SRA: 1 >>A 2 = -536870912 +11111111111111111111111111111111 +1101 +SRA: 1 >>A 3 = -268435456 +11111111111111111111111111111110 +1101 +SRA: 1 >>A 4 = -134217728 +11111111111111111111111111111101 +1101 +SRA: 1 >>A 5 = -67108864 +11111111111111111111111111111100 +1101 +SRA: 1 >>A 6 = -33554432 +11111111111111111111111111111011 +1101 +SRA: 1 >>A 7 = -16777216 +11111111111111111111111111111010 +1101 +SRA: 1 >>A 8 = -8388608 +11111111111111111111111111111001 +1101 +SRA: 1 >>A 9 = -4194304 +11111111111111111111111111111000 +1101 +SRA: 2 >>A -10 = -1 +00000000000000000000000000001100 +1101 +SRA: 2 >>A -9 = -1 +00000000000000000000000000001011 +1101 +SRA: 2 >>A -8 = -1 +00000000000000000000000000001010 +1101 +SRA: 2 >>A -7 = -1 +00000000000000000000000000001001 +1101 +SRA: 2 >>A -6 = -1 +00000000000000000000000000001000 +1101 +SRA: 2 >>A -5 = -1 +00000000000000000000000000000111 +1101 +SRA: 2 >>A -4 = -1 +00000000000000000000000000000110 +1101 +SRA: 2 >>A -3 = -1 +00000000000000000000000000000101 +1101 +SRA: 2 >>A -2 = -1 +00000000000000000000000000000100 +1101 +SRA: 2 >>A -1 = -1 +00000000000000000000000000000011 +1101 +SRA: 2 >>A 0 = -2147483646 +00000000000000000000000000000010 +1101 +SRA: 2 >>A 1 = -1073741823 +00000000000000000000000000000001 +1101 +SRA: 2 >>A 2 = -536870912 +00000000000000000000000000000000 +1101 +SRA: 2 >>A 3 = -268435456 +11111111111111111111111111111111 +1101 +SRA: 2 >>A 4 = -134217728 +11111111111111111111111111111110 +1101 +SRA: 2 >>A 5 = -67108864 +11111111111111111111111111111101 +1101 +SRA: 2 >>A 6 = -33554432 +11111111111111111111111111111100 +1101 +SRA: 2 >>A 7 = -16777216 +11111111111111111111111111111011 +1101 +SRA: 2 >>A 8 = -8388608 +11111111111111111111111111111010 +1101 +SRA: 2 >>A 9 = -4194304 +11111111111111111111111111111001 +1101 +SRA: 3 >>A -10 = -1 +00000000000000000000000000001101 +1101 +SRA: 3 >>A -9 = -1 +00000000000000000000000000001100 +1101 +SRA: 3 >>A -8 = -1 +00000000000000000000000000001011 +1101 +SRA: 3 >>A -7 = -1 +00000000000000000000000000001010 +1101 +SRA: 3 >>A -6 = -1 +00000000000000000000000000001001 +1101 +SRA: 3 >>A -5 = -1 +00000000000000000000000000001000 +1101 +SRA: 3 >>A -4 = -1 +00000000000000000000000000000111 +1101 +SRA: 3 >>A -3 = -1 +00000000000000000000000000000110 +1101 +SRA: 3 >>A -2 = -1 +00000000000000000000000000000101 +1101 +SRA: 3 >>A -1 = -1 +00000000000000000000000000000100 +1101 +SRA: 3 >>A 0 = -2147483645 +00000000000000000000000000000011 +1101 +SRA: 3 >>A 1 = -1073741823 +00000000000000000000000000000010 +1101 +SRA: 3 >>A 2 = -536870912 +00000000000000000000000000000001 +1101 +SRA: 3 >>A 3 = -268435456 +00000000000000000000000000000000 +1101 +SRA: 3 >>A 4 = -134217728 +11111111111111111111111111111111 +1101 +SRA: 3 >>A 5 = -67108864 +11111111111111111111111111111110 +1101 +SRA: 3 >>A 6 = -33554432 +11111111111111111111111111111101 +1101 +SRA: 3 >>A 7 = -16777216 +11111111111111111111111111111100 +1101 +SRA: 3 >>A 8 = -8388608 +11111111111111111111111111111011 +1101 +SRA: 3 >>A 9 = -4194304 +11111111111111111111111111111010 +1101 +SRA: 4 >>A -10 = -1 +00000000000000000000000000001110 +1101 +SRA: 4 >>A -9 = -1 +00000000000000000000000000001101 +1101 +SRA: 4 >>A -8 = -1 +00000000000000000000000000001100 +1101 +SRA: 4 >>A -7 = -1 +00000000000000000000000000001011 +1101 +SRA: 4 >>A -6 = -1 +00000000000000000000000000001010 +1101 +SRA: 4 >>A -5 = -1 +00000000000000000000000000001001 +1101 +SRA: 4 >>A -4 = -1 +00000000000000000000000000001000 +1101 +SRA: 4 >>A -3 = -1 +00000000000000000000000000000111 +1101 +SRA: 4 >>A -2 = -1 +00000000000000000000000000000110 +1101 +SRA: 4 >>A -1 = -1 +00000000000000000000000000000101 +1101 +SRA: 4 >>A 0 = -2147483644 +00000000000000000000000000000100 +1101 +SRA: 4 >>A 1 = -1073741822 +00000000000000000000000000000011 +1101 +SRA: 4 >>A 2 = -536870911 +00000000000000000000000000000010 +1101 +SRA: 4 >>A 3 = -268435456 +00000000000000000000000000000001 +1101 +SRA: 4 >>A 4 = -134217728 +00000000000000000000000000000000 +1101 +SRA: 4 >>A 5 = -67108864 +11111111111111111111111111111111 +1101 +SRA: 4 >>A 6 = -33554432 +11111111111111111111111111111110 +1101 +SRA: 4 >>A 7 = -16777216 +11111111111111111111111111111101 +1101 +SRA: 4 >>A 8 = -8388608 +11111111111111111111111111111100 +1101 +SRA: 4 >>A 9 = -4194304 +11111111111111111111111111111011 +1101 +SRA: 5 >>A -10 = -1 +00000000000000000000000000001111 +1101 +SRA: 5 >>A -9 = -1 +00000000000000000000000000001110 +1101 +SRA: 5 >>A -8 = -1 +00000000000000000000000000001101 +1101 +SRA: 5 >>A -7 = -1 +00000000000000000000000000001100 +1101 +SRA: 5 >>A -6 = -1 +00000000000000000000000000001011 +1101 +SRA: 5 >>A -5 = -1 +00000000000000000000000000001010 +1101 +SRA: 5 >>A -4 = -1 +00000000000000000000000000001001 +1101 +SRA: 5 >>A -3 = -1 +00000000000000000000000000001000 +1101 +SRA: 5 >>A -2 = -1 +00000000000000000000000000000111 +1101 +SRA: 5 >>A -1 = -1 +00000000000000000000000000000110 +1101 +SRA: 5 >>A 0 = -2147483643 +00000000000000000000000000000101 +1101 +SRA: 5 >>A 1 = -1073741822 +00000000000000000000000000000100 +1101 +SRA: 5 >>A 2 = -536870911 +00000000000000000000000000000011 +1101 +SRA: 5 >>A 3 = -268435456 +00000000000000000000000000000010 +1101 +SRA: 5 >>A 4 = -134217728 +00000000000000000000000000000001 +1101 +SRA: 5 >>A 5 = -67108864 +00000000000000000000000000000000 +1101 +SRA: 5 >>A 6 = -33554432 +11111111111111111111111111111111 +1101 +SRA: 5 >>A 7 = -16777216 +11111111111111111111111111111110 +1101 +SRA: 5 >>A 8 = -8388608 +11111111111111111111111111111101 +1101 +SRA: 5 >>A 9 = -4194304 +11111111111111111111111111111100 +1101 +SRA: 6 >>A -10 = -1 +00000000000000000000000000010000 +1101 +SRA: 6 >>A -9 = -1 +00000000000000000000000000001111 +1101 +SRA: 6 >>A -8 = -1 +00000000000000000000000000001110 +1101 +SRA: 6 >>A -7 = -1 +00000000000000000000000000001101 +1101 +SRA: 6 >>A -6 = -1 +00000000000000000000000000001100 +1101 +SRA: 6 >>A -5 = -1 +00000000000000000000000000001011 +1101 +SRA: 6 >>A -4 = -1 +00000000000000000000000000001010 +1101 +SRA: 6 >>A -3 = -1 +00000000000000000000000000001001 +1101 +SRA: 6 >>A -2 = -1 +00000000000000000000000000001000 +1101 +SRA: 6 >>A -1 = -1 +00000000000000000000000000000111 +1101 +SRA: 6 >>A 0 = -2147483642 +00000000000000000000000000000110 +1101 +SRA: 6 >>A 1 = -1073741821 +00000000000000000000000000000101 +1101 +SRA: 6 >>A 2 = -536870911 +00000000000000000000000000000100 +1101 +SRA: 6 >>A 3 = -268435456 +00000000000000000000000000000011 +1101 +SRA: 6 >>A 4 = -134217728 +00000000000000000000000000000010 +1101 +SRA: 6 >>A 5 = -67108864 +00000000000000000000000000000001 +1101 +SRA: 6 >>A 6 = -33554432 +00000000000000000000000000000000 +1101 +SRA: 6 >>A 7 = -16777216 +11111111111111111111111111111111 +1101 +SRA: 6 >>A 8 = -8388608 +11111111111111111111111111111110 +1101 +SRA: 6 >>A 9 = -4194304 +11111111111111111111111111111101 +1101 +SRA: 7 >>A -10 = -1 +00000000000000000000000000010001 +1101 +SRA: 7 >>A -9 = -1 +00000000000000000000000000010000 +1101 +SRA: 7 >>A -8 = -1 +00000000000000000000000000001111 +1101 +SRA: 7 >>A -7 = -1 +00000000000000000000000000001110 +1101 +SRA: 7 >>A -6 = -1 +00000000000000000000000000001101 +1101 +SRA: 7 >>A -5 = -1 +00000000000000000000000000001100 +1101 +SRA: 7 >>A -4 = -1 +00000000000000000000000000001011 +1101 +SRA: 7 >>A -3 = -1 +00000000000000000000000000001010 +1101 +SRA: 7 >>A -2 = -1 +00000000000000000000000000001001 +1101 +SRA: 7 >>A -1 = -1 +00000000000000000000000000001000 +1101 +SRA: 7 >>A 0 = -2147483641 +00000000000000000000000000000111 +1101 +SRA: 7 >>A 1 = -1073741821 +00000000000000000000000000000110 +1101 +SRA: 7 >>A 2 = -536870911 +00000000000000000000000000000101 +1101 +SRA: 7 >>A 3 = -268435456 +00000000000000000000000000000100 +1101 +SRA: 7 >>A 4 = -134217728 +00000000000000000000000000000011 +1101 +SRA: 7 >>A 5 = -67108864 +00000000000000000000000000000010 +1101 +SRA: 7 >>A 6 = -33554432 +00000000000000000000000000000001 +1101 +SRA: 7 >>A 7 = -16777216 +00000000000000000000000000000000 +1101 +SRA: 7 >>A 8 = -8388608 +11111111111111111111111111111111 +1101 +SRA: 7 >>A 9 = -4194304 +11111111111111111111111111111110 +1101 +SRA: 8 >>A -10 = -1 +00000000000000000000000000010010 +1101 +SRA: 8 >>A -9 = -1 +00000000000000000000000000010001 +1101 +SRA: 8 >>A -8 = -1 +00000000000000000000000000010000 +1101 +SRA: 8 >>A -7 = -1 +00000000000000000000000000001111 +1101 +SRA: 8 >>A -6 = -1 +00000000000000000000000000001110 +1101 +SRA: 8 >>A -5 = -1 +00000000000000000000000000001101 +1101 +SRA: 8 >>A -4 = -1 +00000000000000000000000000001100 +1101 +SRA: 8 >>A -3 = -1 +00000000000000000000000000001011 +1101 +SRA: 8 >>A -2 = -1 +00000000000000000000000000001010 +1101 +SRA: 8 >>A -1 = -1 +00000000000000000000000000001001 +1101 +SRA: 8 >>A 0 = -2147483640 +00000000000000000000000000001000 +1101 +SRA: 8 >>A 1 = -1073741820 +00000000000000000000000000000111 +1101 +SRA: 8 >>A 2 = -536870910 +00000000000000000000000000000110 +1101 +SRA: 8 >>A 3 = -268435455 +00000000000000000000000000000101 +1101 +SRA: 8 >>A 4 = -134217728 +00000000000000000000000000000100 +1101 +SRA: 8 >>A 5 = -67108864 +00000000000000000000000000000011 +1101 +SRA: 8 >>A 6 = -33554432 +00000000000000000000000000000010 +1101 +SRA: 8 >>A 7 = -16777216 +00000000000000000000000000000001 +1101 +SRA: 8 >>A 8 = -8388608 +00000000000000000000000000000000 +1101 +SRA: 8 >>A 9 = -4194304 +11111111111111111111111111111111 +1101 +SRA: 9 >>A -10 = -1 +00000000000000000000000000010011 +1101 +SRA: 9 >>A -9 = -1 +00000000000000000000000000010010 +1101 +SRA: 9 >>A -8 = -1 +00000000000000000000000000010001 +1101 +SRA: 9 >>A -7 = -1 +00000000000000000000000000010000 +1101 +SRA: 9 >>A -6 = -1 +00000000000000000000000000001111 +1101 +SRA: 9 >>A -5 = -1 +00000000000000000000000000001110 +1101 +SRA: 9 >>A -4 = -1 +00000000000000000000000000001101 +1101 +SRA: 9 >>A -3 = -1 +00000000000000000000000000001100 +1101 +SRA: 9 >>A -2 = -1 +00000000000000000000000000001011 +1101 +SRA: 9 >>A -1 = -1 +00000000000000000000000000001010 +1101 +SRA: 9 >>A 0 = -2147483639 +00000000000000000000000000001001 +1101 +SRA: 9 >>A 1 = -1073741820 +00000000000000000000000000001000 +1101 +SRA: 9 >>A 2 = -536870910 +00000000000000000000000000000111 +1101 +SRA: 9 >>A 3 = -268435455 +00000000000000000000000000000110 +1101 +SRA: 9 >>A 4 = -134217728 +00000000000000000000000000000101 +1101 +SRA: 9 >>A 5 = -67108864 +00000000000000000000000000000100 +1101 +SRA: 9 >>A 6 = -33554432 +00000000000000000000000000000011 +1101 +SRA: 9 >>A 7 = -16777216 +00000000000000000000000000000010 +1101 +SRA: 9 >>A 8 = -8388608 +00000000000000000000000000000001 +1101 +SRA: 9 >>A 9 = -4194304 +00000000000000000000000000000000 +1101 diff --git a/verilog/alu/v6/shifter.v b/verilog/alu/v6/shifter.v new file mode 100644 index 0000000..7030a1c --- /dev/null +++ b/verilog/alu/v6/shifter.v @@ -0,0 +1,42 @@ +`default_nettype none +`timescale 1us/1ns + +module rightshifter +( + input wire [31:0] shift, + input wire [31:0] number, + output wire [31:0] shifted +); + +always @ (*) +begin + if (number[5] == 1'b1) + begin + shifted = {32{number[31]}}; + end + else + begin + if (number[4] == 1'b1) + begin + shifted = {{16{number[31]}}, number[31:16]} + end + if (number[3] == 1'b1) + begin + shifted = {{8{number[31]}}, number[31:8]} + end + if (number[2] == 1'b1) + begin + shifted = {{4{number[31]}}, number[31:4]} + end + if (number[1] == 1'b1) + begin + shifted = {{2{number[31]}}, number[31:2]} + end + if (number[0] == 1'b1) + begin + shifted = {number[31], number[31:1]} + end + end +end + +endmodule diff --git a/verilog/alu/v6/synth_alu6.v b/verilog/alu/v6/synth_alu6.v new file mode 100644 index 0000000..ba1f4ed --- /dev/null +++ b/verilog/alu/v6/synth_alu6.v @@ -0,0 +1,17083 @@ +/* Generated by Yosys 0.15+70 (git sha1 48d7a6c47, gcc 11.2.0 -march=x86-64 -mtune=generic -O2 -fno-plt -fexceptions -fstack-clash-protection -fcf-protection -fPIC -Os) */ + +module alu6(\alu_in_1[0] , \alu_in_1[1] , \alu_in_1[2] , \alu_in_1[3] , \alu_in_1[4] , \alu_in_1[5] , \alu_in_1[6] , \alu_in_1[7] , \alu_in_1[8] , \alu_in_1[9] , \alu_in_1[10] , \alu_in_1[11] , \alu_in_1[12] , \alu_in_1[13] , \alu_in_1[14] , \alu_in_1[15] , \alu_in_1[16] , \alu_in_1[17] , \alu_in_1[18] , \alu_in_1[19] , \alu_in_1[20] +, \alu_in_1[21] , \alu_in_1[22] , \alu_in_1[23] , \alu_in_1[24] , \alu_in_1[25] , \alu_in_1[26] , \alu_in_1[27] , \alu_in_1[28] , \alu_in_1[29] , \alu_in_1[30] , \alu_in_1[31] , \alu_in_2[0] , \alu_in_2[1] , \alu_in_2[2] , \alu_in_2[3] , \alu_in_2[4] , \alu_in_2[5] , \alu_in_2[6] , \alu_in_2[7] , \alu_in_2[8] , \alu_in_2[9] +, \alu_in_2[10] , \alu_in_2[11] , \alu_in_2[12] , \alu_in_2[13] , \alu_in_2[14] , \alu_in_2[15] , \alu_in_2[16] , \alu_in_2[17] , \alu_in_2[18] , \alu_in_2[19] , \alu_in_2[20] , \alu_in_2[21] , \alu_in_2[22] , \alu_in_2[23] , \alu_in_2[24] , \alu_in_2[25] , \alu_in_2[26] , \alu_in_2[27] , \alu_in_2[28] , \alu_in_2[29] , \alu_in_2[30] +, \alu_in_2[31] , \alu_op_i[0] , \alu_op_i[1] , \alu_op_i[2] , \alu_op_i[3] , \alu_output[0] , \alu_output[1] , \alu_output[2] , \alu_output[3] , \alu_output[4] , \alu_output[5] , \alu_output[6] , \alu_output[7] , \alu_output[8] , \alu_output[9] , \alu_output[10] , \alu_output[11] , \alu_output[12] , \alu_output[13] , \alu_output[14] , \alu_output[15] +, \alu_output[16] , \alu_output[17] , \alu_output[18] , \alu_output[19] , \alu_output[20] , \alu_output[21] , \alu_output[22] , \alu_output[23] , \alu_output[24] , \alu_output[25] , \alu_output[26] , \alu_output[27] , \alu_output[28] , \alu_output[29] , \alu_output[30] , \alu_output[31] ); + wire _0000_; + wire _0001_; + wire _0002_; + input \alu_in_1[0] ; + wire \alu_in_1[0] ; + input \alu_in_1[10] ; + wire \alu_in_1[10] ; + input \alu_in_1[11] ; + wire \alu_in_1[11] ; + input \alu_in_1[12] ; + wire \alu_in_1[12] ; + input \alu_in_1[13] ; + wire \alu_in_1[13] ; + input \alu_in_1[14] ; + wire \alu_in_1[14] ; + input \alu_in_1[15] ; + wire \alu_in_1[15] ; + input \alu_in_1[16] ; + wire \alu_in_1[16] ; + input \alu_in_1[17] ; + wire \alu_in_1[17] ; + input \alu_in_1[18] ; + wire \alu_in_1[18] ; + input \alu_in_1[19] ; + wire \alu_in_1[19] ; + input \alu_in_1[1] ; + wire \alu_in_1[1] ; + input \alu_in_1[20] ; + wire \alu_in_1[20] ; + input \alu_in_1[21] ; + wire \alu_in_1[21] ; + input \alu_in_1[22] ; + wire \alu_in_1[22] ; + input \alu_in_1[23] ; + wire \alu_in_1[23] ; + input \alu_in_1[24] ; + wire \alu_in_1[24] ; + input \alu_in_1[25] ; + wire \alu_in_1[25] ; + input \alu_in_1[26] ; + wire \alu_in_1[26] ; + input \alu_in_1[27] ; + wire \alu_in_1[27] ; + input \alu_in_1[28] ; + wire \alu_in_1[28] ; + input \alu_in_1[29] ; + wire \alu_in_1[29] ; + input \alu_in_1[2] ; + wire \alu_in_1[2] ; + input \alu_in_1[30] ; + wire \alu_in_1[30] ; + input \alu_in_1[31] ; + wire \alu_in_1[31] ; + input \alu_in_1[3] ; + wire \alu_in_1[3] ; + input \alu_in_1[4] ; + wire \alu_in_1[4] ; + input \alu_in_1[5] ; + wire \alu_in_1[5] ; + input \alu_in_1[6] ; + wire \alu_in_1[6] ; + input \alu_in_1[7] ; + wire \alu_in_1[7] ; + input \alu_in_1[8] ; + wire \alu_in_1[8] ; + input \alu_in_1[9] ; + wire \alu_in_1[9] ; + input \alu_in_2[0] ; + wire \alu_in_2[0] ; + input \alu_in_2[10] ; + wire \alu_in_2[10] ; + input \alu_in_2[11] ; + wire \alu_in_2[11] ; + input \alu_in_2[12] ; + wire \alu_in_2[12] ; + input \alu_in_2[13] ; + wire \alu_in_2[13] ; + input \alu_in_2[14] ; + wire \alu_in_2[14] ; + input \alu_in_2[15] ; + wire \alu_in_2[15] ; + input \alu_in_2[16] ; + wire \alu_in_2[16] ; + input \alu_in_2[17] ; + wire \alu_in_2[17] ; + input \alu_in_2[18] ; + wire \alu_in_2[18] ; + input \alu_in_2[19] ; + wire \alu_in_2[19] ; + input \alu_in_2[1] ; + wire \alu_in_2[1] ; + input \alu_in_2[20] ; + wire \alu_in_2[20] ; + input \alu_in_2[21] ; + wire \alu_in_2[21] ; + input \alu_in_2[22] ; + wire \alu_in_2[22] ; + input \alu_in_2[23] ; + wire \alu_in_2[23] ; + input \alu_in_2[24] ; + wire \alu_in_2[24] ; + input \alu_in_2[25] ; + wire \alu_in_2[25] ; + input \alu_in_2[26] ; + wire \alu_in_2[26] ; + input \alu_in_2[27] ; + wire \alu_in_2[27] ; + input \alu_in_2[28] ; + wire \alu_in_2[28] ; + input \alu_in_2[29] ; + wire \alu_in_2[29] ; + input \alu_in_2[2] ; + wire \alu_in_2[2] ; + input \alu_in_2[30] ; + wire \alu_in_2[30] ; + input \alu_in_2[31] ; + wire \alu_in_2[31] ; + input \alu_in_2[3] ; + wire \alu_in_2[3] ; + input \alu_in_2[4] ; + wire \alu_in_2[4] ; + input \alu_in_2[5] ; + wire \alu_in_2[5] ; + input \alu_in_2[6] ; + wire \alu_in_2[6] ; + input \alu_in_2[7] ; + wire \alu_in_2[7] ; + input \alu_in_2[8] ; + wire \alu_in_2[8] ; + input \alu_in_2[9] ; + wire \alu_in_2[9] ; + input \alu_op_i[0] ; + wire \alu_op_i[0] ; + input \alu_op_i[1] ; + wire \alu_op_i[1] ; + input \alu_op_i[2] ; + wire \alu_op_i[2] ; + input \alu_op_i[3] ; + wire \alu_op_i[3] ; + output \alu_output[0] ; + wire \alu_output[0] ; + output \alu_output[10] ; + wire \alu_output[10] ; + output \alu_output[11] ; + wire \alu_output[11] ; + output \alu_output[12] ; + wire \alu_output[12] ; + output \alu_output[13] ; + wire \alu_output[13] ; + output \alu_output[14] ; + wire \alu_output[14] ; + output \alu_output[15] ; + wire \alu_output[15] ; + output \alu_output[16] ; + wire \alu_output[16] ; + output \alu_output[17] ; + wire \alu_output[17] ; + output \alu_output[18] ; + wire \alu_output[18] ; + output \alu_output[19] ; + wire \alu_output[19] ; + output \alu_output[1] ; + wire \alu_output[1] ; + output \alu_output[20] ; + wire \alu_output[20] ; + output \alu_output[21] ; + wire \alu_output[21] ; + output \alu_output[22] ; + wire \alu_output[22] ; + output \alu_output[23] ; + wire \alu_output[23] ; + output \alu_output[24] ; + wire \alu_output[24] ; + output \alu_output[25] ; + wire \alu_output[25] ; + output \alu_output[26] ; + wire \alu_output[26] ; + output \alu_output[27] ; + wire \alu_output[27] ; + output \alu_output[28] ; + wire \alu_output[28] ; + output \alu_output[29] ; + wire \alu_output[29] ; + output \alu_output[2] ; + wire \alu_output[2] ; + output \alu_output[30] ; + wire \alu_output[30] ; + output \alu_output[31] ; + wire \alu_output[31] ; + output \alu_output[3] ; + wire \alu_output[3] ; + output \alu_output[4] ; + wire \alu_output[4] ; + output \alu_output[5] ; + wire \alu_output[5] ; + output \alu_output[6] ; + wire \alu_output[6] ; + output \alu_output[7] ; + wire \alu_output[7] ; + output \alu_output[8] ; + wire \alu_output[8] ; + output \alu_output[9] ; + wire \alu_output[9] ; + wire alu_output_L6MUX21_Z_1_D0; + wire alu_output_L6MUX21_Z_1_D0_PFUMX_Z_ALUT; + wire alu_output_L6MUX21_Z_1_D0_PFUMX_Z_BLUT; + wire alu_output_L6MUX21_Z_1_D1; + wire alu_output_L6MUX21_Z_1_D1_PFUMX_Z_ALUT; + wire alu_output_L6MUX21_Z_1_D1_PFUMX_Z_BLUT; + wire alu_output_L6MUX21_Z_2_D0; + wire alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D0; + wire alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D1; + wire alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_L6MUX21_Z_2_D1; + wire alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D0; + wire alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D1; + wire alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_L6MUX21_Z_3_D0; + wire alu_output_L6MUX21_Z_3_D0_PFUMX_Z_ALUT; + wire alu_output_L6MUX21_Z_3_D0_PFUMX_Z_BLUT; + wire alu_output_L6MUX21_Z_3_D1; + wire alu_output_L6MUX21_Z_3_D1_PFUMX_Z_ALUT; + wire alu_output_L6MUX21_Z_3_D1_PFUMX_Z_BLUT; + wire alu_output_L6MUX21_Z_D0; + wire alu_output_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_L6MUX21_Z_D1; + wire alu_output_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_10_B[0] ; + wire \alu_output_LUT4_Z_10_B[1] ; + wire \alu_output_LUT4_Z_10_B[2] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B[0] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B[1] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B[2] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B[3] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[0] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[1] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[3] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[4] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z_LUT4_Z_1_C[0] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z_LUT4_Z_1_C[1] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z_LUT4_Z_1_C[2] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z_LUT4_Z_1_C[3] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[0] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[1] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[2] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[4] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[5] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_LUT4_Z_1_C[0] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_LUT4_Z_1_C[1] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_LUT4_Z_1_C[2] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_LUT4_Z_1_C[3] ; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_PFUMX_Z_1_ALUT; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_PFUMX_Z_1_BLUT; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A[0] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A[1] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A[2] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A[3] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A[4] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A[5] ; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_ALUT; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[0] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[1] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[2] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[3] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[5] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[6] ; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[0] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[1] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[2] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[3] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] ; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_2_A[0] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_2_A[1] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_2_A[2] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_2_A[3] ; + wire alu_output_LUT4_Z_10_B_LUT4_Z_2_A_PFUMX_Z_1_ALUT; + wire alu_output_LUT4_Z_10_B_LUT4_Z_2_A_PFUMX_Z_1_BLUT; + wire alu_output_LUT4_Z_10_B_LUT4_Z_2_A_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_10_B_LUT4_Z_2_A_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_C[0] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_C[1] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_C[2] ; + wire \alu_output_LUT4_Z_10_B_LUT4_Z_C[3] ; + wire \alu_output_LUT4_Z_11_C[0] ; + wire \alu_output_LUT4_Z_11_C[1] ; + wire \alu_output_LUT4_Z_11_C[2] ; + wire \alu_output_LUT4_Z_11_C[3] ; + wire \alu_output_LUT4_Z_11_C_LUT4_Z_C[0] ; + wire \alu_output_LUT4_Z_11_C_LUT4_Z_C[1] ; + wire \alu_output_LUT4_Z_11_C_LUT4_Z_C[2] ; + wire \alu_output_LUT4_Z_11_C_LUT4_Z_C[3] ; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A[0] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A[1] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A[2] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A[3] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A[4] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B[0] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B[1] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B[2] ; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[0] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[1] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[2] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[3] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[4] ; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_1_Z; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A[0] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A[1] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A[2] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A[3] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A[4] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A[5] ; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_BLUT; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_D0; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_D0_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[1] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[2] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[3] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[4] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_1_D[0] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_1_D[1] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_1_D[2] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_1_D[3] ; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[0] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[1] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[2] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[3] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[4] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[5] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[0] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[1] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[2] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[3] ; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_LUT4_Z_1_D[0] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_LUT4_Z_1_D[1] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_LUT4_Z_1_D[2] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_LUT4_Z_1_D[3] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_C[0] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_C[1] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_C[2] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_C[3] ; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z_D[0] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z_D[1] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z_D[2] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z_D[3] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z_D[4] ; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_1_ALUT; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_1_BLUT; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B[0] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B[1] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B[2] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B[3] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B[4] ; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z[0] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z[1] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z[2] ; + wire \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z[3] ; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_11_C_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_12_C[0] ; + wire \alu_output_LUT4_Z_12_C[1] ; + wire \alu_output_LUT4_Z_12_C[2] ; + wire \alu_output_LUT4_Z_12_C[3] ; + wire alu_output_LUT4_Z_12_C_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_12_C_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_12_C_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_12_C_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_12_C_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_12_C_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_12_C_LUT4_Z_C[0] ; + wire \alu_output_LUT4_Z_12_C_LUT4_Z_C[1] ; + wire \alu_output_LUT4_Z_12_C_LUT4_Z_C[2] ; + wire \alu_output_LUT4_Z_12_C_LUT4_Z_C[3] ; + wire \alu_output_LUT4_Z_1_B[0] ; + wire \alu_output_LUT4_Z_1_B[1] ; + wire \alu_output_LUT4_Z_1_B[2] ; + wire alu_output_LUT4_Z_1_B_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_1_B_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_1_B_LUT4_Z_1_A[0] ; + wire \alu_output_LUT4_Z_1_B_LUT4_Z_1_A[1] ; + wire \alu_output_LUT4_Z_1_B_LUT4_Z_1_A[2] ; + wire \alu_output_LUT4_Z_1_B_LUT4_Z_1_A[3] ; + wire \alu_output_LUT4_Z_1_B_LUT4_Z_1_A[4] ; + wire \alu_output_LUT4_Z_1_B_LUT4_Z_1_A[5] ; + wire alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D0; + wire alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D1; + wire alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D0; + wire alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D1; + wire alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D0; + wire alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D1; + wire alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_1_B_LUT4_Z_C[0] ; + wire \alu_output_LUT4_Z_1_B_LUT4_Z_C[1] ; + wire \alu_output_LUT4_Z_1_B_LUT4_Z_C[2] ; + wire \alu_output_LUT4_Z_1_B_LUT4_Z_C[3] ; + wire \alu_output_LUT4_Z_2_A[0] ; + wire \alu_output_LUT4_Z_2_A[1] ; + wire \alu_output_LUT4_Z_2_A[2] ; + wire \alu_output_LUT4_Z_2_A[3] ; + wire alu_output_LUT4_Z_2_A_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_2_A_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_2_A_PFUMX_Z_1_ALUT; + wire alu_output_LUT4_Z_2_A_PFUMX_Z_1_BLUT; + wire alu_output_LUT4_Z_2_A_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_2_A_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_3_C[0] ; + wire \alu_output_LUT4_Z_3_C[1] ; + wire \alu_output_LUT4_Z_3_C[2] ; + wire \alu_output_LUT4_Z_3_C[3] ; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[0] ; + wire \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] ; + wire \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[2] ; + wire \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] ; + wire \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[4] ; + wire \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[5] ; + wire \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[6] ; + wire \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A[0] ; + wire \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A[1] ; + wire \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A[2] ; + wire \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A[3] ; + wire \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A[4] ; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D0; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D1; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[0] ; + wire \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[1] ; + wire \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[2] ; + wire \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[3] ; + wire \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[4] ; + wire \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[5] ; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D0; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D1; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_B_Z[0] ; + wire \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_B_Z[1] ; + wire \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[0] ; + wire \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[1] ; + wire \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] ; + wire \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[3] ; + wire \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[4] ; + wire \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[5] ; + wire \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z_LUT4_Z_1_A[0] ; + wire \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z_LUT4_Z_1_A[1] ; + wire \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z_LUT4_Z_1_A[2] ; + wire \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z_LUT4_Z_1_A[3] ; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_3_C_LUT4_Z_A[0] ; + wire \alu_output_LUT4_Z_3_C_LUT4_Z_A[1] ; + wire \alu_output_LUT4_Z_3_C_LUT4_Z_A[2] ; + wire \alu_output_LUT4_Z_3_C_LUT4_Z_A[3] ; + wire \alu_output_LUT4_Z_3_C_LUT4_Z_A[4] ; + wire alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z; + wire alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_BLUT; + wire \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[0] ; + wire \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[1] ; + wire \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[2] ; + wire \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[3] ; + wire \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[4] ; + wire \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[0] ; + wire \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[1] ; + wire \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[2] ; + wire \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[3] ; + wire \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A[0] ; + wire \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A[1] ; + wire \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A[2] ; + wire \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A[3] ; + wire alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0; + wire alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1; + wire alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[0] ; + wire \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] ; + wire \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[2] ; + wire \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[3] ; + wire \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] ; + wire alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_3_C_LUT4_Z_A_PFUMX_Z_1_ALUT; + wire alu_output_LUT4_Z_3_C_LUT4_Z_A_PFUMX_Z_1_BLUT; + wire alu_output_LUT4_Z_3_C_LUT4_Z_A_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_3_C_LUT4_Z_A_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_3_C_LUT4_Z_C[0] ; + wire \alu_output_LUT4_Z_3_C_LUT4_Z_C[1] ; + wire \alu_output_LUT4_Z_3_C_LUT4_Z_C[2] ; + wire \alu_output_LUT4_Z_3_C_LUT4_Z_C[3] ; + wire \alu_output_LUT4_Z_4_C[0] ; + wire \alu_output_LUT4_Z_4_C[1] ; + wire \alu_output_LUT4_Z_4_C[2] ; + wire \alu_output_LUT4_Z_4_C[3] ; + wire alu_output_LUT4_Z_4_C_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_4_C_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_4_C_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_4_C_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_4_C_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_4_C_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_4_C_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_4_C_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_4_C_PFUMX_Z_C0[0] ; + wire \alu_output_LUT4_Z_4_C_PFUMX_Z_C0[1] ; + wire \alu_output_LUT4_Z_4_C_PFUMX_Z_C0[2] ; + wire \alu_output_LUT4_Z_4_C_PFUMX_Z_C0[3] ; + wire \alu_output_LUT4_Z_4_C_PFUMX_Z_C0[4] ; + wire \alu_output_LUT4_Z_5_B[0] ; + wire \alu_output_LUT4_Z_5_B[1] ; + wire \alu_output_LUT4_Z_5_B[2] ; + wire \alu_output_LUT4_Z_5_B_LUT4_Z_A[0] ; + wire \alu_output_LUT4_Z_5_B_LUT4_Z_A[1] ; + wire \alu_output_LUT4_Z_5_B_LUT4_Z_A[2] ; + wire \alu_output_LUT4_Z_5_B_LUT4_Z_A[3] ; + wire \alu_output_LUT4_Z_5_B_LUT4_Z_A[4] ; + wire \alu_output_LUT4_Z_5_B_LUT4_Z_A[5] ; + wire alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B[0] ; + wire \alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B[1] ; + wire \alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B[2] ; + wire alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z[0] ; + wire \alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z[1] ; + wire \alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z[2] ; + wire \alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z[3] ; + wire \alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z[4] ; + wire alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B[0] ; + wire \alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B[1] ; + wire \alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B[2] ; + wire \alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B[3] ; + wire \alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B[4] ; + wire alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_5_B_LUT4_Z_C[0] ; + wire \alu_output_LUT4_Z_5_B_LUT4_Z_C[1] ; + wire \alu_output_LUT4_Z_5_B_LUT4_Z_C[2] ; + wire \alu_output_LUT4_Z_5_B_LUT4_Z_C[3] ; + wire \alu_output_LUT4_Z_5_B_LUT4_Z_C_LUT4_Z_1_B[0] ; + wire \alu_output_LUT4_Z_5_B_LUT4_Z_C_LUT4_Z_1_B[1] ; + wire \alu_output_LUT4_Z_5_B_LUT4_Z_C_LUT4_Z_1_B[2] ; + wire alu_output_LUT4_Z_5_B_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_5_B_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_6_A[0] ; + wire \alu_output_LUT4_Z_6_A[1] ; + wire \alu_output_LUT4_Z_6_A[2] ; + wire \alu_output_LUT4_Z_6_A[3] ; + wire alu_output_LUT4_Z_6_A_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_6_A_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_6_A_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_6_A_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] ; + wire \alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] ; + wire \alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[2] ; + wire \alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] ; + wire \alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[4] ; + wire \alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[5] ; + wire \alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B[0] ; + wire \alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B[1] ; + wire \alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B[2] ; + wire alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[0] ; + wire \alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[1] ; + wire \alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[2] ; + wire alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[0] ; + wire \alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[1] ; + wire \alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[2] ; + wire \alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[3] ; + wire \alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[4] ; + wire alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_6_A_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_6_A_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_7_A[0] ; + wire \alu_output_LUT4_Z_7_A[1] ; + wire \alu_output_LUT4_Z_7_A[2] ; + wire \alu_output_LUT4_Z_7_A[3] ; + wire \alu_output_LUT4_Z_7_A_LUT4_Z_A[0] ; + wire \alu_output_LUT4_Z_7_A_LUT4_Z_A[1] ; + wire \alu_output_LUT4_Z_7_A_LUT4_Z_A[2] ; + wire \alu_output_LUT4_Z_7_A_LUT4_Z_A[3] ; + wire alu_output_LUT4_Z_7_A_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_7_A_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_8_A[0] ; + wire \alu_output_LUT4_Z_8_A[1] ; + wire \alu_output_LUT4_Z_8_A[2] ; + wire \alu_output_LUT4_Z_8_A[3] ; + wire \alu_output_LUT4_Z_8_A_LUT4_Z_1_A[0] ; + wire \alu_output_LUT4_Z_8_A_LUT4_Z_1_A[1] ; + wire \alu_output_LUT4_Z_8_A_LUT4_Z_1_A[2] ; + wire \alu_output_LUT4_Z_8_A_LUT4_Z_1_A[3] ; + wire \alu_output_LUT4_Z_8_A_LUT4_Z_1_C[0] ; + wire \alu_output_LUT4_Z_8_A_LUT4_Z_1_C[1] ; + wire \alu_output_LUT4_Z_8_A_LUT4_Z_1_C[2] ; + wire \alu_output_LUT4_Z_8_A_LUT4_Z_1_C[3] ; + wire \alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] ; + wire alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D0; + wire alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D1; + wire alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_8_A_LUT4_Z_C[0] ; + wire \alu_output_LUT4_Z_8_A_LUT4_Z_C[1] ; + wire \alu_output_LUT4_Z_8_A_LUT4_Z_C[2] ; + wire \alu_output_LUT4_Z_8_A_LUT4_Z_C[3] ; + wire \alu_output_LUT4_Z_9_B[0] ; + wire \alu_output_LUT4_Z_9_B[1] ; + wire \alu_output_LUT4_Z_9_B[2] ; + wire alu_output_LUT4_Z_9_B_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_9_B_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_9_B_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_9_B_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] ; + wire \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] ; + wire \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[2] ; + wire \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] ; + wire \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[4] ; + wire \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[5] ; + wire \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[0] ; + wire \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[1] ; + wire \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[2] ; + wire \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[3] ; + wire \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[4] ; + wire \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[5] ; + wire \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[6] ; + wire \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A[0] ; + wire \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A[1] ; + wire \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A[2] ; + wire \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A[3] ; + wire alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_BLUT_LUT4_Z_D[0] ; + wire \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_BLUT_LUT4_Z_D[1] ; + wire \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_BLUT_LUT4_Z_D[2] ; + wire \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_BLUT_LUT4_Z_D[3] ; + wire \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_BLUT_LUT4_Z_D[4] ; + wire \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_C[0] ; + wire \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_C[1] ; + wire \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_C[2] ; + wire \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_C[3] ; + wire alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_Z_1_ALUT; + wire alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_Z_1_BLUT; + wire alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[0] ; + wire \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[1] ; + wire \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[2] ; + wire alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D0; + wire alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D1; + wire alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_9_B_LUT4_Z_1_B[0] ; + wire \alu_output_LUT4_Z_9_B_LUT4_Z_1_B[1] ; + wire \alu_output_LUT4_Z_9_B_LUT4_Z_1_B[2] ; + wire \alu_output_LUT4_Z_9_B_LUT4_Z_1_B[3] ; + wire \alu_output_LUT4_Z_9_B_LUT4_Z_1_B[4] ; + wire \alu_output_LUT4_Z_9_B_LUT4_Z_1_B[5] ; + wire alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_1_D0; + wire alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_1_D1; + wire alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_2_D0; + wire alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_2_D1; + wire alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_2_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_2_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_9_B_LUT4_Z_1_C[0] ; + wire \alu_output_LUT4_Z_9_B_LUT4_Z_1_C[1] ; + wire \alu_output_LUT4_Z_9_B_LUT4_Z_1_C[2] ; + wire \alu_output_LUT4_Z_9_B_LUT4_Z_1_C[3] ; + wire alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_9_B_LUT4_Z_C[0] ; + wire \alu_output_LUT4_Z_9_B_LUT4_Z_C[1] ; + wire \alu_output_LUT4_Z_9_B_LUT4_Z_C[2] ; + wire \alu_output_LUT4_Z_9_B_LUT4_Z_C[3] ; + wire \alu_output_LUT4_Z_A[0] ; + wire \alu_output_LUT4_Z_A[1] ; + wire \alu_output_LUT4_Z_A[2] ; + wire \alu_output_LUT4_Z_A[3] ; + wire alu_output_LUT4_Z_A_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_A_L6MUX21_Z_SD[0] ; + wire \alu_output_LUT4_Z_A_L6MUX21_Z_SD[1] ; + wire \alu_output_LUT4_Z_A_L6MUX21_Z_SD[2] ; + wire \alu_output_LUT4_Z_A_L6MUX21_Z_SD[3] ; + wire \alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] ; + wire alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[0] ; + wire \alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[1] ; + wire \alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[2] ; + wire \alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[3] ; + wire \alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[4] ; + wire \alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B[0] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B[1] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B[2] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B[3] ; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[0] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[1] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[2] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[4] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[5] ; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_1_Z; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_1_Z_PFUMX_BLUT_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[1] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[2] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[3] ; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[0] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[1] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[2] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[3] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[4] ; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D0; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D1; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[2] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[3] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[4] ; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B[0] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B[1] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B[2] ; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_1_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_1_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B[0] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B[1] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B[2] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B[3] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B[4] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[0] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[10] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[11] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[12] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[13] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[14] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[15] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[16] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[17] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[18] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[19] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[1] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[20] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[21] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[22] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[23] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[24] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[25] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[26] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[27] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[28] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[29] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[2] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[30] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[31] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[3] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[4] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[5] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[6] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[7] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[8] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[9] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[0] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[10] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[12] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[14] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[16] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[18] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[20] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[22] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[24] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[26] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[28] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[2] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[30] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[4] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[6] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[8] ; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[0] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[2] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[4] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[5] ; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_1_Z; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[0] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[1] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[2] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[3] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[5] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[6] ; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[0] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[1] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[3] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[4] ; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0[0] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0[1] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0[2] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0[3] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0[4] ; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_C[0] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_C[1] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_C[2] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_C[3] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_C[5] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_1_C[6] ; + wire alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D0; + wire alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D1; + wire alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_A_LUT4_Z_A[0] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_A[1] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_A[2] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_A[3] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[0] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[1] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[2] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[3] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[4] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[5] ; + wire alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D0; + wire alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D1; + wire alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D0; + wire alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D1; + wire alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D0; + wire alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D1; + wire alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_PFUMX_Z_ALUT; + wire alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_PFUMX_Z_BLUT; + wire \alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[0] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[1] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[3] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[4] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_D[0] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_D[1] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_D[2] ; + wire \alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_D[3] ; + wire alu_output_PFUMX_Z_10_ALUT; + wire alu_output_PFUMX_Z_10_BLUT; + wire \alu_output_PFUMX_Z_10_C0[0] ; + wire \alu_output_PFUMX_Z_10_C0[1] ; + wire \alu_output_PFUMX_Z_10_C0[2] ; + wire \alu_output_PFUMX_Z_10_C0[3] ; + wire \alu_output_PFUMX_Z_10_C0[4] ; + wire \alu_output_PFUMX_Z_10_C0_LUT4_Z_1_A[0] ; + wire \alu_output_PFUMX_Z_10_C0_LUT4_Z_1_A[1] ; + wire \alu_output_PFUMX_Z_10_C0_LUT4_Z_1_A[2] ; + wire \alu_output_PFUMX_Z_10_C0_LUT4_Z_1_A[3] ; + wire \alu_output_PFUMX_Z_10_C0_LUT4_Z_C[0] ; + wire \alu_output_PFUMX_Z_10_C0_LUT4_Z_C[1] ; + wire \alu_output_PFUMX_Z_10_C0_LUT4_Z_C[2] ; + wire \alu_output_PFUMX_Z_10_C0_LUT4_Z_C[3] ; + wire alu_output_PFUMX_Z_10_C0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_10_C0_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_11_ALUT; + wire alu_output_PFUMX_Z_11_BLUT; + wire alu_output_PFUMX_Z_12_ALUT; + wire alu_output_PFUMX_Z_12_BLUT; + wire \alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D[0] ; + wire \alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D[1] ; + wire \alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D[2] ; + wire \alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D[3] ; + wire \alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D[4] ; + wire alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D_PFUMX_Z_1_ALUT; + wire alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D_PFUMX_Z_1_BLUT; + wire alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_13_ALUT; + wire alu_output_PFUMX_Z_13_BLUT; + wire alu_output_PFUMX_Z_14_ALUT; + wire alu_output_PFUMX_Z_14_BLUT; + wire alu_output_PFUMX_Z_1_ALUT; + wire alu_output_PFUMX_Z_1_BLUT; + wire \alu_output_PFUMX_Z_1_C0[0] ; + wire \alu_output_PFUMX_Z_1_C0[1] ; + wire \alu_output_PFUMX_Z_1_C0[2] ; + wire \alu_output_PFUMX_Z_1_C0[3] ; + wire \alu_output_PFUMX_Z_1_C0[4] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C[0] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C[1] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C[2] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C[3] ; + wire alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[0] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[1] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[2] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[3] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[4] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[5] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[6] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_B[0] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_B[1] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_B[2] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_B[3] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_B[4] ; + wire alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_BLUT; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A[0] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A[1] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A[2] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z[0] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z[1] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z[2] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z[3] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z[4] ; + wire alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z_PFUMX_Z_BLUT; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[0] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[1] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[2] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[3] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[4] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[5] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[6] ; + wire alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A_LUT4_D_1_Z; + wire alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A_LUT4_D_Z; + wire alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A_LUT4_D_Z_PFUMX_ALUT_Z; + wire alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_A[0] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_A[1] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_C[0] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_C[1] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_C[2] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_C[3] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_C_LUT4_Z_D[0] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_C_LUT4_Z_D[1] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_C_LUT4_Z_D[2] ; + wire \alu_output_PFUMX_Z_1_C0_LUT4_Z_C_LUT4_Z_D[3] ; + wire alu_output_PFUMX_Z_2_ALUT; + wire alu_output_PFUMX_Z_2_BLUT; + wire \alu_output_PFUMX_Z_2_C0[0] ; + wire \alu_output_PFUMX_Z_2_C0[1] ; + wire \alu_output_PFUMX_Z_2_C0[2] ; + wire \alu_output_PFUMX_Z_2_C0[3] ; + wire \alu_output_PFUMX_Z_2_C0[4] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B[0] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B[1] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B[2] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B[3] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A[0] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A[1] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A[2] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A[3] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A[4] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_B[0] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_B[1] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_B[2] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_B[3] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_B[4] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_B[5] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_B[6] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[0] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[1] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[2] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[3] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[4] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[5] ; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[0] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[1] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[2] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[4] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[5] ; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[0] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[2] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[4] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[5] ; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_ALUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_D1; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_D1_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[0] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[1] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[2] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[3] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[4] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[5] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[6] ; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[2] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[4] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[5] ; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_1_Z; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_B[0] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_B[1] ; + wire \alu_output_PFUMX_Z_2_C0_LUT4_Z_B[2] ; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_3_ALUT; + wire alu_output_PFUMX_Z_3_BLUT; + wire \alu_output_PFUMX_Z_3_C0[0] ; + wire \alu_output_PFUMX_Z_3_C0[1] ; + wire \alu_output_PFUMX_Z_3_C0[2] ; + wire \alu_output_PFUMX_Z_3_C0[3] ; + wire \alu_output_PFUMX_Z_3_C0[4] ; + wire alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_PFUMX_Z_3_C0_LUT4_Z_C[0] ; + wire \alu_output_PFUMX_Z_3_C0_LUT4_Z_C[1] ; + wire \alu_output_PFUMX_Z_3_C0_LUT4_Z_C[2] ; + wire \alu_output_PFUMX_Z_3_C0_LUT4_Z_C[3] ; + wire alu_output_PFUMX_Z_3_C0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_3_C0_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_4_ALUT; + wire alu_output_PFUMX_Z_4_BLUT; + wire alu_output_PFUMX_Z_5_ALUT; + wire alu_output_PFUMX_Z_5_BLUT; + wire alu_output_PFUMX_Z_6_ALUT; + wire alu_output_PFUMX_Z_6_BLUT; + wire alu_output_PFUMX_Z_7_ALUT; + wire alu_output_PFUMX_Z_7_BLUT; + wire alu_output_PFUMX_Z_8_ALUT; + wire alu_output_PFUMX_Z_8_BLUT; + wire alu_output_PFUMX_Z_9_ALUT; + wire alu_output_PFUMX_Z_9_BLUT; + wire \alu_output_PFUMX_Z_9_C0[0] ; + wire \alu_output_PFUMX_Z_9_C0[1] ; + wire \alu_output_PFUMX_Z_9_C0[2] ; + wire \alu_output_PFUMX_Z_9_C0[3] ; + wire \alu_output_PFUMX_Z_9_C0[4] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B[0] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B[1] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B[2] ; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[0] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[2] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[4] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[5] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[6] ; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_1_Z; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[2] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[4] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[5] ; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[0] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[1] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[2] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[3] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[4] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[5] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[6] ; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_1_Z; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_D1; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_D1_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[0] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[1] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[2] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[3] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[4] ; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0_PFUMX_Z_BLUT; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[0] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[1] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[2] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[3] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] ; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_PFUMX_Z_BLUT; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_A[0] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_A[1] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_A[2] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_A[3] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_A[4] ; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[0] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[1] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[2] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[3] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[4] ; + wire \alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[5] ; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D0; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D0_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D1; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D1_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D0; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D0_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D1; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D1_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_9_C0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_9_C0_PFUMX_Z_BLUT; + wire \alu_output_PFUMX_Z_9_C0_PFUMX_Z_C0[0] ; + wire \alu_output_PFUMX_Z_9_C0_PFUMX_Z_C0[1] ; + wire \alu_output_PFUMX_Z_9_C0_PFUMX_Z_C0[2] ; + wire \alu_output_PFUMX_Z_9_C0_PFUMX_Z_C0[3] ; + wire \alu_output_PFUMX_Z_9_C0_PFUMX_Z_C0[4] ; + wire alu_output_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_BLUT; + wire \alu_output_PFUMX_Z_C0[0] ; + wire \alu_output_PFUMX_Z_C0[1] ; + wire \alu_output_PFUMX_Z_C0[2] ; + wire \alu_output_PFUMX_Z_C0[3] ; + wire \alu_output_PFUMX_Z_C0[4] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_1_A[0] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_1_A[1] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_1_A[2] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[0] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[1] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[2] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[3] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[4] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[5] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[6] ; + wire alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0; + wire alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1; + wire alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_2_B[0] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_2_B[1] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_2_B[2] ; + wire alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_2_B_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_2_B_PFUMX_Z_BLUT; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_A[0] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_A[1] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_A[2] ; + wire alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[0] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[2] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[4] ; + wire alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[0] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[1] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[2] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[3] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[4] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[5] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A[0] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A[1] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A[2] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A[3] ; + wire alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_ALUT; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_ALUT_LUT4_Z_D[0] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_ALUT_LUT4_Z_D[1] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_ALUT_LUT4_Z_D[2] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_ALUT_LUT4_Z_D[3] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_ALUT_LUT4_Z_D[4] ; + wire alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_BLUT; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_C[0] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_C[1] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_C[2] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_C[3] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_B[0] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_B[1] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_B[2] ; + wire alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[0] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[2] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[4] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[5] ; + wire alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_1_Z; + wire alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_1_Z_PFUMX_ALUT_Z; + wire alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z; + wire alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z[0] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z[1] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z[2] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z[3] ; + wire \alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z[4] ; + wire alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT; + wire \alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[0] ; + wire \alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[1] ; + wire \alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[2] ; + wire \alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[3] ; + wire \alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[4] ; + wire alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0; + wire alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1; + wire alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT; + wire alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT; + wire alu_output_PFUMX_Z_C0_PFUMX_Z_BLUT; + wire \alu_output_PFUMX_Z_C0_PFUMX_Z_C0[0] ; + wire \alu_output_PFUMX_Z_C0_PFUMX_Z_C0[1] ; + wire \alu_output_PFUMX_Z_C0_PFUMX_Z_C0[2] ; + wire \alu_output_PFUMX_Z_C0_PFUMX_Z_C0[3] ; + wire \alu_output_PFUMX_Z_C0_PFUMX_Z_C0[4] ; + wire \alu_output_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z_D[0] ; + wire \alu_output_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z_D[1] ; + wire \alu_output_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z_D[2] ; + wire \alu_output_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z_D[3] ; + wire \complement2[0] ; + wire \complement2[10] ; + wire \complement2[11] ; + wire \complement2[12] ; + wire \complement2[13] ; + wire \complement2[14] ; + wire \complement2[15] ; + wire \complement2[16] ; + wire \complement2[17] ; + wire \complement2[18] ; + wire \complement2[19] ; + wire \complement2[1] ; + wire \complement2[20] ; + wire \complement2[21] ; + wire \complement2[22] ; + wire \complement2[23] ; + wire \complement2[24] ; + wire \complement2[25] ; + wire \complement2[26] ; + wire \complement2[27] ; + wire \complement2[28] ; + wire \complement2[29] ; + wire \complement2[2] ; + wire \complement2[30] ; + wire \complement2[31] ; + wire \complement2[3] ; + wire \complement2[4] ; + wire \complement2[5] ; + wire \complement2[6] ; + wire \complement2[7] ; + wire \complement2[8] ; + wire \complement2[9] ; + wire \complement2_CCU2C_S0_3_COUT[0] ; + wire \complement2_CCU2C_S0_3_COUT[10] ; + wire \complement2_CCU2C_S0_3_COUT[11] ; + wire \complement2_CCU2C_S0_3_COUT[12] ; + wire \complement2_CCU2C_S0_3_COUT[13] ; + wire \complement2_CCU2C_S0_3_COUT[14] ; + wire \complement2_CCU2C_S0_3_COUT[15] ; + wire \complement2_CCU2C_S0_3_COUT[16] ; + wire \complement2_CCU2C_S0_3_COUT[17] ; + wire \complement2_CCU2C_S0_3_COUT[18] ; + wire \complement2_CCU2C_S0_3_COUT[19] ; + wire \complement2_CCU2C_S0_3_COUT[1] ; + wire \complement2_CCU2C_S0_3_COUT[20] ; + wire \complement2_CCU2C_S0_3_COUT[21] ; + wire \complement2_CCU2C_S0_3_COUT[22] ; + wire \complement2_CCU2C_S0_3_COUT[23] ; + wire \complement2_CCU2C_S0_3_COUT[24] ; + wire \complement2_CCU2C_S0_3_COUT[25] ; + wire \complement2_CCU2C_S0_3_COUT[26] ; + wire \complement2_CCU2C_S0_3_COUT[27] ; + wire \complement2_CCU2C_S0_3_COUT[28] ; + wire \complement2_CCU2C_S0_3_COUT[29] ; + wire \complement2_CCU2C_S0_3_COUT[2] ; + wire \complement2_CCU2C_S0_3_COUT[30] ; + wire \complement2_CCU2C_S0_3_COUT[31] ; + wire \complement2_CCU2C_S0_3_COUT[3] ; + wire \complement2_CCU2C_S0_3_COUT[4] ; + wire \complement2_CCU2C_S0_3_COUT[5] ; + wire \complement2_CCU2C_S0_3_COUT[6] ; + wire \complement2_CCU2C_S0_3_COUT[7] ; + wire \complement2_CCU2C_S0_3_COUT[8] ; + wire \complement2_CCU2C_S0_3_COUT[9] ; + wire \complement2_CCU2C_S0_B0[0] ; + wire \complement2_CCU2C_S0_B0[10] ; + wire \complement2_CCU2C_S0_B0[11] ; + wire \complement2_CCU2C_S0_B0[12] ; + wire \complement2_CCU2C_S0_B0[13] ; + wire \complement2_CCU2C_S0_B0[14] ; + wire \complement2_CCU2C_S0_B0[15] ; + wire \complement2_CCU2C_S0_B0[16] ; + wire \complement2_CCU2C_S0_B0[17] ; + wire \complement2_CCU2C_S0_B0[18] ; + wire \complement2_CCU2C_S0_B0[19] ; + wire \complement2_CCU2C_S0_B0[1] ; + wire \complement2_CCU2C_S0_B0[20] ; + wire \complement2_CCU2C_S0_B0[21] ; + wire \complement2_CCU2C_S0_B0[22] ; + wire \complement2_CCU2C_S0_B0[23] ; + wire \complement2_CCU2C_S0_B0[24] ; + wire \complement2_CCU2C_S0_B0[25] ; + wire \complement2_CCU2C_S0_B0[26] ; + wire \complement2_CCU2C_S0_B0[27] ; + wire \complement2_CCU2C_S0_B0[28] ; + wire \complement2_CCU2C_S0_B0[29] ; + wire \complement2_CCU2C_S0_B0[2] ; + wire \complement2_CCU2C_S0_B0[30] ; + wire \complement2_CCU2C_S0_B0[31] ; + wire \complement2_CCU2C_S0_B0[3] ; + wire \complement2_CCU2C_S0_B0[4] ; + wire \complement2_CCU2C_S0_B0[5] ; + wire \complement2_CCU2C_S0_B0[6] ; + wire \complement2_CCU2C_S0_B0[7] ; + wire \complement2_CCU2C_S0_B0[8] ; + wire \complement2_CCU2C_S0_B0[9] ; + wire \complement2_CCU2C_S0_COUT[0] ; + wire \complement2_CCU2C_S0_COUT[10] ; + wire \complement2_CCU2C_S0_COUT[11] ; + wire \complement2_CCU2C_S0_COUT[12] ; + wire \complement2_CCU2C_S0_COUT[13] ; + wire \complement2_CCU2C_S0_COUT[14] ; + wire \complement2_CCU2C_S0_COUT[15] ; + wire \complement2_CCU2C_S0_COUT[16] ; + wire \complement2_CCU2C_S0_COUT[17] ; + wire \complement2_CCU2C_S0_COUT[18] ; + wire \complement2_CCU2C_S0_COUT[19] ; + wire \complement2_CCU2C_S0_COUT[1] ; + wire \complement2_CCU2C_S0_COUT[20] ; + wire \complement2_CCU2C_S0_COUT[21] ; + wire \complement2_CCU2C_S0_COUT[22] ; + wire \complement2_CCU2C_S0_COUT[23] ; + wire \complement2_CCU2C_S0_COUT[24] ; + wire \complement2_CCU2C_S0_COUT[25] ; + wire \complement2_CCU2C_S0_COUT[26] ; + wire \complement2_CCU2C_S0_COUT[27] ; + wire \complement2_CCU2C_S0_COUT[28] ; + wire \complement2_CCU2C_S0_COUT[29] ; + wire \complement2_CCU2C_S0_COUT[2] ; + wire \complement2_CCU2C_S0_COUT[30] ; + wire \complement2_CCU2C_S0_COUT[31] ; + wire \complement2_CCU2C_S0_COUT[3] ; + wire \complement2_CCU2C_S0_COUT[4] ; + wire \complement2_CCU2C_S0_COUT[5] ; + wire \complement2_CCU2C_S0_COUT[6] ; + wire \complement2_CCU2C_S0_COUT[7] ; + wire \complement2_CCU2C_S0_COUT[8] ; + wire \complement2_CCU2C_S0_COUT[9] ; + wire \complement2_LUT4_C_D[0] ; + wire \complement2_LUT4_C_D[1] ; + wire \complement2_LUT4_C_D[2] ; + wire \sum[0] ; + wire \sum[10] ; + wire \sum[11] ; + wire \sum[12] ; + wire \sum[13] ; + wire \sum[14] ; + wire \sum[15] ; + wire \sum[16] ; + wire \sum[17] ; + wire \sum[18] ; + wire \sum[19] ; + wire \sum[1] ; + wire \sum[20] ; + wire \sum[21] ; + wire \sum[22] ; + wire \sum[23] ; + wire \sum[24] ; + wire \sum[25] ; + wire \sum[26] ; + wire \sum[27] ; + wire \sum[28] ; + wire \sum[29] ; + wire \sum[2] ; + wire \sum[30] ; + wire \sum[31] ; + wire \sum[3] ; + wire \sum[4] ; + wire \sum[5] ; + wire \sum[6] ; + wire \sum[7] ; + wire \sum[8] ; + wire \sum[9] ; + wire \sum_CCU2C_S0_3_COUT[0] ; + wire \sum_CCU2C_S0_3_COUT[10] ; + wire \sum_CCU2C_S0_3_COUT[11] ; + wire \sum_CCU2C_S0_3_COUT[12] ; + wire \sum_CCU2C_S0_3_COUT[13] ; + wire \sum_CCU2C_S0_3_COUT[14] ; + wire \sum_CCU2C_S0_3_COUT[15] ; + wire \sum_CCU2C_S0_3_COUT[16] ; + wire \sum_CCU2C_S0_3_COUT[17] ; + wire \sum_CCU2C_S0_3_COUT[18] ; + wire \sum_CCU2C_S0_3_COUT[19] ; + wire \sum_CCU2C_S0_3_COUT[1] ; + wire \sum_CCU2C_S0_3_COUT[20] ; + wire \sum_CCU2C_S0_3_COUT[21] ; + wire \sum_CCU2C_S0_3_COUT[22] ; + wire \sum_CCU2C_S0_3_COUT[23] ; + wire \sum_CCU2C_S0_3_COUT[24] ; + wire \sum_CCU2C_S0_3_COUT[25] ; + wire \sum_CCU2C_S0_3_COUT[26] ; + wire \sum_CCU2C_S0_3_COUT[27] ; + wire \sum_CCU2C_S0_3_COUT[28] ; + wire \sum_CCU2C_S0_3_COUT[29] ; + wire \sum_CCU2C_S0_3_COUT[2] ; + wire \sum_CCU2C_S0_3_COUT[30] ; + wire \sum_CCU2C_S0_3_COUT[31] ; + wire \sum_CCU2C_S0_3_COUT[3] ; + wire \sum_CCU2C_S0_3_COUT[4] ; + wire \sum_CCU2C_S0_3_COUT[5] ; + wire \sum_CCU2C_S0_3_COUT[6] ; + wire \sum_CCU2C_S0_3_COUT[7] ; + wire \sum_CCU2C_S0_3_COUT[8] ; + wire \sum_CCU2C_S0_3_COUT[9] ; + wire \sum_CCU2C_S0_B0[0] ; + wire \sum_CCU2C_S0_B0[10] ; + wire \sum_CCU2C_S0_B0[11] ; + wire \sum_CCU2C_S0_B0[12] ; + wire \sum_CCU2C_S0_B0[13] ; + wire \sum_CCU2C_S0_B0[14] ; + wire \sum_CCU2C_S0_B0[15] ; + wire \sum_CCU2C_S0_B0[16] ; + wire \sum_CCU2C_S0_B0[17] ; + wire \sum_CCU2C_S0_B0[18] ; + wire \sum_CCU2C_S0_B0[19] ; + wire \sum_CCU2C_S0_B0[1] ; + wire \sum_CCU2C_S0_B0[20] ; + wire \sum_CCU2C_S0_B0[21] ; + wire \sum_CCU2C_S0_B0[22] ; + wire \sum_CCU2C_S0_B0[23] ; + wire \sum_CCU2C_S0_B0[24] ; + wire \sum_CCU2C_S0_B0[25] ; + wire \sum_CCU2C_S0_B0[26] ; + wire \sum_CCU2C_S0_B0[27] ; + wire \sum_CCU2C_S0_B0[28] ; + wire \sum_CCU2C_S0_B0[29] ; + wire \sum_CCU2C_S0_B0[2] ; + wire \sum_CCU2C_S0_B0[30] ; + wire \sum_CCU2C_S0_B0[31] ; + wire \sum_CCU2C_S0_B0[3] ; + wire \sum_CCU2C_S0_B0[4] ; + wire \sum_CCU2C_S0_B0[5] ; + wire \sum_CCU2C_S0_B0[6] ; + wire \sum_CCU2C_S0_B0[7] ; + wire \sum_CCU2C_S0_B0[8] ; + wire \sum_CCU2C_S0_B0[9] ; + wire \sum_CCU2C_S0_COUT[0] ; + wire \sum_CCU2C_S0_COUT[10] ; + wire \sum_CCU2C_S0_COUT[11] ; + wire \sum_CCU2C_S0_COUT[12] ; + wire \sum_CCU2C_S0_COUT[13] ; + wire \sum_CCU2C_S0_COUT[14] ; + wire \sum_CCU2C_S0_COUT[15] ; + wire \sum_CCU2C_S0_COUT[16] ; + wire \sum_CCU2C_S0_COUT[17] ; + wire \sum_CCU2C_S0_COUT[18] ; + wire \sum_CCU2C_S0_COUT[19] ; + wire \sum_CCU2C_S0_COUT[1] ; + wire \sum_CCU2C_S0_COUT[20] ; + wire \sum_CCU2C_S0_COUT[21] ; + wire \sum_CCU2C_S0_COUT[22] ; + wire \sum_CCU2C_S0_COUT[23] ; + wire \sum_CCU2C_S0_COUT[24] ; + wire \sum_CCU2C_S0_COUT[25] ; + wire \sum_CCU2C_S0_COUT[26] ; + wire \sum_CCU2C_S0_COUT[27] ; + wire \sum_CCU2C_S0_COUT[28] ; + wire \sum_CCU2C_S0_COUT[29] ; + wire \sum_CCU2C_S0_COUT[2] ; + wire \sum_CCU2C_S0_COUT[30] ; + wire \sum_CCU2C_S0_COUT[31] ; + wire \sum_CCU2C_S0_COUT[3] ; + wire \sum_CCU2C_S0_COUT[4] ; + wire \sum_CCU2C_S0_COUT[5] ; + wire \sum_CCU2C_S0_COUT[6] ; + wire \sum_CCU2C_S0_COUT[7] ; + wire \sum_CCU2C_S0_COUT[8] ; + wire \sum_CCU2C_S0_COUT[9] ; + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0003_ ( + .D0(alu_output_L6MUX21_Z_D0), + .D1(alu_output_L6MUX21_Z_D1), + .SD(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[5] ), + .Z(\alu_output[24] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" *) + L6MUX21 _0004_ ( + .D0(alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D0), + .D1(alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D1), + .SD(\alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[5] ), + .Z(alu_output_L6MUX21_Z_2_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0005_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" *) + PFUMX _0006_ ( + .ALUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0007_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" *) + LUT4 #( + .INIT(16'h0003) + ) _0008_ ( + .A(_0000_), + .B(\alu_in_1[16] ), + .C(\alu_op_i[2] ), + .D(\alu_in_2[6] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0009_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0010_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_1_Z) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0011_ ( + .ALUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z), + .BLUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_1_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0012_ ( + .A(_0000_), + .B(\alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[2] ), + .C(\alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[3] ), + .D(\alu_in_2[1] ), + .Z(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0013_ ( + .A(_0000_), + .B(\alu_in_1[26] ), + .C(\alu_in_1[27] ), + .D(\alu_in_2[0] ), + .Z(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" *) + LUT4 #( + .INIT(16'h0f00) + ) _0014_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_output_LUT4_Z_9_B_LUT4_Z_1_B[1] ), + .D(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] ), + .Z(\alu_output_PFUMX_Z_2_C0[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hf100) + ) _0015_ ( + .A(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .B(\alu_output_LUT4_Z_9_B_LUT4_Z_1_B[0] ), + .C(\alu_output_LUT4_Z_9_B_LUT4_Z_1_C[2] ), + .D(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[5] ), + .Z(\alu_output_PFUMX_Z_2_C0[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'hafcf) + ) _0016_ ( + .A(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A[0] ), + .B(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A[1] ), + .C(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .D(\alu_in_2[2] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0017_ ( + .D0(alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D1), + .SD(\alu_op_i[2] ), + .Z(\alu_output_PFUMX_Z_2_C0_LUT4_Z_B[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0018_ ( + .ALUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[27] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'hfff3) + ) _0019_ ( + .A(_0000_), + .B(\sum[27] ), + .C(\alu_op_i[1] ), + .D(\alu_op_i[0] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'hfff3) + ) _0020_ ( + .A(_0000_), + .B(\sum[27] ), + .C(\alu_op_i[1] ), + .D(\alu_op_i[0] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0021_ ( + .ALUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[27] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h33f0) + ) _0022_ ( + .A(_0000_), + .B(\alu_op_i[1] ), + .C(\alu_op_i[0] ), + .D(\alu_in_1[27] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'hf0ff) + ) _0023_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_op_i[0] ), + .D(\alu_in_1[27] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0c05) + ) _0024_ ( + .A(\alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[0] ), + .B(\alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[1] ), + .C(\alu_in_2[3] ), + .D(\alu_in_2[2] ), + .Z(\alu_output_PFUMX_Z_2_C0_LUT4_Z_B[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0025_ ( + .ALUT(alu_output_PFUMX_Z_3_ALUT), + .BLUT(alu_output_PFUMX_Z_3_BLUT), + .C0(\alu_output_PFUMX_Z_3_C0[4] ), + .Z(\alu_output[26] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'hff0b) + ) _0026_ ( + .A(\alu_output_PFUMX_Z_3_C0[0] ), + .B(\alu_output_PFUMX_Z_3_C0[1] ), + .C(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] ), + .D(\alu_output_PFUMX_Z_3_C0[3] ), + .Z(alu_output_PFUMX_Z_3_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0027_ ( + .D0(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D1), + .SD(\alu_in_2[1] ), + .Z(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'hffff) + ) _0028_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_3_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0029_ ( + .D0(alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D1), + .SD(\alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] ), + .Z(\alu_output_PFUMX_Z_3_C0[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0030_ ( + .ALUT(alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .Z(alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'hff0f) + ) _0031_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] ), + .D(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[2] ), + .Z(alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'hff0f) + ) _0032_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] ), + .D(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[2] ), + .Z(alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0033_ ( + .ALUT(alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .Z(alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h3303) + ) _0034_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[0] ), + .C(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] ), + .D(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[2] ), + .Z(alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'h3303) + ) _0035_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[1] ), + .C(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] ), + .D(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[2] ), + .Z(alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0007) + ) _0036_ ( + .A(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ), + .B(\sum[26] ), + .C(\alu_output_PFUMX_Z_3_C0_LUT4_Z_C[2] ), + .D(\alu_output_PFUMX_Z_3_C0_LUT4_Z_C[3] ), + .Z(\alu_output_PFUMX_Z_3_C0[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'ha300) + ) _0037_ ( + .A(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[0] ), + .B(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[1] ), + .C(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .D(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[5] ), + .Z(\alu_output_PFUMX_Z_3_C0[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" *) + L6MUX21 _0038_ ( + .D0(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0), + .D1(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1), + .SD(\alu_in_2[0] ), + .Z(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hc000) + ) _0039_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ), + .C(\alu_in_1[26] ), + .D(\alu_in_2[26] ), + .Z(\alu_output_PFUMX_Z_3_C0_LUT4_Z_C[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hcee0) + ) _0040_ ( + .A(\alu_output_LUT4_Z_7_A_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_7_A_LUT4_Z_A[1] ), + .C(\alu_in_1[26] ), + .D(\alu_in_2[26] ), + .Z(\alu_output_PFUMX_Z_3_C0_LUT4_Z_C[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0041_ ( + .ALUT(alu_output_PFUMX_Z_3_C0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_3_C0_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] ), + .Z(\alu_output_PFUMX_Z_3_C0[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h0c05) + ) _0042_ ( + .A(\alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[2] ), + .B(\alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[3] ), + .C(\alu_in_2[3] ), + .D(\alu_in_2[2] ), + .Z(alu_output_PFUMX_Z_3_C0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0043_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_3_C0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0044_ ( + .ALUT(alu_output_PFUMX_Z_4_ALUT), + .BLUT(alu_output_PFUMX_Z_4_BLUT), + .C0(\alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z[4] ), + .Z(\alu_output[23] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0045_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z[3] ), + .Z(alu_output_PFUMX_Z_4_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h1fff) + ) _0046_ ( + .A(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .B(\alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z[1] ), + .C(\alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z[2] ), + .D(\alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z[3] ), + .Z(alu_output_PFUMX_Z_4_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0047_ ( + .ALUT(alu_output_PFUMX_Z_5_ALUT), + .BLUT(alu_output_PFUMX_Z_5_BLUT), + .C0(\alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z[4] ), + .Z(\alu_output[22] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0048_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z[3] ), + .Z(alu_output_PFUMX_Z_5_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" *) + L6MUX21 _0049_ ( + .D0(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D1), + .SD(\alu_in_2[31] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h1fff) + ) _0050_ ( + .A(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .B(\alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z[1] ), + .C(\alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z[2] ), + .D(\alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z[3] ), + .Z(alu_output_PFUMX_Z_5_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0051_ ( + .ALUT(alu_output_PFUMX_Z_6_ALUT), + .BLUT(alu_output_PFUMX_Z_6_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[4] ), + .Z(\alu_output[21] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'hf4ff) + ) _0052_ ( + .A(\alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[0] ), + .B(\alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[1] ), + .C(\alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[3] ), + .Z(alu_output_PFUMX_Z_6_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0053_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[3] ), + .Z(alu_output_PFUMX_Z_6_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0054_ ( + .ALUT(alu_output_PFUMX_Z_7_ALUT), + .BLUT(alu_output_PFUMX_Z_7_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[4] ), + .Z(\alu_output[17] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'hf8ff) + ) _0055_ ( + .A(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[0] ), + .B(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[1] ), + .C(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[2] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[3] ), + .Z(alu_output_PFUMX_Z_7_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0056_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[3] ), + .Z(alu_output_PFUMX_Z_7_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0057_ ( + .ALUT(alu_output_PFUMX_Z_8_ALUT), + .BLUT(alu_output_PFUMX_Z_8_BLUT), + .C0(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[4] ), + .Z(\alu_output[16] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h44f4) + ) _0058_ ( + .A(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[0] ), + .B(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[1] ), + .C(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] ), + .D(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[0] ), + .Z(alu_output_PFUMX_Z_8_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'hffff) + ) _0059_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_8_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" *) + PFUMX _0060_ ( + .ALUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_op_i[0] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0061_ ( + .ALUT(alu_output_PFUMX_Z_9_ALUT), + .BLUT(alu_output_PFUMX_Z_9_BLUT), + .C0(\alu_output_PFUMX_Z_9_C0[4] ), + .Z(\alu_output[14] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'hffe0) + ) _0062_ ( + .A(\alu_output_PFUMX_Z_9_C0[0] ), + .B(\alu_output_PFUMX_Z_9_C0[1] ), + .C(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] ), + .D(\alu_output_PFUMX_Z_9_C0[3] ), + .Z(alu_output_PFUMX_Z_9_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'hffff) + ) _0063_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_9_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h5300) + ) _0064_ ( + .A(\alu_output_PFUMX_Z_9_C0_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z[2] ), + .C(\alu_in_2[3] ), + .D(\alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] ), + .Z(\alu_output_PFUMX_Z_9_C0[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" *) + LUT4 #( + .INIT(16'hf000) + ) _0065_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_output_PFUMX_Z_1_C0_LUT4_Z_A[0] ), + .D(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] ), + .Z(\alu_output_PFUMX_Z_9_C0[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'ha300) + ) _0066_ ( + .A(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[1] ), + .B(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B[0] ), + .C(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] ), + .Z(\alu_output_PFUMX_Z_9_C0[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" *) + L6MUX21 _0067_ ( + .D0(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1), + .SD(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .Z(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" *) + L6MUX21 _0068_ ( + .D0(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1), + .SD(\alu_in_2[2] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" *) + PFUMX _0069_ ( + .ALUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0070_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" *) + LUT4 #( + .INIT(16'h0002) + ) _0071_ ( + .A(\alu_in_1[0] ), + .B(\alu_op_i[1] ), + .C(\alu_op_i[2] ), + .D(\alu_in_2[6] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0072_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" *) + PFUMX _0073_ ( + .ALUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0074_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0075_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" *) + L6MUX21 _0076_ ( + .D0(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1), + .SD(\alu_in_2[2] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" *) + PFUMX _0077_ ( + .ALUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0078_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[2] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0079_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0080_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[2] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0081_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_1_Z) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0082_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" *) + PFUMX _0083_ ( + .ALUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z), + .BLUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_1_Z), + .C0(\alu_in_2[1] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0084_ ( + .A(_0000_), + .B(\alu_in_1[13] ), + .C(\alu_in_1[14] ), + .D(\alu_in_2[0] ), + .Z(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0085_ ( + .A(_0000_), + .B(\alu_in_1[11] ), + .C(\alu_in_1[12] ), + .D(\alu_in_2[0] ), + .Z(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" *) + PFUMX _0086_ ( + .ALUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0087_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0088_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'h330f) + ) _0089_ ( + .A(_0000_), + .B(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] ), + .C(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] ), + .D(\alu_in_2[1] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0090_ ( + .ALUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT), + .BLUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z), + .C0(\alu_in_2[2] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0091_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[2] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0092_ ( + .D0(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D1), + .SD(\alu_in_2[1] ), + .Z(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" *) + PFUMX _0093_ ( + .ALUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_op_i[0] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0094_ ( + .ALUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[0] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0095_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[5] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0096_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[6] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0097_ ( + .ALUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[0] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0098_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[3] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0099_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[4] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0100_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[2] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0101_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[2] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_1_Z) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" *) + PFUMX _0102_ ( + .ALUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z), + .BLUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_1_Z), + .C0(\alu_in_2[1] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" *) + L6MUX21 _0103_ ( + .D0(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z), + .D1(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_D1), + .SD(\alu_in_2[2] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" *) + LUT4 #( + .INIT(16'hfffe) + ) _0104_ ( + .A(\alu_in_1[0] ), + .B(\alu_op_i[1] ), + .C(\alu_op_i[2] ), + .D(\alu_in_2[6] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" *) + PFUMX _0105_ ( + .ALUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0106_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[1] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0107_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[2] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" *) + L6MUX21 _0108_ ( + .D0(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0), + .D1(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z), + .SD(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .Z(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" *) + L6MUX21 _0109_ ( + .D0(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1), + .SD(\alu_in_2[2] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" *) + PFUMX _0110_ ( + .ALUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" *) + LUT4 #( + .INIT(16'hffff) + ) _0111_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" *) + LUT4 #( + .INIT(16'hfff0) + ) _0112_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_in_2[31] ), + .D(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[1] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" *) + PFUMX _0113_ ( + .ALUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" *) + LUT4 #( + .INIT(16'hffff) + ) _0114_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" *) + PFUMX _0115_ ( + .ALUT(alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[4] ), + .Z(alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" *) + LUT4 #( + .INIT(16'hffff) + ) _0116_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" *) + LUT4 #( + .INIT(16'hffff) + ) _0117_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hc000) + ) _0118_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ), + .C(\alu_in_2[6] ), + .D(\alu_in_1[6] ), + .Z(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" *) + LUT4 #( + .INIT(16'hf000) + ) _0119_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ), + .D(\sum[6] ), + .Z(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hcee0) + ) _0120_ ( + .A(\alu_output_LUT4_Z_7_A_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_7_A_LUT4_Z_A[1] ), + .C(\alu_in_2[6] ), + .D(\alu_in_1[6] ), + .Z(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0121_ ( + .D0(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0), + .D1(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z), + .SD(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .Z(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0122_ ( + .ALUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[2] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0123_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0124_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" *) + L6MUX21 _0125_ ( + .D0(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z), + .SD(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .Z(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0126_ ( + .D0(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0), + .D1(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1), + .SD(\alu_in_2[4] ), + .Z(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" *) + L6MUX21 _0127_ ( + .D0(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D1), + .SD(\alu_in_2[31] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0128_ ( + .ALUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[31] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0129_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'hfeff) + ) _0130_ ( + .A(\alu_op_i[1] ), + .B(\alu_op_i[2] ), + .C(\alu_in_2[6] ), + .D(\alu_op_i[0] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0131_ ( + .ALUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[31] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h0100) + ) _0132_ ( + .A(\alu_op_i[1] ), + .B(\alu_op_i[2] ), + .C(\alu_in_2[6] ), + .D(\alu_op_i[0] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'h0100) + ) _0133_ ( + .A(\alu_op_i[1] ), + .B(\alu_op_i[2] ), + .C(\alu_in_2[6] ), + .D(\alu_op_i[0] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" *) + L6MUX21 _0134_ ( + .D0(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1), + .SD(\alu_in_2[2] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" *) + PFUMX _0135_ ( + .ALUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0136_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0137_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" *) + PFUMX _0138_ ( + .ALUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_op_i[0] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" *) + PFUMX _0139_ ( + .ALUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0140_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0141_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0142_ ( + .ALUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] ), + .Z(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h00fc) + ) _0143_ ( + .A(_0000_), + .B(\alu_op_i[2] ), + .C(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[2] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h00f0) + ) _0144_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[1] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0145_ ( + .A(_0000_), + .B(\alu_in_1[9] ), + .C(\alu_in_1[10] ), + .D(\alu_in_2[0] ), + .Z(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0146_ ( + .A(_0000_), + .B(\alu_in_1[7] ), + .C(\alu_in_1[8] ), + .D(\alu_in_2[0] ), + .Z(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'h00cf) + ) _0147_ ( + .A(_0000_), + .B(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B[0] ), + .C(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .D(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] ), + .Z(\alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0148_ ( + .D0(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D1), + .SD(\alu_op_i[2] ), + .Z(\alu_output_PFUMX_Z_9_C0_LUT4_Z_A[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" *) + LUT4 #( + .INIT(16'hfffc) + ) _0149_ ( + .A(_0000_), + .B(\alu_op_i[1] ), + .C(\alu_op_i[2] ), + .D(\alu_in_2[6] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0150_ ( + .ALUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[22] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'hfff3) + ) _0151_ ( + .A(_0000_), + .B(\sum[22] ), + .C(\alu_op_i[1] ), + .D(\alu_op_i[0] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'hfff3) + ) _0152_ ( + .A(_0000_), + .B(\sum[22] ), + .C(\alu_op_i[1] ), + .D(\alu_op_i[0] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0153_ ( + .ALUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[22] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h33f0) + ) _0154_ ( + .A(_0000_), + .B(\alu_op_i[1] ), + .C(\alu_op_i[0] ), + .D(\alu_in_1[22] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'hf0ff) + ) _0155_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_op_i[0] ), + .D(\alu_in_1[22] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" *) + LUT4 #( + .INIT(16'h0f00) + ) _0156_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_in_2[2] ), + .D(\alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[3] ), + .Z(\alu_output_PFUMX_Z_9_C0_LUT4_Z_A[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hf0cc) + ) _0157_ ( + .A(_0000_), + .B(\alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[1] ), + .C(\alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[2] ), + .D(\alu_in_2[2] ), + .Z(\alu_output_PFUMX_Z_9_C0_LUT4_Z_A[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0158_ ( + .D0(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(\alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0159_ ( + .D0(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D0), + .D1(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D1), + .SD(\alu_in_2[0] ), + .Z(\alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" *) + LUT4 #( + .INIT(16'hffff) + ) _0160_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0161_ ( + .ALUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0162_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[24] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0163_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[22] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0164_ ( + .ALUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0165_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[25] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0166_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[23] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0167_ ( + .D0(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D0), + .D1(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D1), + .SD(\alu_in_2[0] ), + .Z(\alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0168_ ( + .ALUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0169_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[20] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0170_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[18] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" *) + PFUMX _0171_ ( + .ALUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_op_i[0] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0172_ ( + .ALUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0173_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[21] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0174_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[19] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0175_ ( + .ALUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0176_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[28] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0177_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[26] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0178_ ( + .ALUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0179_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[29] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0180_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[27] ), + .Z(alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0c0a) + ) _0181_ ( + .A(\alu_in_1[30] ), + .B(\alu_in_1[31] ), + .C(\alu_in_2[1] ), + .D(\alu_in_2[0] ), + .Z(\alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" *) + LUT4 #( + .INIT(16'hfffc) + ) _0182_ ( + .A(_0000_), + .B(\alu_op_i[1] ), + .C(\alu_op_i[2] ), + .D(\alu_in_2[6] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0183_ ( + .ALUT(alu_output_PFUMX_Z_9_C0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_9_C0_PFUMX_Z_BLUT), + .C0(\alu_output_PFUMX_Z_9_C0_PFUMX_Z_C0[4] ), + .Z(\alu_output_PFUMX_Z_9_C0[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0184_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_9_C0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h0777) + ) _0185_ ( + .A(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ), + .B(\alu_output_PFUMX_Z_9_C0_PFUMX_Z_C0[1] ), + .C(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ), + .D(\sum[14] ), + .Z(alu_output_PFUMX_Z_9_C0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" *) + LUT4 #( + .INIT(16'hf000) + ) _0186_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_in_1[14] ), + .D(\alu_in_2[14] ), + .Z(\alu_output_PFUMX_Z_9_C0_PFUMX_Z_C0[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hcee0) + ) _0187_ ( + .A(\alu_output_LUT4_Z_7_A_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_7_A_LUT4_Z_A[1] ), + .C(\alu_in_1[14] ), + .D(\alu_in_2[14] ), + .Z(\alu_output_PFUMX_Z_9_C0_PFUMX_Z_C0[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h00fe) + ) _0188_ ( + .A(\alu_output_PFUMX_Z_C0[0] ), + .B(\alu_output_PFUMX_Z_C0[1] ), + .C(\alu_output_PFUMX_Z_C0[2] ), + .D(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] ), + .Z(alu_output_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'hffff) + ) _0189_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h5300) + ) _0190_ ( + .A(\alu_output_PFUMX_Z_C0_LUT4_Z_A[1] ), + .B(\alu_output_PFUMX_Z_C0_LUT4_Z_B[0] ), + .C(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .D(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[5] ), + .Z(\alu_output_PFUMX_Z_C0[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h5300) + ) _0191_ ( + .A(\alu_output_PFUMX_Z_C0_LUT4_Z_1_A[0] ), + .B(\alu_output_PFUMX_Z_C0_LUT4_Z_1_A[1] ), + .C(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .D(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] ), + .Z(\alu_output_PFUMX_Z_C0[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0192_ ( + .A(_0000_), + .B(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] ), + .C(\alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[2] ), + .D(\alu_in_2[1] ), + .Z(\alu_output_PFUMX_Z_C0_LUT4_Z_1_A[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" *) + LUT4 #( + .INIT(16'hffff) + ) _0193_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0194_ ( + .A(_0000_), + .B(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] ), + .C(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] ), + .D(\alu_in_2[1] ), + .Z(\alu_output_PFUMX_Z_C0_LUT4_Z_1_A[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" *) + L6MUX21 _0195_ ( + .D0(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1), + .SD(\alu_op_i[0] ), + .Z(\alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" *) + L6MUX21 _0196_ ( + .D0(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0), + .D1(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1), + .SD(\alu_op_i[0] ), + .Z(\alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" *) + L6MUX21 _0197_ ( + .D0(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" *) + PFUMX _0198_ ( + .ALUT(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0199_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0200_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" *) + PFUMX _0201_ ( + .ALUT(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0202_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0203_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0204_ ( + .ALUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[31] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" *) + L6MUX21 _0205_ ( + .D0(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" *) + PFUMX _0206_ ( + .ALUT(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0207_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" *) + LUT4 #( + .INIT(16'h0003) + ) _0208_ ( + .A(_0000_), + .B(\alu_in_1[23] ), + .C(\alu_op_i[2] ), + .D(\alu_in_2[6] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" *) + PFUMX _0209_ ( + .ALUT(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0210_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" *) + LUT4 #( + .INIT(16'h0003) + ) _0211_ ( + .A(_0000_), + .B(\alu_in_1[22] ), + .C(\alu_op_i[2] ), + .D(\alu_in_2[6] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" *) + L6MUX21 _0212_ ( + .D0(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" *) + PFUMX _0213_ ( + .ALUT(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0214_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'hffff) + ) _0215_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0216_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" *) + PFUMX _0217_ ( + .ALUT(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0218_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0219_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" *) + L6MUX21 _0220_ ( + .D0(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" *) + PFUMX _0221_ ( + .ALUT(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0222_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" *) + LUT4 #( + .INIT(16'h0003) + ) _0223_ ( + .A(_0000_), + .B(\alu_in_1[25] ), + .C(\alu_op_i[2] ), + .D(\alu_in_2[6] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" *) + PFUMX _0224_ ( + .ALUT(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0225_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" *) + LUT4 #( + .INIT(16'hffff) + ) _0226_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'h0100) + ) _0227_ ( + .A(\alu_op_i[1] ), + .B(\alu_op_i[2] ), + .C(\alu_in_2[6] ), + .D(\alu_op_i[0] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" *) + LUT4 #( + .INIT(16'h0003) + ) _0228_ ( + .A(_0000_), + .B(\alu_in_1[24] ), + .C(\alu_op_i[2] ), + .D(\alu_in_2[6] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'h0300) + ) _0229_ ( + .A(_0000_), + .B(\alu_output_PFUMX_Z_C0_LUT4_Z_2_B[0] ), + .C(\alu_output_PFUMX_Z_C0_LUT4_Z_2_B[1] ), + .D(\alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] ), + .Z(\alu_output_PFUMX_Z_C0[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" *) + L6MUX21 _0230_ ( + .D0(alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1), + .SD(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .Z(\alu_output_PFUMX_Z_C0_LUT4_Z_2_B[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" *) + L6MUX21 _0231_ ( + .D0(alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1), + .SD(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" *) + PFUMX _0232_ ( + .ALUT(alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0233_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0234_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" *) + PFUMX _0235_ ( + .ALUT(alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0236_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0237_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0238_ ( + .ALUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[31] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" *) + L6MUX21 _0239_ ( + .D0(alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1), + .SD(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" *) + PFUMX _0240_ ( + .ALUT(alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0241_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0242_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_B[2] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" *) + PFUMX _0243_ ( + .ALUT(alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0244_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" *) + LUT4 #( + .INIT(16'h330f) + ) _0245_ ( + .A(_0000_), + .B(\alu_in_1[30] ), + .C(\alu_in_1[31] ), + .D(\alu_in_2[0] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0246_ ( + .ALUT(alu_output_PFUMX_Z_C0_LUT4_Z_2_B_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_C0_LUT4_Z_2_B_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .Z(\alu_output_PFUMX_Z_C0_LUT4_Z_2_B[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'hf044) + ) _0247_ ( + .A(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .C(\alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[3] ), + .D(\alu_in_2[1] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_2_B_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0248_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_2_B_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'hfeff) + ) _0249_ ( + .A(\alu_op_i[1] ), + .B(\alu_op_i[2] ), + .C(\alu_in_2[6] ), + .D(\alu_op_i[0] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" *) + L6MUX21 _0250_ ( + .D0(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1), + .SD(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .Z(\alu_output_PFUMX_Z_C0_LUT4_Z_A[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" *) + L6MUX21 _0251_ ( + .D0(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1), + .SD(\alu_in_2[1] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" *) + PFUMX _0252_ ( + .ALUT(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" *) + LUT4 #( + .INIT(16'hffff) + ) _0253_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0254_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" *) + PFUMX _0255_ ( + .ALUT(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0256_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[3] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0257_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[3] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" *) + L6MUX21 _0258_ ( + .D0(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1), + .SD(\alu_in_2[1] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" *) + PFUMX _0259_ ( + .ALUT(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'hfeff) + ) _0260_ ( + .A(\alu_op_i[1] ), + .B(\alu_op_i[2] ), + .C(\alu_in_2[6] ), + .D(\alu_op_i[0] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0261_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0262_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" *) + L6MUX21 _0263_ ( + .D0(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1), + .SD(\alu_op_i[0] ), + .Z(\alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" *) + L6MUX21 _0264_ ( + .D0(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" *) + PFUMX _0265_ ( + .ALUT(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0266_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0267_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" *) + PFUMX _0268_ ( + .ALUT(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0269_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0270_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0271_ ( + .A(_0000_), + .B(\alu_in_1[1] ), + .C(\alu_in_1[2] ), + .D(\alu_in_2[0] ), + .Z(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" *) + L6MUX21 _0272_ ( + .D0(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" *) + PFUMX _0273_ ( + .ALUT(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0274_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" *) + LUT4 #( + .INIT(16'h0003) + ) _0275_ ( + .A(_0000_), + .B(\alu_in_1[3] ), + .C(\alu_op_i[2] ), + .D(\alu_in_2[6] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" *) + PFUMX _0276_ ( + .ALUT(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0277_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" *) + LUT4 #( + .INIT(16'h0003) + ) _0278_ ( + .A(_0000_), + .B(\alu_in_1[2] ), + .C(\alu_op_i[2] ), + .D(\alu_in_2[6] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" *) + LUT4 #( + .INIT(16'h0f00) + ) _0279_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[2] ), + .D(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .Z(\alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" *) + PFUMX _0280_ ( + .ALUT(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" *) + LUT4 #( + .INIT(16'h0f00) + ) _0281_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[2] ), + .D(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hf400) + ) _0282_ ( + .A(\alu_output_LUT4_Z_10_B_LUT4_Z_2_A[0] ), + .B(\alu_output_LUT4_Z_10_B_LUT4_Z_2_A[1] ), + .C(\alu_output_LUT4_Z_10_B_LUT4_Z_2_A[2] ), + .D(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] ), + .Z(\alu_output_LUT4_Z_10_B[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" *) + LUT4 #( + .INIT(16'h0f00) + ) _0283_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[2] ), + .D(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" *) + LUT4 #( + .INIT(16'h0f00) + ) _0284_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_output_PFUMX_Z_C0_LUT4_Z_A[1] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] ), + .Z(\alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0007) + ) _0285_ ( + .A(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ), + .B(\sum[7] ), + .C(\alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_C[2] ), + .D(\alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_C[3] ), + .Z(\alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[5] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'h3f00) + ) _0286_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] ), + .C(\alu_in_2[3] ), + .D(\alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] ), + .Z(\alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0c0a) + ) _0287_ ( + .A(\alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A[0] ), + .B(\alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[0] ), + .C(\alu_in_2[3] ), + .D(\alu_in_2[2] ), + .Z(\alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0288_ ( + .ALUT(alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(\alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0289_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_ALUT_LUT4_Z_D[2] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hf0cc) + ) _0290_ ( + .A(_0000_), + .B(\alu_in_1[9] ), + .C(\alu_in_1[10] ), + .D(\alu_in_2[0] ), + .Z(\alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_ALUT_LUT4_Z_D[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h0f33) + ) _0291_ ( + .A(_0000_), + .B(\alu_in_1[7] ), + .C(\alu_in_1[8] ), + .D(\alu_in_2[0] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hc000) + ) _0292_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ), + .C(\alu_in_1[7] ), + .D(\alu_in_2[7] ), + .Z(\alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_C[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hca00) + ) _0293_ ( + .A(\alu_output_LUT4_Z_1_B_LUT4_Z_1_A[0] ), + .B(\alu_output_LUT4_Z_1_B_LUT4_Z_1_A[1] ), + .C(\alu_in_2[2] ), + .D(\alu_in_2[3] ), + .Z(\alu_output_LUT4_Z_10_B_LUT4_Z_2_A[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hcee0) + ) _0294_ ( + .A(\alu_output_LUT4_Z_7_A_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_7_A_LUT4_Z_A[1] ), + .C(\alu_in_1[7] ), + .D(\alu_in_2[7] ), + .Z(\alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_C[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0295_ ( + .D0(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D1), + .SD(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .Z(\alu_output_PFUMX_Z_C0_LUT4_Z_B[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0296_ ( + .ALUT(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0297_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0298_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" *) + L6MUX21 _0299_ ( + .D0(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1), + .SD(\alu_op_i[0] ), + .Z(\alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" *) + L6MUX21 _0300_ ( + .D0(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" *) + PFUMX _0301_ ( + .ALUT(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0302_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0303_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0304_ ( + .ALUT(alu_output_LUT4_Z_10_B_LUT4_Z_2_A_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_10_B_LUT4_Z_2_A_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] ), + .Z(\alu_output_LUT4_Z_10_B_LUT4_Z_2_A[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" *) + PFUMX _0305_ ( + .ALUT(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0306_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0307_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" *) + L6MUX21 _0308_ ( + .D0(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" *) + PFUMX _0309_ ( + .ALUT(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0310_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" *) + LUT4 #( + .INIT(16'h0003) + ) _0311_ ( + .A(_0000_), + .B(\alu_in_1[15] ), + .C(\alu_op_i[2] ), + .D(\alu_in_2[6] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" *) + PFUMX _0312_ ( + .ALUT(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0313_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" *) + LUT4 #( + .INIT(16'h0003) + ) _0314_ ( + .A(_0000_), + .B(\alu_in_1[14] ), + .C(\alu_op_i[2] ), + .D(\alu_in_2[6] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0315_ ( + .ALUT(alu_output_LUT4_Z_10_B_LUT4_Z_2_A_PFUMX_Z_1_ALUT), + .BLUT(alu_output_LUT4_Z_10_B_LUT4_Z_2_A_PFUMX_Z_1_BLUT), + .C0(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] ), + .Z(\alu_output_LUT4_Z_10_B_LUT4_Z_2_A[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0316_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0317_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_1_Z) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0318_ ( + .ALUT(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_1_Z), + .BLUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_1_Z), + .C0(\alu_in_2[1] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_1_Z_PFUMX_ALUT_Z) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0319_ ( + .ALUT(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0320_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_C[3] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0321_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'h00cf) + ) _0322_ ( + .A(_0000_), + .B(\alu_output_PFUMX_Z_C0_LUT4_Z_B[0] ), + .C(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .D(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] ), + .Z(\alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0323_ ( + .A(_0000_), + .B(\alu_output_PFUMX_Z_C0_LUT4_Z_1_A[0] ), + .C(\alu_output_PFUMX_Z_C0_LUT4_Z_1_A[1] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .Z(\alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'h00f3) + ) _0324_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[1] ), + .C(\alu_output_PFUMX_Z_C0_LUT4_Z_A[1] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] ), + .Z(\alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0325_ ( + .ALUT(alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT), + .C0(\alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[4] ), + .Z(\alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h0305) + ) _0326_ ( + .A(\alu_output_LUT4_Z_1_B_LUT4_Z_1_A[2] ), + .B(\alu_output_LUT4_Z_1_B_LUT4_Z_1_A[3] ), + .C(\alu_in_2[3] ), + .D(\alu_in_2[2] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_2_A_PFUMX_Z_1_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h3faf) + ) _0327_ ( + .A(\alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] ), + .B(\alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[1] ), + .C(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] ), + .D(\alu_in_2[3] ), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0328_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0329_ ( + .ALUT(alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_C0_PFUMX_Z_BLUT), + .C0(\alu_output_PFUMX_Z_C0_PFUMX_Z_C0[4] ), + .Z(\alu_output_PFUMX_Z_C0[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h00f7) + ) _0330_ ( + .A(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] ), + .B(\alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[1] ), + .C(\alu_in_2[3] ), + .D(\alu_output_PFUMX_Z_C0_PFUMX_Z_C0[3] ), + .Z(alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0331_ ( + .D0(alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1), + .SD(\alu_op_i[2] ), + .Z(\alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0332_ ( + .ALUT(alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[23] ), + .Z(alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'hfff3) + ) _0333_ ( + .A(_0000_), + .B(\sum[23] ), + .C(\alu_op_i[1] ), + .D(\alu_op_i[0] ), + .Z(alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'hfff3) + ) _0334_ ( + .A(_0000_), + .B(\sum[23] ), + .C(\alu_op_i[1] ), + .D(\alu_op_i[0] ), + .Z(alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0335_ ( + .ALUT(alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[23] ), + .Z(alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h33f0) + ) _0336_ ( + .A(_0000_), + .B(\alu_op_i[1] ), + .C(\alu_op_i[0] ), + .D(\alu_in_1[23] ), + .Z(alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" *) + LUT4 #( + .INIT(16'hffff) + ) _0337_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0338_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_2_A_PFUMX_Z_1_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'hf0ff) + ) _0339_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_op_i[0] ), + .D(\alu_in_1[23] ), + .Z(alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hc500) + ) _0340_ ( + .A(\alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] ), + .B(\alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[1] ), + .C(\alu_in_2[3] ), + .D(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] ), + .Z(\alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'h3000) + ) _0341_ ( + .A(_0000_), + .B(\alu_in_2[3] ), + .C(\alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[1] ), + .D(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] ), + .Z(\alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0100) + ) _0342_ ( + .A(\alu_in_2[0] ), + .B(\alu_in_2[1] ), + .C(\alu_in_2[2] ), + .D(\alu_in_1[31] ), + .Z(\alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0343_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_C0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h007f) + ) _0344_ ( + .A(\alu_in_1[31] ), + .B(\alu_in_2[31] ), + .C(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ), + .D(\alu_output_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z_D[3] ), + .Z(\alu_output_PFUMX_Z_C0_PFUMX_Z_C0[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hcee0) + ) _0345_ ( + .A(\alu_output_LUT4_Z_7_A_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_7_A_LUT4_Z_A[1] ), + .C(\alu_in_1[31] ), + .D(\alu_in_2[31] ), + .Z(\alu_output_PFUMX_Z_C0_PFUMX_Z_C0[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0100) + ) _0346_ ( + .A(\alu_op_i[0] ), + .B(\alu_op_i[1] ), + .C(\alu_op_i[2] ), + .D(\sum[31] ), + .Z(\alu_output_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z_D[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _0347_ ( + .A0(_0000_), + .A1(_0000_), + .B0(\complement2_CCU2C_S0_B0[8] ), + .B1(\complement2_CCU2C_S0_B0[9] ), + .C0(_0000_), + .C1(_0000_), + .CIN(\complement2_CCU2C_S0_COUT[8] ), + .COUT(\complement2_CCU2C_S0_COUT[10] ), + .D0(_0001_), + .D1(_0001_), + .S0(\complement2[8] ), + .S1(\complement2[9] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _0348_ ( + .A0(_0000_), + .A1(_0000_), + .B0(\complement2_CCU2C_S0_B0[6] ), + .B1(\complement2_CCU2C_S0_B0[7] ), + .C0(_0000_), + .C1(_0000_), + .CIN(\complement2_CCU2C_S0_COUT[6] ), + .COUT(\complement2_CCU2C_S0_COUT[8] ), + .D0(_0001_), + .D1(_0001_), + .S0(\complement2[6] ), + .S1(\complement2[7] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'hf3f5) + ) _0349_ ( + .A(\alu_output_LUT4_Z_8_A_LUT4_Z_1_C[0] ), + .B(\alu_output_LUT4_Z_8_A_LUT4_Z_1_C[1] ), + .C(\alu_in_2[3] ), + .D(\alu_in_2[2] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_2_A_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _0350_ ( + .A0(_0000_), + .A1(_0000_), + .B0(\complement2_CCU2C_S0_B0[18] ), + .B1(\complement2_CCU2C_S0_B0[19] ), + .C0(_0000_), + .C1(_0000_), + .CIN(\complement2_CCU2C_S0_COUT[18] ), + .COUT(\complement2_CCU2C_S0_COUT[20] ), + .D0(_0001_), + .D1(_0001_), + .S0(\complement2[18] ), + .S1(\complement2[19] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _0351_ ( + .A0(_0000_), + .A1(_0000_), + .B0(\complement2_CCU2C_S0_B0[16] ), + .B1(\complement2_CCU2C_S0_B0[17] ), + .C0(_0000_), + .C1(_0000_), + .CIN(\complement2_CCU2C_S0_COUT[16] ), + .COUT(\complement2_CCU2C_S0_COUT[18] ), + .D0(_0001_), + .D1(_0001_), + .S0(\complement2[16] ), + .S1(\complement2[17] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _0352_ ( + .A0(_0000_), + .A1(_0000_), + .B0(\complement2_CCU2C_S0_B0[14] ), + .B1(\complement2_CCU2C_S0_B0[15] ), + .C0(_0000_), + .C1(_0000_), + .CIN(\complement2_CCU2C_S0_COUT[14] ), + .COUT(\complement2_CCU2C_S0_COUT[16] ), + .D0(_0001_), + .D1(_0001_), + .S0(\complement2[14] ), + .S1(\complement2[15] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _0353_ ( + .A0(_0000_), + .A1(_0000_), + .B0(\complement2_CCU2C_S0_B0[12] ), + .B1(\complement2_CCU2C_S0_B0[13] ), + .C0(_0000_), + .C1(_0000_), + .CIN(\complement2_CCU2C_S0_COUT[12] ), + .COUT(\complement2_CCU2C_S0_COUT[14] ), + .D0(_0001_), + .D1(_0001_), + .S0(\complement2[12] ), + .S1(\complement2[13] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _0354_ ( + .A0(_0000_), + .A1(_0000_), + .B0(\complement2_CCU2C_S0_B0[10] ), + .B1(\complement2_CCU2C_S0_B0[11] ), + .C0(_0000_), + .C1(_0000_), + .CIN(\complement2_CCU2C_S0_COUT[10] ), + .COUT(\complement2_CCU2C_S0_COUT[12] ), + .D0(_0001_), + .D1(_0001_), + .S0(\complement2[10] ), + .S1(\complement2[11] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _0355_ ( + .A0(_0001_), + .A1(_0000_), + .B0(\complement2_CCU2C_S0_B0[0] ), + .B1(\complement2_CCU2C_S0_B0[1] ), + .C0(_0000_), + .C1(_0000_), + .CIN(_0000_), + .COUT(\complement2_CCU2C_S0_COUT[2] ), + .D0(_0001_), + .D1(_0001_), + .S0(\complement2[0] ), + .S1(\complement2[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _0356_ ( + .A0(_0000_), + .A1(_0000_), + .B0(\complement2_CCU2C_S0_B0[4] ), + .B1(\complement2_CCU2C_S0_B0[5] ), + .C0(_0000_), + .C1(_0000_), + .CIN(\complement2_CCU2C_S0_COUT[4] ), + .COUT(\complement2_CCU2C_S0_COUT[6] ), + .D0(_0001_), + .D1(_0001_), + .S0(\complement2[4] ), + .S1(\complement2[5] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _0357_ ( + .A0(_0000_), + .A1(_0000_), + .B0(\complement2_CCU2C_S0_B0[30] ), + .B1(\complement2_CCU2C_S0_B0[31] ), + .C0(_0000_), + .C1(_0000_), + .CIN(\complement2_CCU2C_S0_COUT[30] ), + .COUT(\complement2_CCU2C_S0_3_COUT[31] ), + .D0(_0001_), + .D1(_0001_), + .S0(\complement2[30] ), + .S1(\complement2[31] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _0358_ ( + .A0(_0000_), + .A1(_0000_), + .B0(\complement2_CCU2C_S0_B0[2] ), + .B1(\complement2_CCU2C_S0_B0[3] ), + .C0(_0000_), + .C1(_0000_), + .CIN(\complement2_CCU2C_S0_COUT[2] ), + .COUT(\complement2_CCU2C_S0_COUT[4] ), + .D0(_0001_), + .D1(_0001_), + .S0(\complement2[2] ), + .S1(\complement2[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _0359_ ( + .A0(_0000_), + .A1(_0000_), + .B0(\complement2_CCU2C_S0_B0[28] ), + .B1(\complement2_CCU2C_S0_B0[29] ), + .C0(_0000_), + .C1(_0000_), + .CIN(\complement2_CCU2C_S0_COUT[28] ), + .COUT(\complement2_CCU2C_S0_COUT[30] ), + .D0(_0001_), + .D1(_0001_), + .S0(\complement2[28] ), + .S1(\complement2[29] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0360_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_2_A_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _0361_ ( + .A0(_0000_), + .A1(_0000_), + .B0(\complement2_CCU2C_S0_B0[26] ), + .B1(\complement2_CCU2C_S0_B0[27] ), + .C0(_0000_), + .C1(_0000_), + .CIN(\complement2_CCU2C_S0_COUT[26] ), + .COUT(\complement2_CCU2C_S0_COUT[28] ), + .D0(_0001_), + .D1(_0001_), + .S0(\complement2[26] ), + .S1(\complement2[27] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _0362_ ( + .A0(_0000_), + .A1(_0000_), + .B0(\complement2_CCU2C_S0_B0[24] ), + .B1(\complement2_CCU2C_S0_B0[25] ), + .C0(_0000_), + .C1(_0000_), + .CIN(\complement2_CCU2C_S0_COUT[24] ), + .COUT(\complement2_CCU2C_S0_COUT[26] ), + .D0(_0001_), + .D1(_0001_), + .S0(\complement2[24] ), + .S1(\complement2[25] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _0363_ ( + .A0(_0000_), + .A1(_0000_), + .B0(\complement2_CCU2C_S0_B0[22] ), + .B1(\complement2_CCU2C_S0_B0[23] ), + .C0(_0000_), + .C1(_0000_), + .CIN(\complement2_CCU2C_S0_COUT[22] ), + .COUT(\complement2_CCU2C_S0_COUT[24] ), + .D0(_0001_), + .D1(_0001_), + .S0(\complement2[22] ), + .S1(\complement2[23] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _0364_ ( + .A0(_0000_), + .A1(_0000_), + .B0(\complement2_CCU2C_S0_B0[20] ), + .B1(\complement2_CCU2C_S0_B0[21] ), + .C0(_0000_), + .C1(_0000_), + .CIN(\complement2_CCU2C_S0_COUT[20] ), + .COUT(\complement2_CCU2C_S0_COUT[22] ), + .D0(_0001_), + .D1(_0001_), + .S0(\complement2[20] ), + .S1(\complement2[21] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0365_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_2[29] ), + .Z(\complement2_CCU2C_S0_B0[29] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0366_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_2[31] ), + .Z(\complement2_CCU2C_S0_B0[31] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0367_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_2[21] ), + .Z(\complement2_CCU2C_S0_B0[21] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0368_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_2[20] ), + .Z(\complement2_CCU2C_S0_B0[20] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0369_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_2[19] ), + .Z(\complement2_CCU2C_S0_B0[19] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0370_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_2[18] ), + .Z(\complement2_CCU2C_S0_B0[18] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hcee0) + ) _0371_ ( + .A(\alu_output_LUT4_Z_7_A_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_7_A_LUT4_Z_A[1] ), + .C(\alu_in_1[8] ), + .D(\alu_in_2[8] ), + .Z(\alu_output_LUT4_Z_10_B_LUT4_Z_C[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0372_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_2[17] ), + .Z(\complement2_CCU2C_S0_B0[17] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0373_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_2[16] ), + .Z(\complement2_CCU2C_S0_B0[16] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0374_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_2[15] ), + .Z(\complement2_CCU2C_S0_B0[15] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0375_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_2[14] ), + .Z(\complement2_CCU2C_S0_B0[14] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0376_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_2[13] ), + .Z(\complement2_CCU2C_S0_B0[13] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0377_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_2[12] ), + .Z(\complement2_CCU2C_S0_B0[12] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0378_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_2[30] ), + .Z(\complement2_CCU2C_S0_B0[30] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0379_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_2[11] ), + .Z(\complement2_CCU2C_S0_B0[11] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0380_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_2[10] ), + .Z(\complement2_CCU2C_S0_B0[10] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0381_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_2[9] ), + .Z(\complement2_CCU2C_S0_B0[9] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hc000) + ) _0382_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ), + .C(\alu_in_1[8] ), + .D(\alu_in_2[8] ), + .Z(\alu_output_LUT4_Z_10_B_LUT4_Z_C[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0383_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_2[8] ), + .Z(\complement2_CCU2C_S0_B0[8] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0384_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_2[7] ), + .Z(\complement2_CCU2C_S0_B0[7] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0385_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_2[6] ), + .Z(\complement2_CCU2C_S0_B0[6] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0386_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_2[5] ), + .Z(\complement2_CCU2C_S0_B0[5] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0387_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_2[4] ), + .Z(\complement2_CCU2C_S0_B0[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0388_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_2[3] ), + .Z(\complement2_CCU2C_S0_B0[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0389_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_2[2] ), + .Z(\complement2_CCU2C_S0_B0[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0390_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_2[28] ), + .Z(\complement2_CCU2C_S0_B0[28] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0391_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_2[1] ), + .Z(\complement2_CCU2C_S0_B0[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0392_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_2[0] ), + .Z(\complement2_CCU2C_S0_B0[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hf2ff) + ) _0393_ ( + .A(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] ), + .B(\alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[0] ), + .C(\alu_output_LUT4_Z_11_C[2] ), + .D(\alu_output_LUT4_Z_11_C[3] ), + .Z(\alu_output[5] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0394_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_2[27] ), + .Z(\complement2_CCU2C_S0_B0[27] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0395_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_2[26] ), + .Z(\complement2_CCU2C_S0_B0[26] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0396_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_2[25] ), + .Z(\complement2_CCU2C_S0_B0[25] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0397_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_2[24] ), + .Z(\complement2_CCU2C_S0_B0[24] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0398_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_2[23] ), + .Z(\complement2_CCU2C_S0_B0[23] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0399_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_2[22] ), + .Z(\complement2_CCU2C_S0_B0[22] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0400_ ( + .A(_0000_), + .B(\alu_in_2[31] ), + .C(\complement2[31] ), + .D(\complement2_LUT4_C_D[2] ), + .Z(\sum_CCU2C_S0_B0[31] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0401_ ( + .A(_0000_), + .B(\alu_in_2[30] ), + .C(\complement2[30] ), + .D(\complement2_LUT4_C_D[2] ), + .Z(\sum_CCU2C_S0_B0[30] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0402_ ( + .A(_0000_), + .B(\alu_in_2[21] ), + .C(\complement2[21] ), + .D(\complement2_LUT4_C_D[2] ), + .Z(\sum_CCU2C_S0_B0[21] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0403_ ( + .A(_0000_), + .B(\alu_in_2[20] ), + .C(\complement2[20] ), + .D(\complement2_LUT4_C_D[2] ), + .Z(\sum_CCU2C_S0_B0[20] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0007) + ) _0404_ ( + .A(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ), + .B(\sum[5] ), + .C(\alu_output_LUT4_Z_11_C_LUT4_Z_C[2] ), + .D(\alu_output_LUT4_Z_11_C_LUT4_Z_C[3] ), + .Z(\alu_output_LUT4_Z_11_C[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0405_ ( + .A(_0000_), + .B(\alu_in_2[19] ), + .C(\complement2[19] ), + .D(\complement2_LUT4_C_D[2] ), + .Z(\sum_CCU2C_S0_B0[19] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0406_ ( + .A(_0000_), + .B(\alu_in_2[18] ), + .C(\complement2[18] ), + .D(\complement2_LUT4_C_D[2] ), + .Z(\sum_CCU2C_S0_B0[18] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0407_ ( + .A(_0000_), + .B(\alu_in_2[17] ), + .C(\complement2[17] ), + .D(\complement2_LUT4_C_D[2] ), + .Z(\sum_CCU2C_S0_B0[17] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0408_ ( + .A(_0000_), + .B(\alu_in_2[16] ), + .C(\complement2[16] ), + .D(\complement2_LUT4_C_D[2] ), + .Z(\sum_CCU2C_S0_B0[16] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0409_ ( + .A(_0000_), + .B(\alu_in_2[15] ), + .C(\complement2[15] ), + .D(\complement2_LUT4_C_D[2] ), + .Z(\sum_CCU2C_S0_B0[15] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0410_ ( + .A(_0000_), + .B(\alu_in_2[14] ), + .C(\complement2[14] ), + .D(\complement2_LUT4_C_D[2] ), + .Z(\sum_CCU2C_S0_B0[14] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0411_ ( + .A(_0000_), + .B(\alu_in_2[13] ), + .C(\complement2[13] ), + .D(\complement2_LUT4_C_D[2] ), + .Z(\sum_CCU2C_S0_B0[13] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0412_ ( + .A(_0000_), + .B(\alu_in_2[12] ), + .C(\complement2[12] ), + .D(\complement2_LUT4_C_D[2] ), + .Z(\sum_CCU2C_S0_B0[12] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0413_ ( + .A(_0000_), + .B(\alu_in_2[29] ), + .C(\complement2[29] ), + .D(\complement2_LUT4_C_D[2] ), + .Z(\sum_CCU2C_S0_B0[29] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0414_ ( + .A(_0000_), + .B(\alu_in_2[11] ), + .C(\complement2[11] ), + .D(\complement2_LUT4_C_D[2] ), + .Z(\sum_CCU2C_S0_B0[11] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hcee0) + ) _0415_ ( + .A(\alu_output_LUT4_Z_7_A_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_7_A_LUT4_Z_A[1] ), + .C(\alu_in_1[5] ), + .D(\alu_in_2[5] ), + .Z(\alu_output_LUT4_Z_11_C_LUT4_Z_C[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0416_ ( + .A(_0000_), + .B(\alu_in_2[10] ), + .C(\complement2[10] ), + .D(\complement2_LUT4_C_D[2] ), + .Z(\sum_CCU2C_S0_B0[10] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0417_ ( + .A(_0000_), + .B(\alu_in_2[9] ), + .C(\complement2[9] ), + .D(\complement2_LUT4_C_D[2] ), + .Z(\sum_CCU2C_S0_B0[9] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0418_ ( + .A(_0000_), + .B(\alu_in_2[8] ), + .C(\complement2[8] ), + .D(\complement2_LUT4_C_D[2] ), + .Z(\sum_CCU2C_S0_B0[8] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0419_ ( + .A(_0000_), + .B(\alu_in_2[7] ), + .C(\complement2[7] ), + .D(\complement2_LUT4_C_D[2] ), + .Z(\sum_CCU2C_S0_B0[7] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0420_ ( + .A(_0000_), + .B(\alu_in_2[6] ), + .C(\complement2[6] ), + .D(\complement2_LUT4_C_D[2] ), + .Z(\sum_CCU2C_S0_B0[6] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0421_ ( + .A(_0000_), + .B(\alu_in_2[5] ), + .C(\complement2[5] ), + .D(\complement2_LUT4_C_D[2] ), + .Z(\sum_CCU2C_S0_B0[5] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0422_ ( + .A(_0000_), + .B(\alu_in_2[4] ), + .C(\complement2[4] ), + .D(\complement2_LUT4_C_D[2] ), + .Z(\sum_CCU2C_S0_B0[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0423_ ( + .A(_0000_), + .B(\alu_in_2[3] ), + .C(\complement2[3] ), + .D(\complement2_LUT4_C_D[2] ), + .Z(\sum_CCU2C_S0_B0[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0424_ ( + .A(_0000_), + .B(\alu_in_2[2] ), + .C(\complement2[2] ), + .D(\complement2_LUT4_C_D[2] ), + .Z(\sum_CCU2C_S0_B0[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0425_ ( + .A(_0000_), + .B(\alu_in_2[28] ), + .C(\complement2[28] ), + .D(\complement2_LUT4_C_D[2] ), + .Z(\sum_CCU2C_S0_B0[28] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hc000) + ) _0426_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ), + .C(\alu_in_1[5] ), + .D(\alu_in_2[5] ), + .Z(\alu_output_LUT4_Z_11_C_LUT4_Z_C[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0427_ ( + .A(_0000_), + .B(\alu_in_2[1] ), + .C(\complement2[1] ), + .D(\complement2_LUT4_C_D[2] ), + .Z(\sum_CCU2C_S0_B0[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0428_ ( + .A(_0000_), + .B(\alu_in_2[0] ), + .C(\complement2[0] ), + .D(\complement2_LUT4_C_D[2] ), + .Z(\sum_CCU2C_S0_B0[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0429_ ( + .A(_0000_), + .B(\alu_in_2[27] ), + .C(\complement2[27] ), + .D(\complement2_LUT4_C_D[2] ), + .Z(\sum_CCU2C_S0_B0[27] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0430_ ( + .A(_0000_), + .B(\alu_in_2[26] ), + .C(\complement2[26] ), + .D(\complement2_LUT4_C_D[2] ), + .Z(\sum_CCU2C_S0_B0[26] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0431_ ( + .A(_0000_), + .B(\alu_in_2[25] ), + .C(\complement2[25] ), + .D(\complement2_LUT4_C_D[2] ), + .Z(\sum_CCU2C_S0_B0[25] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0432_ ( + .A(_0000_), + .B(\alu_in_2[24] ), + .C(\complement2[24] ), + .D(\complement2_LUT4_C_D[2] ), + .Z(\sum_CCU2C_S0_B0[24] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0433_ ( + .A(_0000_), + .B(\alu_in_2[23] ), + .C(\complement2[23] ), + .D(\complement2_LUT4_C_D[2] ), + .Z(\sum_CCU2C_S0_B0[23] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0434_ ( + .A(_0000_), + .B(\alu_in_2[22] ), + .C(\complement2[22] ), + .D(\complement2_LUT4_C_D[2] ), + .Z(\sum_CCU2C_S0_B0[22] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'h00cf) + ) _0435_ ( + .A(_0000_), + .B(\alu_op_i[0] ), + .C(\alu_op_i[1] ), + .D(\alu_op_i[3] ), + .Z(\complement2_LUT4_C_D[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _0436_ ( + .A0(\alu_in_1[8] ), + .A1(\alu_in_1[9] ), + .B0(\sum_CCU2C_S0_B0[8] ), + .B1(\sum_CCU2C_S0_B0[9] ), + .C0(_0000_), + .C1(_0000_), + .CIN(\sum_CCU2C_S0_COUT[8] ), + .COUT(\sum_CCU2C_S0_COUT[10] ), + .D0(_0001_), + .D1(_0001_), + .S0(\sum[8] ), + .S1(\sum[9] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0437_ ( + .ALUT(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_11_C_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] ), + .Z(\alu_output_LUT4_Z_11_C[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _0438_ ( + .A0(\alu_in_1[6] ), + .A1(\alu_in_1[7] ), + .B0(\sum_CCU2C_S0_B0[6] ), + .B1(\sum_CCU2C_S0_B0[7] ), + .C0(_0000_), + .C1(_0000_), + .CIN(\sum_CCU2C_S0_COUT[6] ), + .COUT(\sum_CCU2C_S0_COUT[8] ), + .D0(_0001_), + .D1(_0001_), + .S0(\sum[6] ), + .S1(\sum[7] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _0439_ ( + .A0(\alu_in_1[18] ), + .A1(\alu_in_1[19] ), + .B0(\sum_CCU2C_S0_B0[18] ), + .B1(\sum_CCU2C_S0_B0[19] ), + .C0(_0000_), + .C1(_0000_), + .CIN(\sum_CCU2C_S0_COUT[18] ), + .COUT(\sum_CCU2C_S0_COUT[20] ), + .D0(_0001_), + .D1(_0001_), + .S0(\sum[18] ), + .S1(\sum[19] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _0440_ ( + .A0(\alu_in_1[16] ), + .A1(\alu_in_1[17] ), + .B0(\sum_CCU2C_S0_B0[16] ), + .B1(\sum_CCU2C_S0_B0[17] ), + .C0(_0000_), + .C1(_0000_), + .CIN(\sum_CCU2C_S0_COUT[16] ), + .COUT(\sum_CCU2C_S0_COUT[18] ), + .D0(_0001_), + .D1(_0001_), + .S0(\sum[16] ), + .S1(\sum[17] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _0441_ ( + .A0(\alu_in_1[14] ), + .A1(\alu_in_1[15] ), + .B0(\sum_CCU2C_S0_B0[14] ), + .B1(\sum_CCU2C_S0_B0[15] ), + .C0(_0000_), + .C1(_0000_), + .CIN(\sum_CCU2C_S0_COUT[14] ), + .COUT(\sum_CCU2C_S0_COUT[16] ), + .D0(_0001_), + .D1(_0001_), + .S0(\sum[14] ), + .S1(\sum[15] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _0442_ ( + .A0(\alu_in_1[12] ), + .A1(\alu_in_1[13] ), + .B0(\sum_CCU2C_S0_B0[12] ), + .B1(\sum_CCU2C_S0_B0[13] ), + .C0(_0000_), + .C1(_0000_), + .CIN(\sum_CCU2C_S0_COUT[12] ), + .COUT(\sum_CCU2C_S0_COUT[14] ), + .D0(_0001_), + .D1(_0001_), + .S0(\sum[12] ), + .S1(\sum[13] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _0443_ ( + .A0(\alu_in_1[10] ), + .A1(\alu_in_1[11] ), + .B0(\sum_CCU2C_S0_B0[10] ), + .B1(\sum_CCU2C_S0_B0[11] ), + .C0(_0000_), + .C1(_0000_), + .CIN(\sum_CCU2C_S0_COUT[10] ), + .COUT(\sum_CCU2C_S0_COUT[12] ), + .D0(_0001_), + .D1(_0001_), + .S0(\sum[10] ), + .S1(\sum[11] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _0444_ ( + .A0(\alu_in_1[0] ), + .A1(\alu_in_1[1] ), + .B0(\sum_CCU2C_S0_B0[0] ), + .B1(\sum_CCU2C_S0_B0[1] ), + .C0(_0000_), + .C1(_0000_), + .CIN(_0000_), + .COUT(\sum_CCU2C_S0_COUT[2] ), + .D0(_0001_), + .D1(_0001_), + .S0(\sum[0] ), + .S1(\sum[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _0445_ ( + .A0(\alu_in_1[4] ), + .A1(\alu_in_1[5] ), + .B0(\sum_CCU2C_S0_B0[4] ), + .B1(\sum_CCU2C_S0_B0[5] ), + .C0(_0000_), + .C1(_0000_), + .CIN(\sum_CCU2C_S0_COUT[4] ), + .COUT(\sum_CCU2C_S0_COUT[6] ), + .D0(_0001_), + .D1(_0001_), + .S0(\sum[4] ), + .S1(\sum[5] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _0446_ ( + .A0(\alu_in_1[30] ), + .A1(\alu_in_1[31] ), + .B0(\sum_CCU2C_S0_B0[30] ), + .B1(\sum_CCU2C_S0_B0[31] ), + .C0(_0000_), + .C1(_0000_), + .CIN(\sum_CCU2C_S0_COUT[30] ), + .COUT(\sum_CCU2C_S0_3_COUT[31] ), + .D0(_0001_), + .D1(_0001_), + .S0(\sum[30] ), + .S1(\sum[31] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _0447_ ( + .A0(\alu_in_1[2] ), + .A1(\alu_in_1[3] ), + .B0(\sum_CCU2C_S0_B0[2] ), + .B1(\sum_CCU2C_S0_B0[3] ), + .C0(_0000_), + .C1(_0000_), + .CIN(\sum_CCU2C_S0_COUT[2] ), + .COUT(\sum_CCU2C_S0_COUT[4] ), + .D0(_0001_), + .D1(_0001_), + .S0(\sum[2] ), + .S1(\sum[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" *) + PFUMX _0448_ ( + .ALUT(alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[4] ), + .Z(alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h4f44) + ) _0449_ ( + .A(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] ), + .C(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A[2] ), + .D(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A[3] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _0450_ ( + .A0(\alu_in_1[28] ), + .A1(\alu_in_1[29] ), + .B0(\sum_CCU2C_S0_B0[28] ), + .B1(\sum_CCU2C_S0_B0[29] ), + .C0(_0000_), + .C1(_0000_), + .CIN(\sum_CCU2C_S0_COUT[28] ), + .COUT(\sum_CCU2C_S0_COUT[30] ), + .D0(_0001_), + .D1(_0001_), + .S0(\sum[28] ), + .S1(\sum[29] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _0451_ ( + .A0(\alu_in_1[26] ), + .A1(\alu_in_1[27] ), + .B0(\sum_CCU2C_S0_B0[26] ), + .B1(\sum_CCU2C_S0_B0[27] ), + .C0(_0000_), + .C1(_0000_), + .CIN(\sum_CCU2C_S0_COUT[26] ), + .COUT(\sum_CCU2C_S0_COUT[28] ), + .D0(_0001_), + .D1(_0001_), + .S0(\sum[26] ), + .S1(\sum[27] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _0452_ ( + .A0(\alu_in_1[24] ), + .A1(\alu_in_1[25] ), + .B0(\sum_CCU2C_S0_B0[24] ), + .B1(\sum_CCU2C_S0_B0[25] ), + .C0(_0000_), + .C1(_0000_), + .CIN(\sum_CCU2C_S0_COUT[24] ), + .COUT(\sum_CCU2C_S0_COUT[26] ), + .D0(_0001_), + .D1(_0001_), + .S0(\sum[24] ), + .S1(\sum[25] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _0453_ ( + .A0(\alu_in_1[22] ), + .A1(\alu_in_1[23] ), + .B0(\sum_CCU2C_S0_B0[22] ), + .B1(\sum_CCU2C_S0_B0[23] ), + .C0(_0000_), + .C1(_0000_), + .CIN(\sum_CCU2C_S0_COUT[22] ), + .COUT(\sum_CCU2C_S0_COUT[24] ), + .D0(_0001_), + .D1(_0001_), + .S0(\sum[22] ), + .S1(\sum[23] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _0454_ ( + .A0(\alu_in_1[20] ), + .A1(\alu_in_1[21] ), + .B0(\sum_CCU2C_S0_B0[20] ), + .B1(\sum_CCU2C_S0_B0[21] ), + .C0(_0000_), + .C1(_0000_), + .CIN(\sum_CCU2C_S0_COUT[20] ), + .COUT(\sum_CCU2C_S0_COUT[22] ), + .D0(_0001_), + .D1(_0001_), + .S0(\sum[20] ), + .S1(\sum[21] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0c0a) + ) _0455_ ( + .A(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[1] ), + .B(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B[0] ), + .C(\alu_in_2[3] ), + .D(\alu_in_2[2] ), + .Z(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0456_ ( + .D0(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0457_ ( + .ALUT(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0458_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[11] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0459_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[9] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0460_ ( + .ALUT(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0461_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[12] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0462_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[10] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hf0cc) + ) _0463_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B[0] ), + .C(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B[1] ), + .D(\alu_in_2[2] ), + .Z(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" *) + LUT4 #( + .INIT(16'hffff) + ) _0464_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0465_ ( + .D0(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0466_ ( + .ALUT(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0467_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[7] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0468_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[5] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0469_ ( + .ALUT(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0470_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[8] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0471_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[6] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'hf5f3) + ) _0472_ ( + .A(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A[0] ), + .B(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[2] ), + .C(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A[2] ), + .D(\alu_in_2[3] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'hf0cc) + ) _0473_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[0] ), + .C(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[1] ), + .D(\alu_in_2[2] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_1_Z) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hf0cc) + ) _0474_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[0] ), + .C(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[1] ), + .D(\alu_in_2[2] ), + .Z(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0475_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0476_ ( + .ALUT(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] ), + .Z(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h0305) + ) _0477_ ( + .A(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[2] ), + .B(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[3] ), + .C(\alu_in_2[3] ), + .D(\alu_in_2[2] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0478_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0479_ ( + .ALUT(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z), + .BLUT(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_BLUT), + .C0(\alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0480_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A[2] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0481_ ( + .D0(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_D0), + .D1(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z), + .SD(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] ), + .Z(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0482_ ( + .ALUT(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_D0_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0483_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0484_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hcee0) + ) _0485_ ( + .A(\alu_output_LUT4_Z_7_A_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_7_A_LUT4_Z_A[1] ), + .C(\alu_in_1[9] ), + .D(\alu_in_2[9] ), + .Z(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" *) + L6MUX21 _0486_ ( + .D0(alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D0), + .D1(alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D1), + .SD(\alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[5] ), + .Z(alu_output_L6MUX21_Z_2_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h001f) + ) _0487_ ( + .A(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[3] ), + .B(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[2] ), + .C(\alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] ), + .D(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_1_D[3] ), + .Z(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hc000) + ) _0488_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ), + .C(\alu_in_1[9] ), + .D(\alu_in_2[9] ), + .Z(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_1_D[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'h0003) + ) _0489_ ( + .A(_0000_), + .B(\alu_op_i[0] ), + .C(\alu_op_i[1] ), + .D(\alu_op_i[2] ), + .Z(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0490_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[2] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0491_ ( + .ALUT(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z), + .BLUT(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_1_Z), + .C0(\alu_in_2[3] ), + .Z(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0007) + ) _0492_ ( + .A(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ), + .B(\sum[1] ), + .C(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_C[2] ), + .D(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_C[3] ), + .Z(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[5] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" *) + LUT4 #( + .INIT(16'hf000) + ) _0493_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[1] ), + .Z(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" *) + LUT4 #( + .INIT(16'h0f00) + ) _0494_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[0] ), + .D(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] ), + .Z(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0495_ ( + .D0(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D1), + .SD(\alu_in_2[2] ), + .Z(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0496_ ( + .ALUT(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[3] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" *) + PFUMX _0497_ ( + .ALUT(alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[4] ), + .Z(alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0498_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[2] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0499_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[0] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0500_ ( + .ALUT(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[3] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0501_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[3] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0502_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[1] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hcee0) + ) _0503_ ( + .A(\alu_output_LUT4_Z_7_A_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_7_A_LUT4_Z_A[1] ), + .C(\alu_in_1[17] ), + .D(\alu_in_2[17] ), + .Z(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h007f) + ) _0504_ ( + .A(\alu_in_1[17] ), + .B(\alu_in_2[17] ), + .C(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ), + .D(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_LUT4_Z_1_D[3] ), + .Z(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0100) + ) _0505_ ( + .A(\alu_op_i[0] ), + .B(\alu_op_i[1] ), + .C(\alu_op_i[2] ), + .D(\sum[17] ), + .Z(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_LUT4_Z_1_D[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hc000) + ) _0506_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ), + .C(\alu_in_1[1] ), + .D(\alu_in_2[1] ), + .Z(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_C[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hcee0) + ) _0507_ ( + .A(\alu_output_LUT4_Z_7_A_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_7_A_LUT4_Z_A[1] ), + .C(\alu_in_1[1] ), + .D(\alu_in_2[1] ), + .Z(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_C[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" *) + LUT4 #( + .INIT(16'hffff) + ) _0508_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0509_ ( + .ALUT(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h0f33) + ) _0510_ ( + .A(_0000_), + .B(\alu_in_1[3] ), + .C(\alu_in_1[4] ), + .D(\alu_in_2[0] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0511_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z_D[2] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hf0cc) + ) _0512_ ( + .A(_0000_), + .B(\alu_in_1[1] ), + .C(\alu_in_1[2] ), + .D(\alu_in_2[0] ), + .Z(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z_D[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0513_ ( + .ALUT(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] ), + .Z(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0514_ ( + .ALUT(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_1_ALUT), + .BLUT(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_1_BLUT), + .C0(\alu_in_2[2] ), + .Z(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'hfff0) + ) _0515_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[2] ), + .D(\alu_in_2[3] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_1_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'hf0cc) + ) _0516_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[1] ), + .C(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[3] ), + .D(\alu_in_2[3] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_1_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h5f3f) + ) _0517_ ( + .A(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[0] ), + .B(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B[1] ), + .C(\alu_in_2[3] ), + .D(\alu_in_2[2] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0518_ ( + .D0(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0519_ ( + .D0(alu_output_L6MUX21_Z_1_D0), + .D1(alu_output_L6MUX21_Z_1_D1), + .SD(\alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[5] ), + .Z(\alu_output[7] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" *) + LUT4 #( + .INIT(16'hffff) + ) _0520_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0521_ ( + .ALUT(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0522_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[15] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0523_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[13] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0524_ ( + .ALUT(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0525_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[16] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0526_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[14] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0a0c) + ) _0527_ ( + .A(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[0] ), + .B(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B[1] ), + .C(\alu_in_2[3] ), + .D(\alu_in_2[2] ), + .Z(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0100) + ) _0528_ ( + .A(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[3] ), + .B(\alu_in_2[2] ), + .C(\alu_in_2[3] ), + .D(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] ), + .Z(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0529_ ( + .ALUT(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] ), + .Z(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h3f5f) + ) _0530_ ( + .A(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[1] ), + .B(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[2] ), + .C(\alu_in_2[3] ), + .D(\alu_in_2[2] ), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" *) + PFUMX _0531_ ( + .ALUT(alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[4] ), + .Z(alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0532_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0533_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0534_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_11_C_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hf8ff) + ) _0535_ ( + .A(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] ), + .B(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[0] ), + .C(\alu_output_LUT4_Z_12_C[2] ), + .D(\alu_output_LUT4_Z_12_C[3] ), + .Z(\alu_output[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0536_ ( + .D0(alu_output_LUT4_Z_12_C_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_12_C_L6MUX21_Z_D1), + .SD(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] ), + .Z(\alu_output_LUT4_Z_12_C[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0537_ ( + .ALUT(alu_output_LUT4_Z_12_C_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_12_C_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[4] ), + .Z(alu_output_LUT4_Z_12_C_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0538_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_12_C_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0539_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_12_C_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0540_ ( + .ALUT(alu_output_LUT4_Z_12_C_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_12_C_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[4] ), + .Z(alu_output_LUT4_Z_12_C_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h000f) + ) _0541_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_output_LUT4_Z_5_B_LUT4_Z_A[2] ), + .D(\alu_in_2[5] ), + .Z(alu_output_LUT4_Z_12_C_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" *) + LUT4 #( + .INIT(16'hffff) + ) _0542_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'h0003) + ) _0543_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_5_B_LUT4_Z_A[0] ), + .C(\alu_output_LUT4_Z_5_B_LUT4_Z_A[1] ), + .D(\alu_in_2[5] ), + .Z(alu_output_LUT4_Z_12_C_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0007) + ) _0544_ ( + .A(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ), + .B(\sum[2] ), + .C(\alu_output_LUT4_Z_12_C_LUT4_Z_C[2] ), + .D(\alu_output_LUT4_Z_12_C_LUT4_Z_C[3] ), + .Z(\alu_output_LUT4_Z_12_C[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hc000) + ) _0545_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ), + .C(\alu_in_1[2] ), + .D(\alu_in_2[2] ), + .Z(\alu_output_LUT4_Z_12_C_LUT4_Z_C[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hcee0) + ) _0546_ ( + .A(\alu_output_LUT4_Z_7_A_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_7_A_LUT4_Z_A[1] ), + .C(\alu_in_1[2] ), + .D(\alu_in_2[2] ), + .Z(\alu_output_LUT4_Z_12_C_LUT4_Z_C[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" *) + L6MUX21 _0547_ ( + .D0(alu_output_LUT4_Z_1_B_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_1_B_L6MUX21_Z_D1), + .SD(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] ), + .Z(\alu_output_LUT4_Z_1_B[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" *) + L6MUX21 _0548_ ( + .D0(alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D1), + .SD(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[5] ), + .Z(alu_output_LUT4_Z_1_B_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" *) + PFUMX _0549_ ( + .ALUT(alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] ), + .Z(alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" *) + LUT4 #( + .INIT(16'hffff) + ) _0550_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" *) + LUT4 #( + .INIT(16'hf000) + ) _0551_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] ), + .D(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[1] ), + .Z(alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" *) + PFUMX _0552_ ( + .ALUT(alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] ), + .Z(alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" *) + LUT4 #( + .INIT(16'h4f44) + ) _0553_ ( + .A(\alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[0] ), + .B(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] ), + .C(\alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[2] ), + .D(\alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[3] ), + .Z(alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" *) + LUT4 #( + .INIT(16'hffff) + ) _0554_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" *) + LUT4 #( + .INIT(16'hfff8) + ) _0555_ ( + .A(\alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] ), + .B(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[1] ), + .C(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[2] ), + .D(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[3] ), + .Z(alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" *) + L6MUX21 _0556_ ( + .D0(alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D1), + .SD(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[5] ), + .Z(alu_output_LUT4_Z_1_B_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" *) + PFUMX _0557_ ( + .ALUT(alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] ), + .Z(alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0558_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0559_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" *) + PFUMX _0560_ ( + .ALUT(alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] ), + .Z(alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0561_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0562_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0007) + ) _0563_ ( + .A(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ), + .B(\sum[28] ), + .C(\alu_output_LUT4_Z_1_B_LUT4_Z_C[2] ), + .D(\alu_output_LUT4_Z_1_B_LUT4_Z_C[3] ), + .Z(\alu_output_LUT4_Z_1_B[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0564_ ( + .D0(alu_output_L6MUX21_Z_3_D0), + .D1(alu_output_L6MUX21_Z_3_D1), + .SD(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[5] ), + .Z(\alu_output[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0100) + ) _0565_ ( + .A(\alu_output_LUT4_Z_1_B_LUT4_Z_1_A[3] ), + .B(\alu_in_2[2] ), + .C(\alu_in_2[3] ), + .D(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] ), + .Z(\alu_output_LUT4_Z_1_B[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0566_ ( + .D0(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(\alu_output_LUT4_Z_1_B_LUT4_Z_1_A[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0567_ ( + .D0(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D0), + .D1(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D1), + .SD(\alu_in_2[0] ), + .Z(\alu_output_LUT4_Z_1_B_LUT4_Z_1_A[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0568_ ( + .ALUT(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0569_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[26] ), + .Z(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0570_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[24] ), + .Z(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0571_ ( + .ALUT(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0572_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[27] ), + .Z(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0573_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[25] ), + .Z(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0574_ ( + .D0(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D0), + .D1(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D1), + .SD(\alu_in_2[0] ), + .Z(\alu_output_LUT4_Z_1_B_LUT4_Z_1_A[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0575_ ( + .ALUT(alu_output_L6MUX21_Z_3_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_L6MUX21_Z_3_D0_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[4] ), + .Z(alu_output_L6MUX21_Z_3_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0576_ ( + .ALUT(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0577_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[22] ), + .Z(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0578_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[20] ), + .Z(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0579_ ( + .ALUT(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0580_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[23] ), + .Z(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0581_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[21] ), + .Z(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0582_ ( + .D0(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D0), + .D1(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D1), + .SD(\alu_in_2[0] ), + .Z(\alu_output_LUT4_Z_1_B_LUT4_Z_1_A[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0583_ ( + .ALUT(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0584_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[18] ), + .Z(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0585_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[16] ), + .Z(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'hffff) + ) _0586_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_L6MUX21_Z_3_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0587_ ( + .ALUT(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0588_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[19] ), + .Z(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0589_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[17] ), + .Z(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0590_ ( + .ALUT(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0591_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[30] ), + .Z(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0592_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[28] ), + .Z(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0593_ ( + .ALUT(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0594_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[31] ), + .Z(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0595_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[29] ), + .Z(alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hc000) + ) _0596_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ), + .C(\alu_in_1[28] ), + .D(\alu_in_2[28] ), + .Z(\alu_output_LUT4_Z_1_B_LUT4_Z_C[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'hffff) + ) _0597_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_L6MUX21_Z_3_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hcee0) + ) _0598_ ( + .A(\alu_output_LUT4_Z_7_A_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_7_A_LUT4_Z_A[1] ), + .C(\alu_in_1[28] ), + .D(\alu_in_2[28] ), + .Z(\alu_output_LUT4_Z_1_B_LUT4_Z_C[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hfeff) + ) _0599_ ( + .A(\alu_output_LUT4_Z_2_A[0] ), + .B(\alu_output_LUT4_Z_2_A[1] ), + .C(\alu_output_LUT4_Z_2_A[2] ), + .D(\alu_output_LUT4_Z_2_A[3] ), + .Z(\alu_output[25] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" *) + L6MUX21 _0600_ ( + .D0(alu_output_LUT4_Z_2_A_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_2_A_L6MUX21_Z_D1), + .SD(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] ), + .Z(\alu_output_LUT4_Z_2_A[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" *) + L6MUX21 _0601_ ( + .D0(alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D1), + .SD(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] ), + .Z(alu_output_LUT4_Z_2_A_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" *) + PFUMX _0602_ ( + .ALUT(alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[4] ), + .Z(alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0603_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" *) + LUT4 #( + .INIT(16'h000f) + ) _0604_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[0] ), + .D(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[1] ), + .Z(alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" *) + PFUMX _0605_ ( + .ALUT(alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[4] ), + .Z(alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0606_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0607_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0608_ ( + .ALUT(alu_output_L6MUX21_Z_3_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_L6MUX21_Z_3_D1_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[4] ), + .Z(alu_output_L6MUX21_Z_3_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" *) + L6MUX21 _0609_ ( + .D0(alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D1), + .SD(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] ), + .Z(alu_output_LUT4_Z_2_A_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" *) + PFUMX _0610_ ( + .ALUT(alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[4] ), + .Z(alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0611_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" *) + LUT4 #( + .INIT(16'hfff0) + ) _0612_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[2] ), + .D(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[3] ), + .Z(alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" *) + PFUMX _0613_ ( + .ALUT(alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[4] ), + .Z(alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0614_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0615_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hcee0) + ) _0616_ ( + .A(\alu_output_LUT4_Z_7_A_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_7_A_LUT4_Z_A[1] ), + .C(\alu_in_1[25] ), + .D(\alu_in_2[25] ), + .Z(\alu_output_LUT4_Z_2_A[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0617_ ( + .ALUT(alu_output_LUT4_Z_2_A_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_2_A_PFUMX_Z_BLUT), + .C0(\sum[25] ), + .Z(\alu_output_LUT4_Z_2_A[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0618_ ( + .ALUT(alu_output_LUT4_Z_2_A_PFUMX_Z_1_ALUT), + .BLUT(alu_output_LUT4_Z_2_A_PFUMX_Z_1_BLUT), + .C0(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] ), + .Z(\alu_output_LUT4_Z_2_A[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'hffff) + ) _0619_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_L6MUX21_Z_3_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h0305) + ) _0620_ ( + .A(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[2] ), + .B(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[3] ), + .C(\alu_in_2[3] ), + .D(\alu_in_2[2] ), + .Z(alu_output_LUT4_Z_2_A_PFUMX_Z_1_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0621_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_2_A_PFUMX_Z_1_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h007f) + ) _0622_ ( + .A(\alu_in_2[25] ), + .B(\alu_in_1[25] ), + .C(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ), + .D(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ), + .Z(alu_output_LUT4_Z_2_A_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h3fff) + ) _0623_ ( + .A(_0000_), + .B(\alu_in_2[25] ), + .C(\alu_in_1[25] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ), + .Z(alu_output_LUT4_Z_2_A_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hf8ff) + ) _0624_ ( + .A(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ), + .B(\sum[20] ), + .C(\alu_output_LUT4_Z_3_C[2] ), + .D(\alu_output_LUT4_Z_3_C[3] ), + .Z(\alu_output[20] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" *) + L6MUX21 _0625_ ( + .D0(alu_output_LUT4_Z_3_C_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1), + .SD(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[4] ), + .Z(\alu_output_LUT4_Z_3_C[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" *) + L6MUX21 _0626_ ( + .D0(alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D1), + .SD(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] ), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" *) + PFUMX _0627_ ( + .ALUT(alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0628_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0629_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0630_ ( + .ALUT(alu_output_L6MUX21_Z_1_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_L6MUX21_Z_1_D0_PFUMX_Z_BLUT), + .C0(\alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[4] ), + .Z(alu_output_L6MUX21_Z_1_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'hf040) + ) _0631_ ( + .A(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[0] ), + .B(\alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] ), + .C(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] ), + .D(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[3] ), + .Z(alu_output_L6MUX21_Z_3_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" *) + PFUMX _0632_ ( + .ALUT(alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0633_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0634_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" *) + L6MUX21 _0635_ ( + .D0(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D1), + .SD(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] ), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" *) + PFUMX _0636_ ( + .ALUT(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0637_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[2] ), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0638_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] ), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h5300) + ) _0639_ ( + .A(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_A_L6MUX21_Z_SD[2] ), + .C(\alu_in_2[2] ), + .D(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .Z(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h5300) + ) _0640_ ( + .A(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A[0] ), + .B(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A[1] ), + .C(\alu_in_2[2] ), + .D(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .Z(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0641_ ( + .D0(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D1), + .SD(\alu_in_2[1] ), + .Z(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0642_ ( + .ALUT(alu_output_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[4] ), + .Z(alu_output_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0643_ ( + .D0(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D0), + .D1(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D1), + .SD(\alu_in_2[1] ), + .Z(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0644_ ( + .ALUT(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[0] ), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0645_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[7] ), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0646_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[8] ), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0647_ ( + .ALUT(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[0] ), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0648_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[5] ), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0649_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[6] ), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0650_ ( + .ALUT(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[0] ), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0651_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[11] ), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0652_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[12] ), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'hffff) + ) _0653_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0654_ ( + .ALUT(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[0] ), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0655_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[9] ), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0656_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[10] ), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" *) + L6MUX21 _0657_ ( + .D0(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1), + .SD(\alu_in_2[3] ), + .Z(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[5] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0658_ ( + .D0(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D0), + .D1(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D1), + .SD(\alu_in_2[1] ), + .Z(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0659_ ( + .ALUT(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[0] ), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0660_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[15] ), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0661_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[16] ), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0662_ ( + .ALUT(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[0] ), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0663_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[13] ), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'hffff) + ) _0664_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0665_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[14] ), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" *) + L6MUX21 _0666_ ( + .D0(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1), + .SD(\alu_in_2[4] ), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" *) + PFUMX _0667_ ( + .ALUT(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[31] ), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0668_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0669_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" *) + PFUMX _0670_ ( + .ALUT(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[31] ), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0671_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" *) + LUT4 #( + .INIT(16'hfeff) + ) _0672_ ( + .A(\alu_op_i[1] ), + .B(\alu_op_i[2] ), + .C(\alu_in_2[6] ), + .D(\alu_op_i[0] ), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" *) + L6MUX21 _0673_ ( + .D0(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1), + .SD(\alu_in_2[4] ), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" *) + PFUMX _0674_ ( + .ALUT(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[31] ), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0675_ ( + .ALUT(alu_output_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[4] ), + .Z(alu_output_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" *) + LUT4 #( + .INIT(16'h0100) + ) _0676_ ( + .A(\alu_op_i[1] ), + .B(\alu_op_i[2] ), + .C(\alu_in_2[6] ), + .D(\alu_op_i[0] ), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" *) + LUT4 #( + .INIT(16'h0100) + ) _0677_ ( + .A(\alu_op_i[1] ), + .B(\alu_op_i[2] ), + .C(\alu_in_2[6] ), + .D(\alu_op_i[0] ), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" *) + PFUMX _0678_ ( + .ALUT(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[31] ), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0679_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0680_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h5300) + ) _0681_ ( + .A(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A[1] ), + .B(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[0] ), + .C(\alu_in_2[2] ), + .D(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .Z(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_B_Z[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'h3f00) + ) _0682_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .C(\alu_in_2[5] ), + .D(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[5] ), + .Z(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hacff) + ) _0683_ ( + .A(\alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[1] ), + .B(\alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[2] ), + .C(\alu_in_2[1] ), + .D(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .Z(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hacff) + ) _0684_ ( + .A(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z_LUT4_Z_1_A[0] ), + .B(\alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[0] ), + .C(\alu_in_2[1] ), + .D(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .Z(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0685_ ( + .A(_0000_), + .B(\alu_in_1[19] ), + .C(\alu_in_1[20] ), + .D(\alu_in_2[0] ), + .Z(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z_LUT4_Z_1_A[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'hffff) + ) _0686_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" *) + PFUMX _0687_ ( + .ALUT(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0688_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" *) + LUT4 #( + .INIT(16'h000f) + ) _0689_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[0] ), + .D(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[1] ), + .Z(alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h000b) + ) _0690_ ( + .A(\alu_output_LUT4_Z_3_C_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] ), + .C(\alu_output_LUT4_Z_3_C_LUT4_Z_C[2] ), + .D(\alu_output_LUT4_Z_3_C_LUT4_Z_C[3] ), + .Z(\alu_output_LUT4_Z_3_C[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h4f44) + ) _0691_ ( + .A(\alu_output_LUT4_Z_3_C_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] ), + .C(\alu_output_LUT4_Z_3_C_LUT4_Z_A[2] ), + .D(\alu_output_LUT4_Z_3_C_LUT4_Z_A[3] ), + .Z(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0692_ ( + .ALUT(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z), + .BLUT(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_BLUT), + .C0(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] ), + .Z(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0693_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'h0300) + ) _0694_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A[3] ), + .C(\alu_in_2[2] ), + .D(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .Z(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'h3f00) + ) _0695_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[1] ), + .C(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .Z(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0007) + ) _0696_ ( + .A(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ), + .B(\sum[4] ), + .C(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[2] ), + .D(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[3] ), + .Z(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'h00fe) + ) _0697_ ( + .A(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[0] ), + .B(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[1] ), + .C(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[2] ), + .D(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] ), + .Z(alu_output_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hcee0) + ) _0698_ ( + .A(\alu_output_LUT4_Z_7_A_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_7_A_LUT4_Z_A[1] ), + .C(\alu_in_1[4] ), + .D(\alu_in_2[4] ), + .Z(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hc000) + ) _0699_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ), + .C(\alu_in_1[4] ), + .D(\alu_in_2[4] ), + .Z(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0c0a) + ) _0700_ ( + .A(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_8_A_LUT4_Z_1_C[0] ), + .C(\alu_in_2[3] ), + .D(\alu_in_2[2] ), + .Z(\alu_output_LUT4_Z_3_C_LUT4_Z_A[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0701_ ( + .D0(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" *) + L6MUX21 _0702_ ( + .D0(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0), + .D1(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1), + .SD(\alu_in_2[0] ), + .Z(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" *) + L6MUX21 _0703_ ( + .D0(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D1), + .SD(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" *) + PFUMX _0704_ ( + .ALUT(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[2] ), + .Z(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0705_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0706_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[0] ), + .Z(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" *) + PFUMX _0707_ ( + .ALUT(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[2] ), + .Z(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0bff) + ) _0708_ ( + .A(\alu_output_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_A[1] ), + .C(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] ), + .D(\alu_output_LUT4_Z_A[3] ), + .Z(\alu_output[29] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0709_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0710_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[2] ), + .Z(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" *) + L6MUX21 _0711_ ( + .D0(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D1), + .SD(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" *) + PFUMX _0712_ ( + .ALUT(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[2] ), + .Z(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0713_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0714_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[1] ), + .Z(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" *) + PFUMX _0715_ ( + .ALUT(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[2] ), + .Z(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0716_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0717_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[3] ), + .Z(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0718_ ( + .ALUT(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hfcff) + ) _0719_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_1_B[0] ), + .C(\alu_output_LUT4_Z_1_B[1] ), + .D(\alu_output_LUT4_Z_1_B[2] ), + .Z(\alu_output[28] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0720_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[6] ), + .Z(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0721_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[4] ), + .Z(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0722_ ( + .ALUT(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0723_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[7] ), + .Z(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0724_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[5] ), + .Z(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h000b) + ) _0725_ ( + .A(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A[0] ), + .B(\alu_in_2[2] ), + .C(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A[2] ), + .D(\alu_in_2[3] ), + .Z(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0726_ ( + .D0(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1), + .SD(\alu_in_2[2] ), + .Z(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0727_ ( + .ALUT(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[3] ), + .Z(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0728_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_1_B_LUT4_Z_1_A[2] ), + .Z(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0729_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_1_B_LUT4_Z_1_A[0] ), + .Z(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hfcff) + ) _0730_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_10_B[0] ), + .C(\alu_output_LUT4_Z_10_B[1] ), + .D(\alu_output_LUT4_Z_10_B[2] ), + .Z(\alu_output[8] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0731_ ( + .ALUT(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[3] ), + .Z(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0732_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_1_B_LUT4_Z_1_A[3] ), + .Z(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0733_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_1_B_LUT4_Z_1_A[1] ), + .Z(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" *) + LUT4 #( + .INIT(16'h0f00) + ) _0734_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_in_2[5] ), + .D(\alu_in_2[4] ), + .Z(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'h3000) + ) _0735_ ( + .A(_0000_), + .B(\alu_op_i[1] ), + .C(\alu_op_i[0] ), + .D(\alu_op_i[2] ), + .Z(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0736_ ( + .ALUT(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] ), + .Z(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h3f5f) + ) _0737_ ( + .A(\alu_output_LUT4_Z_8_A_LUT4_Z_1_C[0] ), + .B(\alu_output_LUT4_Z_8_A_LUT4_Z_1_C[1] ), + .C(\alu_in_2[3] ), + .D(\alu_in_2[2] ), + .Z(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0738_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0739_ ( + .ALUT(alu_output_LUT4_Z_3_C_LUT4_Z_A_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_3_C_LUT4_Z_A_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] ), + .Z(\alu_output_LUT4_Z_3_C_LUT4_Z_A[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0740_ ( + .ALUT(alu_output_LUT4_Z_3_C_LUT4_Z_A_PFUMX_Z_1_ALUT), + .BLUT(alu_output_LUT4_Z_3_C_LUT4_Z_A_PFUMX_Z_1_BLUT), + .C0(\alu_in_2[2] ), + .Z(\alu_output_LUT4_Z_3_C_LUT4_Z_A[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'hffff) + ) _0741_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_L6MUX21_Z_1_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0007) + ) _0742_ ( + .A(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ), + .B(\sum[8] ), + .C(\alu_output_LUT4_Z_10_B_LUT4_Z_C[2] ), + .D(\alu_output_LUT4_Z_10_B_LUT4_Z_C[3] ), + .Z(\alu_output_LUT4_Z_10_B[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'hfff0) + ) _0743_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_output_LUT4_Z_1_B_LUT4_Z_1_A[2] ), + .D(\alu_in_2[3] ), + .Z(alu_output_LUT4_Z_3_C_LUT4_Z_A_PFUMX_Z_1_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'hf0cc) + ) _0744_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_1_B_LUT4_Z_1_A[1] ), + .C(\alu_output_LUT4_Z_1_B_LUT4_Z_1_A[3] ), + .D(\alu_in_2[3] ), + .Z(alu_output_LUT4_Z_3_C_LUT4_Z_A_PFUMX_Z_1_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h5f3f) + ) _0745_ ( + .A(\alu_output_LUT4_Z_1_B_LUT4_Z_1_A[0] ), + .B(\alu_output_LUT4_Z_8_A_LUT4_Z_1_C[1] ), + .C(\alu_in_2[3] ), + .D(\alu_in_2[2] ), + .Z(alu_output_LUT4_Z_3_C_LUT4_Z_A_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0746_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_3_C_LUT4_Z_A_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hc000) + ) _0747_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ), + .C(\alu_in_1[20] ), + .D(\alu_in_2[20] ), + .Z(\alu_output_LUT4_Z_3_C_LUT4_Z_C[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hcee0) + ) _0748_ ( + .A(\alu_output_LUT4_Z_7_A_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_7_A_LUT4_Z_A[1] ), + .C(\alu_in_1[20] ), + .D(\alu_in_2[20] ), + .Z(\alu_output_LUT4_Z_3_C_LUT4_Z_C[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hf4ff) + ) _0749_ ( + .A(\alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[0] ), + .B(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] ), + .C(\alu_output_LUT4_Z_4_C[2] ), + .D(\alu_output_LUT4_Z_4_C[3] ), + .Z(\alu_output[19] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0750_ ( + .D0(alu_output_LUT4_Z_4_C_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_4_C_L6MUX21_Z_D1), + .SD(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[4] ), + .Z(\alu_output_LUT4_Z_4_C[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0751_ ( + .ALUT(alu_output_LUT4_Z_4_C_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_4_C_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .Z(alu_output_LUT4_Z_4_C_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0752_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_4_C_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hf100) + ) _0753_ ( + .A(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .B(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B[1] ), + .C(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B[2] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] ), + .Z(\alu_output_LUT4_Z_10_B[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0754_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_4_C_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0755_ ( + .ALUT(alu_output_LUT4_Z_4_C_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_4_C_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .Z(alu_output_LUT4_Z_4_C_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'hf0f3) + ) _0756_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_9_B_LUT4_Z_1_B[0] ), + .C(\alu_output_LUT4_Z_9_B_LUT4_Z_1_B[2] ), + .D(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] ), + .Z(alu_output_LUT4_Z_4_C_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'hf0f3) + ) _0757_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_9_B_LUT4_Z_1_B[1] ), + .C(\alu_output_LUT4_Z_9_B_LUT4_Z_1_B[2] ), + .D(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] ), + .Z(alu_output_LUT4_Z_4_C_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0758_ ( + .ALUT(alu_output_LUT4_Z_4_C_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_4_C_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_4_C_PFUMX_Z_C0[4] ), + .Z(\alu_output_LUT4_Z_4_C[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0759_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_4_C_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h0777) + ) _0760_ ( + .A(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ), + .B(\alu_output_LUT4_Z_4_C_PFUMX_Z_C0[1] ), + .C(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ), + .D(\sum[19] ), + .Z(alu_output_LUT4_Z_4_C_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" *) + LUT4 #( + .INIT(16'hf000) + ) _0761_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_in_1[19] ), + .D(\alu_in_2[19] ), + .Z(\alu_output_LUT4_Z_4_C_PFUMX_Z_C0[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hcee0) + ) _0762_ ( + .A(\alu_output_LUT4_Z_7_A_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_7_A_LUT4_Z_A[1] ), + .C(\alu_in_1[19] ), + .D(\alu_in_2[19] ), + .Z(\alu_output_LUT4_Z_4_C_PFUMX_Z_C0[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'h30ff) + ) _0763_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_5_B[0] ), + .C(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[4] ), + .D(\alu_output_LUT4_Z_5_B[2] ), + .Z(\alu_output[18] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hf5f3) + ) _0764_ ( + .A(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B[1] ), + .B(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_B_Z[0] ), + .C(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .Z(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hb000) + ) _0765_ ( + .A(\alu_output_LUT4_Z_5_B_LUT4_Z_A[2] ), + .B(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] ), + .C(\alu_output_LUT4_Z_5_B_LUT4_Z_C[2] ), + .D(\alu_output_LUT4_Z_5_B_LUT4_Z_C[3] ), + .Z(\alu_output_LUT4_Z_5_B[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0766_ ( + .D0(alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D1), + .SD(\alu_in_2[2] ), + .Z(\alu_output_LUT4_Z_5_B_LUT4_Z_A[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0767_ ( + .ALUT(alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[3] ), + .Z(alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0768_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[2] ), + .Z(alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0769_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[0] ), + .Z(alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0770_ ( + .ALUT(alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[3] ), + .Z(alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0771_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[3] ), + .Z(alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0772_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[1] ), + .Z(alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hca00) + ) _0773_ ( + .A(\alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z[1] ), + .B(\alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B[1] ), + .C(\alu_in_2[2] ), + .D(\alu_in_2[3] ), + .Z(\alu_output_LUT4_Z_5_B_LUT4_Z_A[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0774_ ( + .D0(alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(\alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" *) + LUT4 #( + .INIT(16'hf000) + ) _0775_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] ), + .D(\alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] ), + .Z(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0776_ ( + .ALUT(alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0777_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[16] ), + .Z(alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0778_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[14] ), + .Z(alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0779_ ( + .ALUT(alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0780_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[17] ), + .Z(alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0781_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[15] ), + .Z(alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0782_ ( + .A(_0000_), + .B(\alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[0] ), + .C(\alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B[1] ), + .D(\alu_in_2[2] ), + .Z(\alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0783_ ( + .D0(alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(\alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0784_ ( + .ALUT(alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0785_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[12] ), + .Z(alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0007) + ) _0786_ ( + .A(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ), + .B(\sum[16] ), + .C(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z_LUT4_Z_1_C[2] ), + .D(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z_LUT4_Z_1_C[3] ), + .Z(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0787_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[10] ), + .Z(alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0788_ ( + .ALUT(alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0789_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[13] ), + .Z(alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0790_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[11] ), + .Z(alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0791_ ( + .ALUT(alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT), + .C0(\alu_in_2[2] ), + .Z(\alu_output_LUT4_Z_5_B_LUT4_Z_A[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h00f0) + ) _0792_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B[2] ), + .D(\alu_in_2[3] ), + .Z(alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h0003) + ) _0793_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B[0] ), + .C(\alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B[1] ), + .D(\alu_in_2[3] ), + .Z(alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0794_ ( + .D0(alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(\alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0795_ ( + .ALUT(alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0796_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[8] ), + .Z(alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hc000) + ) _0797_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ), + .C(\alu_in_1[16] ), + .D(\alu_in_2[16] ), + .Z(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z_LUT4_Z_1_C[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0798_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[6] ), + .Z(alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0799_ ( + .ALUT(alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0800_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[9] ), + .Z(alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0801_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[7] ), + .Z(alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hca00) + ) _0802_ ( + .A(\alu_in_1[4] ), + .B(\alu_in_1[5] ), + .C(\alu_in_2[0] ), + .D(\alu_in_2[1] ), + .Z(\alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0c0a) + ) _0803_ ( + .A(\alu_in_1[2] ), + .B(\alu_in_1[3] ), + .C(\alu_in_2[1] ), + .D(\alu_in_2[0] ), + .Z(\alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h533f) + ) _0804_ ( + .A(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ), + .B(\alu_output_LUT4_Z_7_A_LUT4_Z_A[0] ), + .C(\alu_in_1[18] ), + .D(\alu_in_2[18] ), + .Z(\alu_output_LUT4_Z_5_B_LUT4_Z_C[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'h0f33) + ) _0805_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_5_B_LUT4_Z_C_LUT4_Z_1_B[0] ), + .C(\alu_in_2[18] ), + .D(\alu_output_LUT4_Z_7_A_LUT4_Z_A[1] ), + .Z(\alu_output_LUT4_Z_5_B_LUT4_Z_C[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0100) + ) _0806_ ( + .A(\alu_op_i[0] ), + .B(\alu_op_i[1] ), + .C(\alu_op_i[2] ), + .D(\sum[18] ), + .Z(\alu_output_LUT4_Z_5_B_LUT4_Z_C_LUT4_Z_1_B[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0807_ ( + .ALUT(alu_output_LUT4_Z_5_B_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_5_B_PFUMX_Z_BLUT), + .C0(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] ), + .Z(\alu_output_LUT4_Z_5_B[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hcee0) + ) _0808_ ( + .A(\alu_output_LUT4_Z_7_A_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_7_A_LUT4_Z_A[1] ), + .C(\alu_in_1[16] ), + .D(\alu_in_2[16] ), + .Z(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z_LUT4_Z_1_C[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'hff0f) + ) _0809_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[0] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .Z(alu_output_LUT4_Z_5_B_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0810_ ( + .A(_0000_), + .B(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[1] ), + .C(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[2] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .Z(alu_output_LUT4_Z_5_B_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hfeff) + ) _0811_ ( + .A(\alu_output_LUT4_Z_6_A[0] ), + .B(\alu_output_LUT4_Z_6_A[1] ), + .C(\alu_output_LUT4_Z_6_A[2] ), + .D(\alu_output_LUT4_Z_6_A[3] ), + .Z(\alu_output[15] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0812_ ( + .D0(alu_output_LUT4_Z_6_A_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1), + .SD(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] ), + .Z(\alu_output_LUT4_Z_6_A[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0813_ ( + .ALUT(alu_output_LUT4_Z_6_A_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_6_A_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] ), + .Z(alu_output_LUT4_Z_6_A_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0814_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_6_A_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0815_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_6_A_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0816_ ( + .ALUT(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] ), + .Z(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'hf5f3) + ) _0817_ ( + .A(\alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] ), + .B(\alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] ), + .C(\alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[2] ), + .D(\alu_in_2[3] ), + .Z(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0818_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[2] ), + .Z(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h00bf) + ) _0819_ ( + .A(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .B(\alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[1] ), + .C(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[2] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] ), + .Z(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0820_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[0] ), + .C(\alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[1] ), + .D(\alu_in_2[2] ), + .Z(\alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hf0cc) + ) _0821_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B[0] ), + .C(\alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[0] ), + .D(\alu_in_2[2] ), + .Z(\alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0822_ ( + .D0(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(\alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0823_ ( + .ALUT(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0824_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[25] ), + .Z(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0825_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[23] ), + .Z(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0826_ ( + .ALUT(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0827_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[26] ), + .Z(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0828_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[24] ), + .Z(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0829_ ( + .D0(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(\alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hf100) + ) _0830_ ( + .A(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .B(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B[1] ), + .C(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B[2] ), + .D(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[5] ), + .Z(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0831_ ( + .ALUT(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0832_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[21] ), + .Z(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0833_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[19] ), + .Z(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0834_ ( + .ALUT(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0835_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[22] ), + .Z(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0836_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[20] ), + .Z(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hf0cc) + ) _0837_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[0] ), + .C(\alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B[0] ), + .D(\alu_in_2[2] ), + .Z(\alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0838_ ( + .D0(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(\alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0839_ ( + .ALUT(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0840_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[29] ), + .Z(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'h003f) + ) _0841_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] ), + .C(\alu_op_i[3] ), + .D(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .Z(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0842_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[27] ), + .Z(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0843_ ( + .ALUT(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0844_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[30] ), + .Z(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0845_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[28] ), + .Z(alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'h0300) + ) _0846_ ( + .A(_0000_), + .B(\alu_in_2[0] ), + .C(\alu_in_2[1] ), + .D(\alu_in_1[31] ), + .Z(\alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hcee0) + ) _0847_ ( + .A(\alu_output_LUT4_Z_7_A_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_7_A_LUT4_Z_A[1] ), + .C(\alu_in_1[15] ), + .D(\alu_in_2[15] ), + .Z(\alu_output_LUT4_Z_6_A[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h5300) + ) _0848_ ( + .A(\alu_output_PFUMX_Z_C0_LUT4_Z_A[1] ), + .B(\alu_output_PFUMX_Z_C0_LUT4_Z_B[0] ), + .C(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] ), + .Z(\alu_output_LUT4_Z_6_A[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0849_ ( + .ALUT(alu_output_LUT4_Z_6_A_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_6_A_PFUMX_Z_BLUT), + .C0(\sum[15] ), + .Z(\alu_output_LUT4_Z_6_A[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h007f) + ) _0850_ ( + .A(\alu_in_2[15] ), + .B(\alu_in_1[15] ), + .C(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ), + .D(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ), + .Z(alu_output_LUT4_Z_6_A_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h3fff) + ) _0851_ ( + .A(_0000_), + .B(\alu_in_2[15] ), + .C(\alu_in_1[15] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ), + .Z(alu_output_LUT4_Z_6_A_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'hffff) + ) _0852_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_L6MUX21_Z_1_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0007) + ) _0853_ ( + .A(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ), + .B(\sum[24] ), + .C(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_LUT4_Z_1_C[2] ), + .D(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_LUT4_Z_1_C[3] ), + .Z(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[5] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hfeff) + ) _0854_ ( + .A(\alu_output_LUT4_Z_7_A[0] ), + .B(\alu_output_LUT4_Z_7_A[1] ), + .C(\alu_output_LUT4_Z_7_A[2] ), + .D(\alu_output_LUT4_Z_7_A[3] ), + .Z(\alu_output[13] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hcee0) + ) _0855_ ( + .A(\alu_output_LUT4_Z_7_A_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_7_A_LUT4_Z_A[1] ), + .C(\alu_in_1[13] ), + .D(\alu_in_2[13] ), + .Z(\alu_output_LUT4_Z_7_A[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hf400) + ) _0856_ ( + .A(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z[0] ), + .B(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z[1] ), + .C(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z[2] ), + .D(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] ), + .Z(\alu_output_LUT4_Z_7_A[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h5300) + ) _0857_ ( + .A(\alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[0] ), + .B(\alu_output_LUT4_Z_A_LUT4_Z_1_B[1] ), + .C(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] ), + .Z(\alu_output_LUT4_Z_7_A[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" *) + LUT4 #( + .INIT(16'h0f00) + ) _0858_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_op_i[0] ), + .D(\alu_op_i[2] ), + .Z(\alu_output_LUT4_Z_7_A_LUT4_Z_A[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'h3000) + ) _0859_ ( + .A(_0000_), + .B(\alu_op_i[0] ), + .C(\alu_op_i[1] ), + .D(\alu_op_i[2] ), + .Z(\alu_output_LUT4_Z_7_A_LUT4_Z_A[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0860_ ( + .ALUT(alu_output_LUT4_Z_7_A_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_7_A_PFUMX_Z_BLUT), + .C0(\sum[13] ), + .Z(\alu_output_LUT4_Z_7_A[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h007f) + ) _0861_ ( + .A(\alu_in_2[13] ), + .B(\alu_in_1[13] ), + .C(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ), + .D(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ), + .Z(alu_output_LUT4_Z_7_A_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h3fff) + ) _0862_ ( + .A(_0000_), + .B(\alu_in_2[13] ), + .C(\alu_in_1[13] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ), + .Z(alu_output_LUT4_Z_7_A_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hf4ff) + ) _0863_ ( + .A(\alu_output_LUT4_Z_8_A[0] ), + .B(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] ), + .C(\alu_output_LUT4_Z_8_A[2] ), + .D(\alu_output_LUT4_Z_8_A[3] ), + .Z(\alu_output[12] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hc000) + ) _0864_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ), + .C(\alu_in_1[24] ), + .D(\alu_in_2[24] ), + .Z(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_LUT4_Z_1_C[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0007) + ) _0865_ ( + .A(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ), + .B(\sum[12] ), + .C(\alu_output_LUT4_Z_8_A_LUT4_Z_C[2] ), + .D(\alu_output_LUT4_Z_8_A_LUT4_Z_C[3] ), + .Z(\alu_output_LUT4_Z_8_A[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h00ef) + ) _0866_ ( + .A(\alu_output_LUT4_Z_8_A_LUT4_Z_1_A[0] ), + .B(\alu_output_LUT4_Z_8_A_LUT4_Z_1_A[1] ), + .C(\alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] ), + .D(\alu_output_LUT4_Z_8_A_LUT4_Z_1_A[3] ), + .Z(\alu_output_LUT4_Z_8_A[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hca00) + ) _0867_ ( + .A(\alu_output_LUT4_Z_1_B_LUT4_Z_1_A[1] ), + .B(\alu_output_LUT4_Z_1_B_LUT4_Z_1_A[2] ), + .C(\alu_in_2[2] ), + .D(\alu_in_2[3] ), + .Z(\alu_output_LUT4_Z_8_A_LUT4_Z_1_A[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0a0c) + ) _0868_ ( + .A(\alu_output_LUT4_Z_1_B_LUT4_Z_1_A[0] ), + .B(\alu_output_LUT4_Z_8_A_LUT4_Z_1_C[1] ), + .C(\alu_in_2[3] ), + .D(\alu_in_2[2] ), + .Z(\alu_output_LUT4_Z_8_A_LUT4_Z_1_A[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0100) + ) _0869_ ( + .A(\alu_output_LUT4_Z_1_B_LUT4_Z_1_A[3] ), + .B(\alu_in_2[2] ), + .C(\alu_in_2[3] ), + .D(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] ), + .Z(\alu_output_LUT4_Z_8_A_LUT4_Z_1_A[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0870_ ( + .D0(alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(\alu_output_LUT4_Z_8_A_LUT4_Z_1_C[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0871_ ( + .D0(alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D0), + .D1(alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D1), + .SD(\alu_in_2[0] ), + .Z(\alu_output_LUT4_Z_8_A_LUT4_Z_1_C[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0872_ ( + .ALUT(alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0873_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[10] ), + .Z(alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0874_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[8] ), + .Z(alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hcee0) + ) _0875_ ( + .A(\alu_output_LUT4_Z_7_A_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_7_A_LUT4_Z_A[1] ), + .C(\alu_in_1[24] ), + .D(\alu_in_2[24] ), + .Z(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_LUT4_Z_1_C[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0876_ ( + .ALUT(alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0877_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[11] ), + .Z(alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0878_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[9] ), + .Z(alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0879_ ( + .ALUT(alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0880_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[14] ), + .Z(alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0881_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[12] ), + .Z(alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0882_ ( + .ALUT(alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0883_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[15] ), + .Z(alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0884_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[13] ), + .Z(alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" *) + LUT4 #( + .INIT(16'h000f) + ) _0885_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_in_2[4] ), + .D(\alu_in_2[5] ), + .Z(\alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" *) + LUT4 #( + .INIT(16'h0f00) + ) _0886_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_B_Z[0] ), + .D(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] ), + .Z(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hfc00) + ) _0887_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[2] ), + .C(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[3] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] ), + .Z(\alu_output_LUT4_Z_8_A[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hc000) + ) _0888_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ), + .C(\alu_in_1[12] ), + .D(\alu_in_2[12] ), + .Z(\alu_output_LUT4_Z_8_A_LUT4_Z_C[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hcee0) + ) _0889_ ( + .A(\alu_output_LUT4_Z_7_A_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_7_A_LUT4_Z_A[1] ), + .C(\alu_in_1[12] ), + .D(\alu_in_2[12] ), + .Z(\alu_output_LUT4_Z_8_A_LUT4_Z_C[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hfcff) + ) _0890_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_9_B[0] ), + .C(\alu_output_LUT4_Z_9_B[1] ), + .D(\alu_output_LUT4_Z_9_B[2] ), + .Z(\alu_output[11] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0891_ ( + .D0(alu_output_LUT4_Z_9_B_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1), + .SD(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] ), + .Z(\alu_output_LUT4_Z_9_B[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0892_ ( + .ALUT(alu_output_LUT4_Z_9_B_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_9_B_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] ), + .Z(alu_output_LUT4_Z_9_B_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0893_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_9_B_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0894_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_9_B_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0895_ ( + .ALUT(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] ), + .Z(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'hf5f3) + ) _0896_ ( + .A(\alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[2] ), + .B(\alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] ), + .C(\alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[2] ), + .D(\alu_in_2[3] ), + .Z(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0897_ ( + .ALUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] ), + .Z(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0898_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[2] ), + .Z(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'h3f00) + ) _0899_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] ), + .C(\alu_in_2[3] ), + .D(\alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] ), + .Z(\alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0007) + ) _0900_ ( + .A(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ), + .B(\sum[3] ), + .C(\alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_C[2] ), + .D(\alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_C[3] ), + .Z(\alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[5] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0c0a) + ) _0901_ ( + .A(\alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A[0] ), + .B(\alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A[0] ), + .C(\alu_in_2[3] ), + .D(\alu_in_2[2] ), + .Z(\alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0902_ ( + .ALUT(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(\alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h0f33) + ) _0903_ ( + .A(_0000_), + .B(\alu_in_1[5] ), + .C(\alu_in_1[6] ), + .D(\alu_in_2[0] ), + .Z(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0904_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_BLUT_LUT4_Z_D[2] ), + .Z(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hf0cc) + ) _0905_ ( + .A(_0000_), + .B(\alu_in_1[3] ), + .C(\alu_in_1[4] ), + .D(\alu_in_2[0] ), + .Z(\alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_BLUT_LUT4_Z_D[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hcee0) + ) _0906_ ( + .A(\alu_output_LUT4_Z_7_A_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_7_A_LUT4_Z_A[1] ), + .C(\alu_in_1[3] ), + .D(\alu_in_2[3] ), + .Z(\alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_C[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hc000) + ) _0907_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ), + .C(\alu_in_1[3] ), + .D(\alu_in_2[3] ), + .Z(\alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_C[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0908_ ( + .ALUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_PFUMX_Z_1_ALUT), + .BLUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_PFUMX_Z_1_BLUT), + .C0(\alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] ), + .Z(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0909_ ( + .ALUT(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] ), + .Z(\alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0910_ ( + .ALUT(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_Z_1_ALUT), + .BLUT(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_Z_1_BLUT), + .C0(\alu_in_2[3] ), + .Z(\alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h0fcc) + ) _0911_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[0] ), + .C(\alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[1] ), + .D(\alu_in_2[2] ), + .Z(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_Z_1_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0912_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[2] ), + .Z(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_Z_1_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h0503) + ) _0913_ ( + .A(\alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[0] ), + .B(\alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] ), + .C(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .D(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0914_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hf0cc) + ) _0915_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[0] ), + .C(\alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[1] ), + .D(\alu_in_2[2] ), + .Z(\alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0916_ ( + .D0(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(\alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0917_ ( + .D0(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D0), + .D1(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D1), + .SD(\alu_in_2[0] ), + .Z(\alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0918_ ( + .ALUT(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'hf3aa) + ) _0919_ ( + .A(\alu_output_LUT4_Z_A_L6MUX21_Z_SD[0] ), + .B(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .C(\alu_output_LUT4_Z_A_L6MUX21_Z_SD[2] ), + .D(\alu_in_2[2] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_PFUMX_Z_1_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0920_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[13] ), + .Z(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0921_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[11] ), + .Z(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0922_ ( + .ALUT(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0923_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[14] ), + .Z(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0924_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[12] ), + .Z(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0925_ ( + .ALUT(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0926_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[17] ), + .Z(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0927_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[15] ), + .Z(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0928_ ( + .ALUT(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0929_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[18] ), + .Z(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0930_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_PFUMX_Z_1_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _0931_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[16] ), + .Z(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _0932_ ( + .ALUT(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] ), + .Z(\alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h0c05) + ) _0933_ ( + .A(\alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[0] ), + .B(\alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[1] ), + .C(\alu_in_2[3] ), + .D(\alu_in_2[2] ), + .Z(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0934_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0007) + ) _0935_ ( + .A(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ), + .B(\sum[11] ), + .C(\alu_output_LUT4_Z_9_B_LUT4_Z_C[2] ), + .D(\alu_output_LUT4_Z_9_B_LUT4_Z_C[3] ), + .Z(\alu_output_LUT4_Z_9_B[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hf100) + ) _0936_ ( + .A(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .B(\alu_output_LUT4_Z_9_B_LUT4_Z_1_B[0] ), + .C(\alu_output_LUT4_Z_9_B_LUT4_Z_1_C[2] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] ), + .Z(\alu_output_LUT4_Z_9_B[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0937_ ( + .D0(alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D1), + .SD(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[0] ), + .Z(\alu_output_LUT4_Z_9_B_LUT4_Z_1_B[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0938_ ( + .D0(alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_1_D0), + .D1(alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_1_D1), + .SD(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .Z(\alu_output_LUT4_Z_9_B_LUT4_Z_1_B[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0939_ ( + .D0(alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_2_D0), + .D1(alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_2_D1), + .SD(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .Z(\alu_output_LUT4_Z_9_B_LUT4_Z_1_B[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0940_ ( + .ALUT(alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_2_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_2_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_2_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h0305) + ) _0941_ ( + .A(\alu_output_LUT4_Z_1_B_LUT4_Z_1_A[2] ), + .B(\alu_output_LUT4_Z_1_B_LUT4_Z_1_A[3] ), + .C(\alu_in_2[3] ), + .D(\alu_in_2[2] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0942_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[3] ), + .Z(alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_2_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0943_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] ), + .Z(alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_2_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0944_ ( + .ALUT(alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .Z(alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0945_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0946_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0947_ ( + .ALUT(alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .Z(alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0948_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'hafcf) + ) _0949_ ( + .A(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[2] ), + .B(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[1] ), + .C(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .D(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0950_ ( + .D0(alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D1), + .SD(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .Z(\alu_output_LUT4_Z_9_B_LUT4_Z_1_C[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0951_ ( + .ALUT(alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .Z(alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0952_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0953_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0954_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0955_ ( + .ALUT(alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .Z(alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0956_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'hafcf) + ) _0957_ ( + .A(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[2] ), + .B(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[1] ), + .C(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .D(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hcee0) + ) _0958_ ( + .A(\alu_output_LUT4_Z_7_A_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_7_A_LUT4_Z_A[1] ), + .C(\alu_in_1[11] ), + .D(\alu_in_2[11] ), + .Z(\alu_output_LUT4_Z_9_B_LUT4_Z_C[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hc000) + ) _0959_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ), + .C(\alu_in_1[11] ), + .D(\alu_in_2[11] ), + .Z(\alu_output_LUT4_Z_9_B_LUT4_Z_C[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0960_ ( + .D0(alu_output_LUT4_Z_A_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_A_L6MUX21_Z_D1), + .SD(\alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] ), + .Z(\alu_output_LUT4_Z_A[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0961_ ( + .ALUT(alu_output_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .Z(alu_output_LUT4_Z_A_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'hff0f) + ) _0962_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] ), + .D(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[3] ), + .Z(alu_output_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0963_ ( + .ALUT(alu_output_L6MUX21_Z_1_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_L6MUX21_Z_1_D1_PFUMX_Z_BLUT), + .C0(\alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[4] ), + .Z(alu_output_L6MUX21_Z_1_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h4000) + ) _0964_ ( + .A(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .B(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] ), + .C(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[1] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .Z(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'hff0f) + ) _0965_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] ), + .D(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[3] ), + .Z(alu_output_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0966_ ( + .ALUT(alu_output_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .Z(alu_output_LUT4_Z_A_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'hcc0c) + ) _0967_ ( + .A(_0000_), + .B(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[0] ), + .C(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] ), + .D(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[3] ), + .Z(alu_output_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'h3303) + ) _0968_ ( + .A(_0000_), + .B(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[1] ), + .C(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] ), + .D(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[3] ), + .Z(alu_output_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0969_ ( + .D0(alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D1), + .SD(\alu_in_2[1] ), + .Z(\alu_output_LUT4_Z_A_L6MUX21_Z_SD[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0970_ ( + .ALUT(alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[0] ), + .Z(alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0971_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[19] ), + .Z(alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0972_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[20] ), + .Z(alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _0973_ ( + .ALUT(alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[0] ), + .Z(alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0974_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[17] ), + .Z(alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h5300) + ) _0975_ ( + .A(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A[3] ), + .B(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A[0] ), + .C(\alu_in_2[2] ), + .D(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .Z(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0976_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[18] ), + .Z(alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hacff) + ) _0977_ ( + .A(\alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[0] ), + .B(\alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[1] ), + .C(\alu_in_2[1] ), + .D(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .Z(\alu_output_LUT4_Z_A_L6MUX21_Z_SD[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0007) + ) _0978_ ( + .A(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .B(\alu_in_2[5] ), + .C(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .D(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] ), + .Z(\alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0979_ ( + .A(_0000_), + .B(\alu_in_1[4] ), + .C(\alu_in_1[5] ), + .D(\alu_in_2[0] ), + .Z(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0980_ ( + .A(_0000_), + .B(\alu_in_1[2] ), + .C(\alu_in_1[3] ), + .D(\alu_in_2[0] ), + .Z(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _0981_ ( + .A(_0000_), + .B(\alu_in_1[0] ), + .C(\alu_in_1[1] ), + .D(\alu_in_2[0] ), + .Z(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0100) + ) _0982_ ( + .A(\alu_op_i[1] ), + .B(\alu_op_i[2] ), + .C(\alu_in_2[6] ), + .D(\alu_op_i[0] ), + .Z(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0700) + ) _0983_ ( + .A(\alu_output_LUT4_Z_A_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] ), + .C(\alu_output_LUT4_Z_A_LUT4_Z_A[2] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_A[3] ), + .Z(\alu_output_LUT4_Z_A[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h5300) + ) _0984_ ( + .A(\alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[0] ), + .B(\alu_output_LUT4_Z_A_LUT4_Z_1_B[1] ), + .C(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .D(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[5] ), + .Z(\alu_output_LUT4_Z_A[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0985_ ( + .D0(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1), + .SD(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .Z(\alu_output_LUT4_Z_A_LUT4_Z_1_B[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _0986_ ( + .D0(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1), + .SD(\alu_in_2[1] ), + .Z(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0987_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'hff00) + ) _0988_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" *) + L6MUX21 _0989_ ( + .D0(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1), + .SD(\alu_op_i[0] ), + .Z(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" *) + L6MUX21 _0990_ ( + .D0(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" *) + PFUMX _0991_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0992_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0993_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" *) + PFUMX _0994_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0995_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" *) + LUT4 #( + .INIT(16'h0000) + ) _0996_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _0997_ ( + .ALUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[0] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" *) + L6MUX21 _0998_ ( + .D0(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" *) + PFUMX _0999_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1000_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" *) + LUT4 #( + .INIT(16'h0003) + ) _1001_ ( + .A(_0000_), + .B(\alu_in_1[11] ), + .C(\alu_op_i[2] ), + .D(\alu_in_2[6] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" *) + PFUMX _1002_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1003_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" *) + LUT4 #( + .INIT(16'h0003) + ) _1004_ ( + .A(_0000_), + .B(\alu_in_1[10] ), + .C(\alu_op_i[2] ), + .D(\alu_in_2[6] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'hff00) + ) _1005_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'hff00) + ) _1006_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_1_Z) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _1007_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_1_Z_PFUMX_BLUT_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_1_Z), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_2_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'hff00) + ) _1008_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[3] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'hff00) + ) _1009_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_C[3] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_1_Z_PFUMX_BLUT_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _1010_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_1_Z), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _1011_ ( + .D0(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_1_Z_PFUMX_ALUT_Z), + .D1(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z), + .SD(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .Z(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _1012_ ( + .D0(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1), + .SD(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .Z(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _1013_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'hff00) + ) _1014_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'hff00) + ) _1015_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_C[3] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _1016_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'hff00) + ) _1017_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'hff00) + ) _1018_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[3] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'hff00) + ) _1019_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[4] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0503) + ) _1020_ ( + .A(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ), + .B(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[1] ), + .C(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .Z(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" *) + L6MUX21 _1021_ ( + .D0(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1), + .SD(\alu_in_2[4] ), + .Z(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _1022_ ( + .D0(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D0), + .D1(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D1), + .SD(\alu_op_i[0] ), + .Z(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _1023_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D0_PFUMX_Z_BLUT), + .C0(\alu_op_i[2] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1024_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1025_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _1026_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D1_PFUMX_Z_BLUT), + .C0(\alu_op_i[2] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h00f0) + ) _1027_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_op_i[3] ), + .D(\alu_op_i[1] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'h0003) + ) _1028_ ( + .A(_0000_), + .B(\alu_in_2[5] ), + .C(\alu_in_2[6] ), + .D(\alu_op_i[1] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" *) + L6MUX21 _1029_ ( + .D0(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D1), + .SD(\alu_in_2[3] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _1030_ ( + .ALUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[0] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" *) + PFUMX _1031_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[31] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1032_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1033_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" *) + PFUMX _1034_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[31] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1035_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" *) + LUT4 #( + .INIT(16'hfeff) + ) _1036_ ( + .A(\alu_op_i[1] ), + .B(\alu_op_i[2] ), + .C(\alu_in_2[6] ), + .D(\alu_op_i[0] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" *) + L6MUX21 _1037_ ( + .D0(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D1), + .SD(\alu_in_2[3] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" *) + PFUMX _1038_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[31] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" *) + LUT4 #( + .INIT(16'h0100) + ) _1039_ ( + .A(\alu_op_i[1] ), + .B(\alu_op_i[2] ), + .C(\alu_in_2[6] ), + .D(\alu_op_i[0] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" *) + LUT4 #( + .INIT(16'h0100) + ) _1040_ ( + .A(\alu_op_i[1] ), + .B(\alu_op_i[2] ), + .C(\alu_in_2[6] ), + .D(\alu_op_i[0] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'hff00) + ) _1041_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[1] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" *) + PFUMX _1042_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[31] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1043_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1044_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'h0300) + ) _1045_ ( + .A(_0000_), + .B(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] ), + .C(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[4] ), + .Z(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _1046_ ( + .D0(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D1), + .SD(\alu_in_2[2] ), + .Z(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _1047_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[31] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1048_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'hfeff) + ) _1049_ ( + .A(\alu_op_i[1] ), + .B(\alu_op_i[2] ), + .C(\alu_in_2[6] ), + .D(\alu_op_i[0] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _1050_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[31] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h0100) + ) _1051_ ( + .A(\alu_op_i[1] ), + .B(\alu_op_i[2] ), + .C(\alu_in_2[6] ), + .D(\alu_op_i[0] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'hff00) + ) _1052_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[2] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'h0100) + ) _1053_ ( + .A(\alu_op_i[1] ), + .B(\alu_op_i[2] ), + .C(\alu_in_2[6] ), + .D(\alu_op_i[0] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hfc00) + ) _1054_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B[0] ), + .C(\alu_op_i[2] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B[2] ), + .Z(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" *) + LUT4 #( + .INIT(16'hf000) + ) _1055_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[1] ), + .D(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] ), + .Z(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _1056_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _1057_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_1_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_1_BLUT), + .C0(\alu_op_i[2] ), + .Z(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h5ccf) + ) _1058_ ( + .A(\alu_op_i[1] ), + .B(\alu_op_i[0] ), + .C(\alu_in_1[0] ), + .D(\alu_in_2[0] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_1_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'hffff) + ) _1059_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_1_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'hcc0f) + ) _1060_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B[0] ), + .C(\sum[31] ), + .D(\alu_op_i[0] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _1061_ ( + .A0(\alu_in_1[30] ), + .A1(\alu_in_1[31] ), + .B0(\alu_in_2[30] ), + .B1(\alu_in_2[31] ), + .C0(_0001_), + .C1(_0001_), + .CIN(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[30] ), + .COUT(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B[0] ), + .D0(_0001_), + .D1(_0001_), + .S0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[30] ), + .S1(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[31] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _1062_ ( + .A0(\alu_in_1[8] ), + .A1(\alu_in_1[9] ), + .B0(\alu_in_2[8] ), + .B1(\alu_in_2[9] ), + .C0(_0001_), + .C1(_0001_), + .CIN(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[8] ), + .COUT(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[10] ), + .D0(_0001_), + .D1(_0001_), + .S0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[8] ), + .S1(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[9] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'hff0f) + ) _1063_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .D(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A[3] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _1064_ ( + .A0(\alu_in_1[6] ), + .A1(\alu_in_1[7] ), + .B0(\alu_in_2[6] ), + .B1(\alu_in_2[7] ), + .C0(_0001_), + .C1(_0001_), + .CIN(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[6] ), + .COUT(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[8] ), + .D0(_0001_), + .D1(_0001_), + .S0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[6] ), + .S1(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[7] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _1065_ ( + .A0(\alu_in_1[16] ), + .A1(\alu_in_1[17] ), + .B0(\alu_in_2[16] ), + .B1(\alu_in_2[17] ), + .C0(_0001_), + .C1(_0001_), + .CIN(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[16] ), + .COUT(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[18] ), + .D0(_0001_), + .D1(_0001_), + .S0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[16] ), + .S1(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[17] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _1066_ ( + .A0(\alu_in_1[14] ), + .A1(\alu_in_1[15] ), + .B0(\alu_in_2[14] ), + .B1(\alu_in_2[15] ), + .C0(_0001_), + .C1(_0001_), + .CIN(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[14] ), + .COUT(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[16] ), + .D0(_0001_), + .D1(_0001_), + .S0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[14] ), + .S1(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[15] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _1067_ ( + .A0(\alu_in_1[12] ), + .A1(\alu_in_1[13] ), + .B0(\alu_in_2[12] ), + .B1(\alu_in_2[13] ), + .C0(_0001_), + .C1(_0001_), + .CIN(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[12] ), + .COUT(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[14] ), + .D0(_0001_), + .D1(_0001_), + .S0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[12] ), + .S1(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[13] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _1068_ ( + .A0(\alu_in_1[10] ), + .A1(\alu_in_1[11] ), + .B0(\alu_in_2[10] ), + .B1(\alu_in_2[11] ), + .C0(_0001_), + .C1(_0001_), + .CIN(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[10] ), + .COUT(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[12] ), + .D0(_0001_), + .D1(_0001_), + .S0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[10] ), + .S1(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[11] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _1069_ ( + .A0(\alu_in_1[0] ), + .A1(\alu_in_1[1] ), + .B0(\alu_in_2[0] ), + .B1(\alu_in_2[1] ), + .C0(_0001_), + .C1(_0001_), + .CIN(_0001_), + .COUT(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[2] ), + .D0(_0001_), + .D1(_0001_), + .S0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[0] ), + .S1(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _1070_ ( + .A0(\alu_in_1[4] ), + .A1(\alu_in_1[5] ), + .B0(\alu_in_2[4] ), + .B1(\alu_in_2[5] ), + .C0(_0001_), + .C1(_0001_), + .CIN(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[4] ), + .COUT(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[6] ), + .D0(_0001_), + .D1(_0001_), + .S0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[4] ), + .S1(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[5] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _1071_ ( + .A0(\alu_in_1[2] ), + .A1(\alu_in_1[3] ), + .B0(\alu_in_2[2] ), + .B1(\alu_in_2[3] ), + .C0(_0001_), + .C1(_0001_), + .CIN(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[2] ), + .COUT(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[4] ), + .D0(_0001_), + .D1(_0001_), + .S0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[2] ), + .S1(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _1072_ ( + .A0(\alu_in_1[28] ), + .A1(\alu_in_1[29] ), + .B0(\alu_in_2[28] ), + .B1(\alu_in_2[29] ), + .C0(_0001_), + .C1(_0001_), + .CIN(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[28] ), + .COUT(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[30] ), + .D0(_0001_), + .D1(_0001_), + .S0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[28] ), + .S1(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[29] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _1073_ ( + .A0(\alu_in_1[26] ), + .A1(\alu_in_1[27] ), + .B0(\alu_in_2[26] ), + .B1(\alu_in_2[27] ), + .C0(_0001_), + .C1(_0001_), + .CIN(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[26] ), + .COUT(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[28] ), + .D0(_0001_), + .D1(_0001_), + .S0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[26] ), + .S1(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[27] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'hffff) + ) _1074_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_L6MUX21_Z_1_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _1075_ ( + .ALUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_ALUT), + .BLUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _1076_ ( + .A0(\alu_in_1[24] ), + .A1(\alu_in_1[25] ), + .B0(\alu_in_2[24] ), + .B1(\alu_in_2[25] ), + .C0(_0001_), + .C1(_0001_), + .CIN(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[24] ), + .COUT(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[26] ), + .D0(_0001_), + .D1(_0001_), + .S0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[24] ), + .S1(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[25] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _1077_ ( + .A0(\alu_in_1[22] ), + .A1(\alu_in_1[23] ), + .B0(\alu_in_2[22] ), + .B1(\alu_in_2[23] ), + .C0(_0001_), + .C1(_0001_), + .CIN(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[22] ), + .COUT(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[24] ), + .D0(_0001_), + .D1(_0001_), + .S0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[22] ), + .S1(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[23] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _1078_ ( + .A0(\alu_in_1[20] ), + .A1(\alu_in_1[21] ), + .B0(\alu_in_2[20] ), + .B1(\alu_in_2[21] ), + .C0(_0001_), + .C1(_0001_), + .CIN(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[20] ), + .COUT(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[22] ), + .D0(_0001_), + .D1(_0001_), + .S0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[20] ), + .S1(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[21] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" *) + CCU2C #( + .INIT0(16'h96aa), + .INIT1(16'h96aa), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) _1079_ ( + .A0(\alu_in_1[18] ), + .A1(\alu_in_1[19] ), + .B0(\alu_in_2[18] ), + .B1(\alu_in_2[19] ), + .C0(_0001_), + .C1(_0001_), + .CIN(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[18] ), + .COUT(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[20] ), + .D0(_0001_), + .D1(_0001_), + .S0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[18] ), + .S1(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[19] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'hff0f) + ) _1080_ ( + .A(_0000_), + .B(_0000_), + .C(\sum[0] ), + .D(\alu_op_i[0] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _1081_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] ), + .Z(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h4f44) + ) _1082_ ( + .A(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[0] ), + .B(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] ), + .C(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[2] ), + .D(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[3] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1083_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0b00) + ) _1084_ ( + .A(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[0] ), + .B(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] ), + .C(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[2] ), + .D(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[3] ), + .Z(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0d00) + ) _1085_ ( + .A(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .B(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[2] ), + .C(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .D(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] ), + .Z(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'hf000) + ) _1086_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] ), + .D(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[1] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'hff00) + ) _1087_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" *) + L6MUX21 _1088_ ( + .D0(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1), + .SD(\alu_op_i[0] ), + .Z(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" *) + L6MUX21 _1089_ ( + .D0(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" *) + PFUMX _1090_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1091_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1092_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" *) + PFUMX _1093_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1094_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1095_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" *) + L6MUX21 _1096_ ( + .D0(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _1097_ ( + .D0(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0), + .D1(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z), + .SD(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .Z(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" *) + PFUMX _1098_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1099_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" *) + LUT4 #( + .INIT(16'h0003) + ) _1100_ ( + .A(_0000_), + .B(\alu_in_1[13] ), + .C(\alu_op_i[2] ), + .D(\alu_in_2[6] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" *) + PFUMX _1101_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1102_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" *) + LUT4 #( + .INIT(16'h0003) + ) _1103_ ( + .A(_0000_), + .B(\alu_in_1[12] ), + .C(\alu_op_i[2] ), + .D(\alu_in_2[6] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'hff00) + ) _1104_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'hff00) + ) _1105_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_1_Z) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _1106_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z), + .BLUT(alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_1_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _1107_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _1108_ ( + .ALUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'hff00) + ) _1109_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" *) + L6MUX21 _1110_ ( + .D0(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1), + .SD(\alu_op_i[0] ), + .Z(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" *) + L6MUX21 _1111_ ( + .D0(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0), + .D1(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1), + .SD(\alu_op_i[0] ), + .Z(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" *) + L6MUX21 _1112_ ( + .D0(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" *) + PFUMX _1113_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1114_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1115_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" *) + PFUMX _1116_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1117_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1118_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1119_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" *) + L6MUX21 _1120_ ( + .D0(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" *) + PFUMX _1121_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1122_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" *) + LUT4 #( + .INIT(16'h0003) + ) _1123_ ( + .A(_0000_), + .B(\alu_in_1[5] ), + .C(\alu_op_i[2] ), + .D(\alu_in_2[6] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" *) + PFUMX _1124_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1125_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" *) + LUT4 #( + .INIT(16'h0003) + ) _1126_ ( + .A(_0000_), + .B(\alu_in_1[4] ), + .C(\alu_op_i[2] ), + .D(\alu_in_2[6] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" *) + L6MUX21 _1127_ ( + .D0(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" *) + PFUMX _1128_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1129_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1130_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1131_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" *) + PFUMX _1132_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1133_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1134_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" *) + L6MUX21 _1135_ ( + .D0(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" *) + PFUMX _1136_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1137_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" *) + LUT4 #( + .INIT(16'h0003) + ) _1138_ ( + .A(_0000_), + .B(\alu_in_1[7] ), + .C(\alu_op_i[2] ), + .D(\alu_in_2[6] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" *) + PFUMX _1139_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1140_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" *) + L6MUX21 _1141_ ( + .D0(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1), + .SD(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .Z(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" *) + LUT4 #( + .INIT(16'h0003) + ) _1142_ ( + .A(_0000_), + .B(\alu_in_1[6] ), + .C(\alu_op_i[2] ), + .D(\alu_in_2[6] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'hff00) + ) _1143_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_C[3] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hf5f3) + ) _1144_ ( + .A(\alu_output_LUT4_Z_A_LUT4_Z_1_B[1] ), + .B(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[3] ), + .C(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .Z(\alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _1145_ ( + .D0(alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D1), + .SD(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .Z(\alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _1146_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1147_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'hff00) + ) _1148_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _1149_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h0f33) + ) _1150_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[0] ), + .C(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[2] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'hff0f) + ) _1151_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[1] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _1152_ ( + .D0(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0), + .D1(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1), + .SD(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[5] ), + .Z(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" *) + LUT4 #( + .INIT(16'h0f00) + ) _1153_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[4] ), + .Z(\alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" *) + LUT4 #( + .INIT(16'h0f00) + ) _1154_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[4] ), + .Z(\alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _1155_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0[4] ), + .Z(\alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h0bbb) + ) _1156_ ( + .A(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] ), + .C(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ), + .D(\sum[21] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1157_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _1158_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0_PFUMX_Z_BLUT), + .C0(\alu_op_i[2] ), + .Z(\alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h5ccf) + ) _1159_ ( + .A(\alu_op_i[1] ), + .B(\alu_op_i[0] ), + .C(\alu_in_1[21] ), + .D(\alu_in_2[21] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'hffff) + ) _1160_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" *) + L6MUX21 _1161_ ( + .D0(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1), + .SD(\alu_op_i[0] ), + .Z(\alu_output_LUT4_Z_A_LUT4_Z_1_C[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _1162_ ( + .D0(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D0), + .D1(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D1), + .SD(\alu_in_2[3] ), + .Z(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _1163_ ( + .ALUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[2] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _1164_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[31] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1165_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'hfeff) + ) _1166_ ( + .A(\alu_op_i[1] ), + .B(\alu_op_i[2] ), + .C(\alu_in_2[6] ), + .D(\alu_op_i[0] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _1167_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[31] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h0100) + ) _1168_ ( + .A(\alu_op_i[1] ), + .B(\alu_op_i[2] ), + .C(\alu_in_2[6] ), + .D(\alu_op_i[0] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'h0100) + ) _1169_ ( + .A(\alu_op_i[1] ), + .B(\alu_op_i[2] ), + .C(\alu_in_2[6] ), + .D(\alu_op_i[0] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" *) + L6MUX21 _1170_ ( + .D0(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" *) + PFUMX _1171_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1172_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1173_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1174_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" *) + PFUMX _1175_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1176_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1177_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" *) + L6MUX21 _1178_ ( + .D0(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" *) + PFUMX _1179_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1180_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" *) + LUT4 #( + .INIT(16'h0003) + ) _1181_ ( + .A(_0000_), + .B(\alu_in_1[9] ), + .C(\alu_op_i[2] ), + .D(\alu_in_2[6] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" *) + PFUMX _1182_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1183_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" *) + LUT4 #( + .INIT(16'h0003) + ) _1184_ ( + .A(_0000_), + .B(\alu_in_1[8] ), + .C(\alu_op_i[2] ), + .D(\alu_in_2[6] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'hf040) + ) _1185_ ( + .A(\alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[0] ), + .B(\alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[1] ), + .C(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] ), + .D(\alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[3] ), + .Z(alu_output_L6MUX21_Z_1_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1186_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h007f) + ) _1187_ ( + .A(\alu_in_1[29] ), + .B(\alu_in_2[29] ), + .C(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_D[3] ), + .Z(\alu_output_LUT4_Z_A_LUT4_Z_A[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hcee0) + ) _1188_ ( + .A(\alu_output_LUT4_Z_7_A_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_7_A_LUT4_Z_A[1] ), + .C(\alu_in_1[29] ), + .D(\alu_in_2[29] ), + .Z(\alu_output_LUT4_Z_A_LUT4_Z_A[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'h0003) + ) _1189_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[3] ), + .C(\alu_in_2[2] ), + .D(\alu_in_2[3] ), + .Z(\alu_output_LUT4_Z_A_LUT4_Z_A[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _1190_ ( + .D0(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _1191_ ( + .D0(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D0), + .D1(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D1), + .SD(\alu_in_2[0] ), + .Z(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _1192_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _1193_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[23] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _1194_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[21] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _1195_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _1196_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[24] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _1197_ ( + .ALUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[2] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _1198_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[22] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _1199_ ( + .D0(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D0), + .D1(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D1), + .SD(\alu_in_2[0] ), + .Z(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _1200_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _1201_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[19] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _1202_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[17] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _1203_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _1204_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[20] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _1205_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[18] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _1206_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _1207_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[27] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h0fcf) + ) _1208_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[0] ), + .C(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .D(\alu_in_2[5] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _1209_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[25] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _1210_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _1211_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[28] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _1212_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_in_1[26] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _1213_ ( + .ALUT(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_PFUMX_Z_BLUT), + .C0(\alu_in_2[0] ), + .Z(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'hff0f) + ) _1214_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_in_1[30] ), + .D(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h0f33) + ) _1215_ ( + .A(_0000_), + .B(\alu_in_1[29] ), + .C(\alu_in_1[31] ), + .D(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hc000) + ) _1216_ ( + .A(_0000_), + .B(\alu_op_i[0] ), + .C(\alu_op_i[1] ), + .D(\alu_op_i[2] ), + .Z(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0100) + ) _1217_ ( + .A(\alu_op_i[0] ), + .B(\alu_op_i[1] ), + .C(\alu_op_i[2] ), + .D(\sum[29] ), + .Z(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_D[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _1218_ ( + .ALUT(alu_output_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_BLUT), + .C0(\alu_output_PFUMX_Z_C0[4] ), + .Z(\alu_output[31] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'h0fcf) + ) _1219_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_A_L6MUX21_Z_SD[2] ), + .C(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .D(\alu_in_2[5] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _1220_ ( + .ALUT(alu_output_PFUMX_Z_1_ALUT), + .BLUT(alu_output_PFUMX_Z_1_BLUT), + .C0(\alu_output_PFUMX_Z_1_C0[4] ), + .Z(\alu_output[30] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _1221_ ( + .ALUT(alu_output_PFUMX_Z_10_ALUT), + .BLUT(alu_output_PFUMX_Z_10_BLUT), + .C0(\alu_output_PFUMX_Z_10_C0[4] ), + .Z(\alu_output[10] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'hffe0) + ) _1222_ ( + .A(\alu_output_PFUMX_Z_10_C0[0] ), + .B(\alu_output_PFUMX_Z_10_C0[1] ), + .C(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] ), + .D(\alu_output_PFUMX_Z_10_C0[3] ), + .Z(alu_output_PFUMX_Z_10_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'hffff) + ) _1223_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_10_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0007) + ) _1224_ ( + .A(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ), + .B(\sum[10] ), + .C(\alu_output_PFUMX_Z_10_C0_LUT4_Z_C[2] ), + .D(\alu_output_PFUMX_Z_10_C0_LUT4_Z_C[3] ), + .Z(\alu_output_PFUMX_Z_10_C0[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h5300) + ) _1225_ ( + .A(\alu_output_PFUMX_Z_10_C0_LUT4_Z_1_A[0] ), + .B(\alu_output_PFUMX_Z_10_C0_LUT4_Z_1_A[1] ), + .C(\alu_in_2[3] ), + .D(\alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] ), + .Z(\alu_output_PFUMX_Z_10_C0[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hf0cc) + ) _1226_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z[1] ), + .C(\alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B[1] ), + .D(\alu_in_2[2] ), + .Z(\alu_output_PFUMX_Z_10_C0_LUT4_Z_1_A[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hf0cc) + ) _1227_ ( + .A(_0000_), + .B(\alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[0] ), + .C(\alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[1] ), + .D(\alu_in_2[2] ), + .Z(\alu_output_PFUMX_Z_10_C0_LUT4_Z_1_A[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'ha300) + ) _1228_ ( + .A(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[0] ), + .B(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[1] ), + .C(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] ), + .Z(\alu_output_PFUMX_Z_10_C0[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hc000) + ) _1229_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ), + .C(\alu_in_1[10] ), + .D(\alu_in_2[10] ), + .Z(\alu_output_PFUMX_Z_10_C0_LUT4_Z_C[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" *) + L6MUX21 _1230_ ( + .D0(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1), + .SD(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hcee0) + ) _1231_ ( + .A(\alu_output_LUT4_Z_7_A_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_7_A_LUT4_Z_A[1] ), + .C(\alu_in_1[10] ), + .D(\alu_in_2[10] ), + .Z(\alu_output_PFUMX_Z_10_C0_LUT4_Z_C[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _1232_ ( + .ALUT(alu_output_PFUMX_Z_10_C0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_10_C0_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] ), + .Z(\alu_output_PFUMX_Z_10_C0[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h0c05) + ) _1233_ ( + .A(\alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[2] ), + .B(\alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[3] ), + .C(\alu_in_2[3] ), + .D(\alu_in_2[2] ), + .Z(alu_output_PFUMX_Z_10_C0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1234_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_10_C0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _1235_ ( + .ALUT(alu_output_PFUMX_Z_11_ALUT), + .BLUT(alu_output_PFUMX_Z_11_BLUT), + .C0(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[4] ), + .Z(\alu_output[9] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'hfff8) + ) _1236_ ( + .A(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ), + .B(\sum[9] ), + .C(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[2] ), + .D(\alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[3] ), + .Z(alu_output_PFUMX_Z_11_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'hffff) + ) _1237_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_11_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _1238_ ( + .ALUT(alu_output_PFUMX_Z_12_ALUT), + .BLUT(alu_output_PFUMX_Z_12_BLUT), + .C0(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] ), + .Z(\alu_output[6] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'hf4ff) + ) _1239_ ( + .A(\alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D[0] ), + .B(\alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] ), + .C(\alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D[2] ), + .D(\alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D[3] ), + .Z(alu_output_PFUMX_Z_12_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _1240_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D[3] ), + .Z(alu_output_PFUMX_Z_12_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" *) + PFUMX _1241_ ( + .ALUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hc500) + ) _1242_ ( + .A(\alu_output_PFUMX_Z_9_C0_LUT4_Z_A[0] ), + .B(\alu_output_PFUMX_Z_9_C0_LUT4_Z_A[1] ), + .C(\alu_in_2[3] ), + .D(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] ), + .Z(\alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _1243_ ( + .ALUT(alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D_PFUMX_Z_BLUT), + .C0(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[4] ), + .Z(\alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _1244_ ( + .ALUT(alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D_PFUMX_Z_1_ALUT), + .BLUT(alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D_PFUMX_Z_1_BLUT), + .C0(\alu_in_2[3] ), + .Z(\alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'hff00) + ) _1245_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z[2] ), + .Z(alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D_PFUMX_Z_1_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'hf0cc) + ) _1246_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B[2] ), + .C(\alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z[1] ), + .D(\alu_in_2[2] ), + .Z(alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D_PFUMX_Z_1_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1247_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h0007) + ) _1248_ ( + .A(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] ), + .B(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[1] ), + .C(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[2] ), + .D(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[3] ), + .Z(alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _1249_ ( + .ALUT(alu_output_PFUMX_Z_13_ALUT), + .BLUT(alu_output_PFUMX_Z_13_BLUT), + .C0(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[4] ), + .Z(\alu_output[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'hff10) + ) _1250_ ( + .A(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[0] ), + .B(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[1] ), + .C(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] ), + .D(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[3] ), + .Z(alu_output_PFUMX_Z_13_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'hffff) + ) _1251_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_13_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" *) + LUT4 #( + .INIT(16'hffff) + ) _1252_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _1253_ ( + .ALUT(alu_output_PFUMX_Z_14_ALUT), + .BLUT(alu_output_PFUMX_Z_14_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[4] ), + .Z(\alu_output[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'hff40) + ) _1254_ ( + .A(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .B(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] ), + .C(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[2] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[3] ), + .Z(alu_output_PFUMX_Z_14_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'hffff) + ) _1255_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_14_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h00fe) + ) _1256_ ( + .A(\alu_output_PFUMX_Z_1_C0[0] ), + .B(\alu_output_PFUMX_Z_1_C0[1] ), + .C(\alu_output_PFUMX_Z_1_C0[2] ), + .D(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] ), + .Z(alu_output_PFUMX_Z_1_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'hffff) + ) _1257_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_1_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0700) + ) _1258_ ( + .A(\alu_output_PFUMX_Z_1_C0_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] ), + .C(\alu_output_PFUMX_Z_1_C0_LUT4_Z_C[2] ), + .D(\alu_output_PFUMX_Z_1_C0_LUT4_Z_C[3] ), + .Z(\alu_output_PFUMX_Z_1_C0[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0b00) + ) _1259_ ( + .A(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[1] ), + .B(\alu_in_2[2] ), + .C(\alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C[2] ), + .D(\alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] ), + .Z(\alu_output_PFUMX_Z_1_C0[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _1260_ ( + .ALUT(alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .Z(\alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h0503) + ) _1261_ ( + .A(\alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[3] ), + .B(\alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_B[1] ), + .C(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .D(\alu_in_2[1] ), + .Z(alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _1262_ ( + .A(_0000_), + .B(\alu_in_1[27] ), + .C(\alu_in_1[28] ), + .D(\alu_in_2[0] ), + .Z(\alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" *) + LUT4 #( + .INIT(16'hffff) + ) _1263_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _1264_ ( + .A(_0000_), + .B(\alu_in_1[25] ), + .C(\alu_in_1[26] ), + .D(\alu_in_2[0] ), + .Z(\alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _1265_ ( + .A(_0000_), + .B(\alu_in_1[23] ), + .C(\alu_in_1[24] ), + .D(\alu_in_2[0] ), + .Z(\alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _1266_ ( + .A(_0000_), + .B(\alu_in_1[21] ), + .C(\alu_in_1[22] ), + .D(\alu_in_2[0] ), + .Z(\alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _1267_ ( + .A(_0000_), + .B(\alu_in_1[29] ), + .C(\alu_in_1[30] ), + .D(\alu_in_2[0] ), + .Z(\alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_B[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1268_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hac00) + ) _1269_ ( + .A(\alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A[0] ), + .B(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[0] ), + .C(\alu_in_2[2] ), + .D(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] ), + .Z(\alu_output_PFUMX_Z_1_C0[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'h330f) + ) _1270_ ( + .A(_0000_), + .B(\alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A[0] ), + .C(\alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[0] ), + .D(\alu_in_2[2] ), + .Z(\alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'h003f) + ) _1271_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[1] ), + .C(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[1] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] ), + .Z(\alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _1272_ ( + .ALUT(alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z_PFUMX_Z_BLUT), + .C0(\alu_output_PFUMX_Z_9_C0_LUT4_Z_A[4] ), + .Z(\alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h3faf) + ) _1273_ ( + .A(\alu_output_PFUMX_Z_9_C0_LUT4_Z_A[0] ), + .B(\alu_output_PFUMX_Z_9_C0_LUT4_Z_A[1] ), + .C(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] ), + .D(\alu_in_2[3] ), + .Z(alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" *) + PFUMX _1274_ ( + .ALUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1275_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hacff) + ) _1276_ ( + .A(\alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[2] ), + .B(\alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[3] ), + .C(\alu_in_2[1] ), + .D(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .Z(\alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _1277_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[2] ), + .Z(alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A_LUT4_D_Z) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _1278_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[3] ), + .Z(alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A_LUT4_D_1_Z) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" *) + PFUMX _1279_ ( + .ALUT(alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A_LUT4_D_Z), + .BLUT(alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A_LUT4_D_1_Z), + .C0(\alu_in_2[1] ), + .Z(alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A_LUT4_D_Z_PFUMX_ALUT_Z) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" *) + L6MUX21 _1280_ ( + .D0(alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A_LUT4_D_Z_PFUMX_ALUT_Z), + .D1(alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z), + .SD(\alu_in_2[2] ), + .Z(alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _1281_ ( + .A(_0000_), + .B(\alu_in_1[17] ), + .C(\alu_in_1[18] ), + .D(\alu_in_2[0] ), + .Z(\alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _1282_ ( + .A(_0000_), + .B(\alu_in_1[15] ), + .C(\alu_in_1[16] ), + .D(\alu_in_2[0] ), + .Z(\alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'ha300) + ) _1283_ ( + .A(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[1] ), + .B(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B[0] ), + .C(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .D(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[5] ), + .Z(\alu_output_PFUMX_Z_1_C0[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'h0300) + ) _1284_ ( + .A(_0000_), + .B(\alu_in_2[2] ), + .C(\alu_in_2[3] ), + .D(\alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[3] ), + .Z(\alu_output_PFUMX_Z_1_C0_LUT4_Z_A[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" *) + LUT4 #( + .INIT(16'hffff) + ) _1285_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h007f) + ) _1286_ ( + .A(\alu_in_1[30] ), + .B(\alu_in_2[30] ), + .C(\alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ), + .D(\alu_output_PFUMX_Z_1_C0_LUT4_Z_C_LUT4_Z_D[3] ), + .Z(\alu_output_PFUMX_Z_1_C0_LUT4_Z_C[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hcee0) + ) _1287_ ( + .A(\alu_output_LUT4_Z_7_A_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_7_A_LUT4_Z_A[1] ), + .C(\alu_in_1[30] ), + .D(\alu_in_2[30] ), + .Z(\alu_output_PFUMX_Z_1_C0_LUT4_Z_C[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h0100) + ) _1288_ ( + .A(\alu_op_i[0] ), + .B(\alu_op_i[1] ), + .C(\alu_op_i[2] ), + .D(\sum[30] ), + .Z(\alu_output_PFUMX_Z_1_C0_LUT4_Z_C_LUT4_Z_D[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _1289_ ( + .ALUT(alu_output_PFUMX_Z_2_ALUT), + .BLUT(alu_output_PFUMX_Z_2_BLUT), + .C0(\alu_output_PFUMX_Z_2_C0[4] ), + .Z(\alu_output[27] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h00fe) + ) _1290_ ( + .A(\alu_output_PFUMX_Z_2_C0[0] ), + .B(\alu_output_PFUMX_Z_2_C0[1] ), + .C(\alu_output_PFUMX_Z_2_C0[2] ), + .D(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] ), + .Z(alu_output_PFUMX_Z_2_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'hffff) + ) _1291_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_2_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'h3f00) + ) _1292_ ( + .A(_0000_), + .B(\alu_output_PFUMX_Z_2_C0_LUT4_Z_B[0] ), + .C(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] ), + .D(\alu_output_PFUMX_Z_2_C0_LUT4_Z_B[2] ), + .Z(\alu_output_PFUMX_Z_2_C0[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'h5300) + ) _1293_ ( + .A(\alu_output_PFUMX_Z_C0_LUT4_Z_1_A[1] ), + .B(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B[1] ), + .C(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .D(\alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] ), + .Z(\alu_output_PFUMX_Z_2_C0[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hf044) + ) _1294_ ( + .A(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A[0] ), + .B(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .C(\alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[3] ), + .D(\alu_in_2[1] ), + .Z(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" *) + LUT4 #( + .INIT(16'hacff) + ) _1295_ ( + .A(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A[0] ), + .B(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_B[2] ), + .C(\alu_in_2[1] ), + .D(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .Z(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" *) + L6MUX21 _1296_ ( + .D0(alu_output_L6MUX21_Z_2_D0), + .D1(alu_output_L6MUX21_Z_2_D1), + .SD(\alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] ), + .Z(\alu_output[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" *) + LUT4 #( + .INIT(16'hffff) + ) _1297_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'hccf0) + ) _1298_ ( + .A(_0000_), + .B(\alu_in_1[28] ), + .C(\alu_in_1[29] ), + .D(\alu_in_2[0] ), + .Z(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_B[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" *) + L6MUX21 _1299_ ( + .D0(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1), + .SD(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .Z(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" *) + PFUMX _1300_ ( + .ALUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" *) + LUT4 #( + .INIT(16'hff00) + ) _1301_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" *) + L6MUX21 _1302_ ( + .D0(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1), + .SD(\alu_op_i[0] ), + .Z(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" *) + L6MUX21 _1303_ ( + .D0(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" *) + PFUMX _1304_ ( + .ALUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1305_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1306_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" *) + PFUMX _1307_ ( + .ALUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" *) + L6MUX21 _1308_ ( + .D0(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0), + .D1(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1), + .SD(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1309_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1310_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" *) + L6MUX21 _1311_ ( + .D0(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" *) + PFUMX _1312_ ( + .ALUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1313_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" *) + LUT4 #( + .INIT(16'h0003) + ) _1314_ ( + .A(_0000_), + .B(\alu_in_1[19] ), + .C(\alu_op_i[2] ), + .D(\alu_in_2[6] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" *) + PFUMX _1315_ ( + .ALUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1316_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" *) + LUT4 #( + .INIT(16'h0003) + ) _1317_ ( + .A(_0000_), + .B(\alu_in_1[18] ), + .C(\alu_op_i[2] ), + .D(\alu_in_2[6] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'hff00) + ) _1318_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" *) + PFUMX _1319_ ( + .ALUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" *) + LUT4 #( + .INIT(16'hff00) + ) _1320_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" *) + L6MUX21 _1321_ ( + .D0(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1), + .SD(\alu_op_i[0] ), + .Z(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" *) + L6MUX21 _1322_ ( + .D0(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" *) + PFUMX _1323_ ( + .ALUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1324_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1325_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" *) + PFUMX _1326_ ( + .ALUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1327_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1328_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" *) + L6MUX21 _1329_ ( + .D0(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" *) + LUT4 #( + .INIT(16'hff00) + ) _1330_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[2] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" *) + PFUMX _1331_ ( + .ALUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1332_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" *) + LUT4 #( + .INIT(16'h0003) + ) _1333_ ( + .A(_0000_), + .B(\alu_in_1[21] ), + .C(\alu_op_i[2] ), + .D(\alu_in_2[6] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" *) + PFUMX _1334_ ( + .ALUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1335_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" *) + LUT4 #( + .INIT(16'h0003) + ) _1336_ ( + .A(_0000_), + .B(\alu_in_1[20] ), + .C(\alu_op_i[2] ), + .D(\alu_in_2[6] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" *) + LUT4 #( + .INIT(16'hff00) + ) _1337_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" *) + PFUMX _1338_ ( + .ALUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_ALUT), + .BLUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1339_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" *) + L6MUX21 _1340_ ( + .D0(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z), + .D1(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_D1), + .SD(\alu_in_2[1] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" *) + LUT4 #( + .INIT(16'hff00) + ) _1341_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[3] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" *) + PFUMX _1342_ ( + .ALUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_D1_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1343_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" *) + LUT4 #( + .INIT(16'hff00) + ) _1344_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" *) + L6MUX21 _1345_ ( + .D0(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0), + .D1(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z), + .SD(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .Z(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[0] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" *) + L6MUX21 _1346_ ( + .D0(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1), + .SD(\alu_in_2[1] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" *) + PFUMX _1347_ ( + .ALUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1348_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" *) + LUT4 #( + .INIT(16'hff00) + ) _1349_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[3] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" *) + PFUMX _1350_ ( + .ALUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1351_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" *) + PFUMX _1352_ ( + .ALUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" *) + LUT4 #( + .INIT(16'hff00) + ) _1353_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[2] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" *) + L6MUX21 _1354_ ( + .D0(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1), + .SD(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .Z(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[1] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" *) + L6MUX21 _1355_ ( + .D0(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0), + .D1(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1), + .SD(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .Z(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" *) + L6MUX21 _1356_ ( + .D0(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D1), + .SD(\alu_in_2[1] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" *) + PFUMX _1357_ ( + .ALUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1358_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _1359_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_C[3] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" *) + PFUMX _1360_ ( + .ALUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1361_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _1362_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" *) + LUT4 #( + .INIT(16'hff00) + ) _1363_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[0] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" *) + L6MUX21 _1364_ ( + .D0(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1), + .SD(\alu_in_2[1] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" *) + PFUMX _1365_ ( + .ALUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1366_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _1367_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[3] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" *) + PFUMX _1368_ ( + .ALUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1369_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" *) + LUT4 #( + .INIT(16'h00ff) + ) _1370_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" *) + L6MUX21 _1371_ ( + .D0(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1), + .SD(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" *) + PFUMX _1372_ ( + .ALUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1373_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" *) + LUT4 #( + .INIT(16'hff00) + ) _1374_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[1] ), + .Z(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1375_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" *) + PFUMX _1376_ ( + .ALUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1377_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1378_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" *) + L6MUX21 _1379_ ( + .D0(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1), + .SD(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" *) + PFUMX _1380_ ( + .ALUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" *) + LUT4 #( + .INIT(16'hff00) + ) _1381_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" *) + LUT4 #( + .INIT(16'hff00) + ) _1382_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" *) + PFUMX _1383_ ( + .ALUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" *) + LUT4 #( + .INIT(16'hff00) + ) _1384_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" *) + LUT4 #( + .INIT(16'h3f00) + ) _1385_ ( + .A(_0000_), + .B(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .C(\alu_in_2[5] ), + .D(\alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] ), + .Z(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[5] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" *) + LUT4 #( + .INIT(16'hff00) + ) _1386_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" *) + LUT4 #( + .INIT(16'hf000) + ) _1387_ ( + .A(_0000_), + .B(_0000_), + .C(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .D(\alu_in_2[5] ), + .Z(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[4] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _1388_ ( + .ALUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] ), + .Z(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" *) + LUT4 #( + .INIT(16'h0d00) + ) _1389_ ( + .A(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ), + .B(\alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[2] ), + .C(\alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ), + .D(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1390_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" *) + PFUMX _1391_ ( + .ALUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_in_2[1] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" *) + LUT4 #( + .INIT(16'hff00) + ) _1392_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" *) + LUT4 #( + .INIT(16'hff00) + ) _1393_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" *) + L6MUX21 _1394_ ( + .D0(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1), + .SD(\alu_op_i[0] ), + .Z(\alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" *) + L6MUX21 _1395_ ( + .D0(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" *) + PFUMX _1396_ ( + .ALUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_PFUMX_Z_ALUT), + .BLUT(alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_PFUMX_Z_BLUT), + .C0(\alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ), + .Z(\alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[2] ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" *) + PFUMX _1397_ ( + .ALUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1398_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1399_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" *) + PFUMX _1400_ ( + .ALUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1401_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1402_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" *) + L6MUX21 _1403_ ( + .D0(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0), + .D1(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1), + .SD(\alu_in_2[0] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" *) + PFUMX _1404_ ( + .ALUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT), + .BLUT(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT), + .C0(\alu_op_i[1] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" *) + LUT4 #( + .INIT(16'h0000) + ) _1405_ ( + .A(_0000_), + .B(_0000_), + .C(_0000_), + .D(_0000_), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" *) + LUT4 #( + .INIT(16'h0003) + ) _1406_ ( + .A(_0000_), + .B(\alu_in_1[17] ), + .C(\alu_op_i[2] ), + .D(\alu_in_2[6] ), + .Z(alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT) + ); + assign _0000_ = 1'h0; + assign _0001_ = 1'h1; + assign _0002_ = 1'hx; + assign \sum_CCU2C_S0_3_COUT[30] = \sum_CCU2C_S0_COUT[31] ; + assign \sum_CCU2C_S0_3_COUT[29] = \sum_CCU2C_S0_COUT[30] ; + assign \sum_CCU2C_S0_3_COUT[28] = \sum_CCU2C_S0_COUT[29] ; + assign \sum_CCU2C_S0_3_COUT[27] = \sum_CCU2C_S0_COUT[28] ; + assign \sum_CCU2C_S0_3_COUT[26] = \sum_CCU2C_S0_COUT[27] ; + assign \sum_CCU2C_S0_3_COUT[25] = \sum_CCU2C_S0_COUT[26] ; + assign \sum_CCU2C_S0_3_COUT[24] = \sum_CCU2C_S0_COUT[25] ; + assign \sum_CCU2C_S0_3_COUT[23] = \sum_CCU2C_S0_COUT[24] ; + assign \sum_CCU2C_S0_3_COUT[22] = \sum_CCU2C_S0_COUT[23] ; + assign \sum_CCU2C_S0_3_COUT[21] = \sum_CCU2C_S0_COUT[22] ; + assign \sum_CCU2C_S0_3_COUT[20] = \sum_CCU2C_S0_COUT[21] ; + assign \sum_CCU2C_S0_3_COUT[19] = \sum_CCU2C_S0_COUT[20] ; + assign \sum_CCU2C_S0_3_COUT[18] = \sum_CCU2C_S0_COUT[19] ; + assign \sum_CCU2C_S0_3_COUT[17] = \sum_CCU2C_S0_COUT[18] ; + assign \sum_CCU2C_S0_3_COUT[16] = \sum_CCU2C_S0_COUT[17] ; + assign \sum_CCU2C_S0_3_COUT[15] = \sum_CCU2C_S0_COUT[16] ; + assign \sum_CCU2C_S0_3_COUT[14] = \sum_CCU2C_S0_COUT[15] ; + assign \sum_CCU2C_S0_3_COUT[13] = \sum_CCU2C_S0_COUT[14] ; + assign \sum_CCU2C_S0_3_COUT[12] = \sum_CCU2C_S0_COUT[13] ; + assign \sum_CCU2C_S0_3_COUT[11] = \sum_CCU2C_S0_COUT[12] ; + assign \sum_CCU2C_S0_3_COUT[10] = \sum_CCU2C_S0_COUT[11] ; + assign \sum_CCU2C_S0_3_COUT[9] = \sum_CCU2C_S0_COUT[10] ; + assign \sum_CCU2C_S0_3_COUT[8] = \sum_CCU2C_S0_COUT[9] ; + assign \sum_CCU2C_S0_3_COUT[7] = \sum_CCU2C_S0_COUT[8] ; + assign \sum_CCU2C_S0_3_COUT[6] = \sum_CCU2C_S0_COUT[7] ; + assign \sum_CCU2C_S0_3_COUT[5] = \sum_CCU2C_S0_COUT[6] ; + assign \sum_CCU2C_S0_3_COUT[4] = \sum_CCU2C_S0_COUT[5] ; + assign \sum_CCU2C_S0_3_COUT[3] = \sum_CCU2C_S0_COUT[4] ; + assign \sum_CCU2C_S0_3_COUT[2] = \sum_CCU2C_S0_COUT[3] ; + assign \sum_CCU2C_S0_3_COUT[1] = \sum_CCU2C_S0_COUT[2] ; + assign \sum_CCU2C_S0_3_COUT[0] = \sum_CCU2C_S0_COUT[1] ; + assign \sum_CCU2C_S0_COUT[0] = _0000_; + assign \complement2_CCU2C_S0_3_COUT[30] = \complement2_CCU2C_S0_COUT[31] ; + assign \complement2_CCU2C_S0_3_COUT[29] = \complement2_CCU2C_S0_COUT[30] ; + assign \complement2_CCU2C_S0_3_COUT[28] = \complement2_CCU2C_S0_COUT[29] ; + assign \complement2_CCU2C_S0_3_COUT[27] = \complement2_CCU2C_S0_COUT[28] ; + assign \complement2_CCU2C_S0_3_COUT[26] = \complement2_CCU2C_S0_COUT[27] ; + assign \complement2_CCU2C_S0_3_COUT[25] = \complement2_CCU2C_S0_COUT[26] ; + assign \complement2_CCU2C_S0_3_COUT[24] = \complement2_CCU2C_S0_COUT[25] ; + assign \complement2_CCU2C_S0_3_COUT[23] = \complement2_CCU2C_S0_COUT[24] ; + assign \complement2_CCU2C_S0_3_COUT[22] = \complement2_CCU2C_S0_COUT[23] ; + assign \complement2_CCU2C_S0_3_COUT[21] = \complement2_CCU2C_S0_COUT[22] ; + assign \complement2_CCU2C_S0_3_COUT[20] = \complement2_CCU2C_S0_COUT[21] ; + assign \complement2_CCU2C_S0_3_COUT[19] = \complement2_CCU2C_S0_COUT[20] ; + assign \complement2_CCU2C_S0_3_COUT[18] = \complement2_CCU2C_S0_COUT[19] ; + assign \complement2_CCU2C_S0_3_COUT[17] = \complement2_CCU2C_S0_COUT[18] ; + assign \complement2_CCU2C_S0_3_COUT[16] = \complement2_CCU2C_S0_COUT[17] ; + assign \complement2_CCU2C_S0_3_COUT[15] = \complement2_CCU2C_S0_COUT[16] ; + assign \complement2_CCU2C_S0_3_COUT[14] = \complement2_CCU2C_S0_COUT[15] ; + assign \complement2_CCU2C_S0_3_COUT[13] = \complement2_CCU2C_S0_COUT[14] ; + assign \complement2_CCU2C_S0_3_COUT[12] = \complement2_CCU2C_S0_COUT[13] ; + assign \complement2_CCU2C_S0_3_COUT[11] = \complement2_CCU2C_S0_COUT[12] ; + assign \complement2_CCU2C_S0_3_COUT[10] = \complement2_CCU2C_S0_COUT[11] ; + assign \complement2_CCU2C_S0_3_COUT[9] = \complement2_CCU2C_S0_COUT[10] ; + assign \complement2_CCU2C_S0_3_COUT[8] = \complement2_CCU2C_S0_COUT[9] ; + assign \complement2_CCU2C_S0_3_COUT[7] = \complement2_CCU2C_S0_COUT[8] ; + assign \complement2_CCU2C_S0_3_COUT[6] = \complement2_CCU2C_S0_COUT[7] ; + assign \complement2_CCU2C_S0_3_COUT[5] = \complement2_CCU2C_S0_COUT[6] ; + assign \complement2_CCU2C_S0_3_COUT[4] = \complement2_CCU2C_S0_COUT[5] ; + assign \complement2_CCU2C_S0_3_COUT[3] = \complement2_CCU2C_S0_COUT[4] ; + assign \complement2_CCU2C_S0_3_COUT[2] = \complement2_CCU2C_S0_COUT[3] ; + assign \complement2_CCU2C_S0_3_COUT[1] = \complement2_CCU2C_S0_COUT[2] ; + assign \complement2_CCU2C_S0_3_COUT[0] = \complement2_CCU2C_S0_B0[0] ; + assign \complement2_CCU2C_S0_COUT[1] = \complement2_CCU2C_S0_B0[0] ; + assign \complement2_CCU2C_S0_COUT[0] = _0000_; + assign \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[2] = \alu_in_2[2] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[0] = _0001_; + assign \alu_output_PFUMX_Z_9_C0_LUT4_Z_A[3] = \alu_in_2[3] ; + assign \alu_output_PFUMX_Z_9_C0_LUT4_Z_A[2] = \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] ; + assign \alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A[2] = \alu_in_2[2] ; + assign \alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A[1] = \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[0] ; + assign \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[6] = \alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ; + assign \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[5] = \alu_in_2[2] ; + assign \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[4] = \alu_in_2[1] ; + assign \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[3] = \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[1] ; + assign \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[1] = \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[2] ; + assign \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[0] = \alu_in_2[31] ; + assign \alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z[0] = \alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ; + assign \alu_output_LUT4_Z_8_A_LUT4_Z_C[1] = \sum[12] ; + assign \alu_output_LUT4_Z_8_A_LUT4_Z_C[0] = \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ; + assign \alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[5] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ; + assign \alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[4] = \alu_in_2[1] ; + assign \alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[2] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] ; + assign \alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] ; + assign \alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[0] = \alu_output_LUT4_Z_A_LUT4_Z_1_C[3] ; + assign \alu_output_PFUMX_Z_C0_LUT4_Z_B[2] = \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] ; + assign \alu_output_PFUMX_Z_C0_LUT4_Z_B[1] = \alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ; + assign \alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B[2] = \alu_in_2[2] ; + assign \alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B[1] = \alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[0] ; + assign \alu_output_PFUMX_Z_1_C0[3] = \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] ; + assign \alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[3] = \alu_in_2[3] ; + assign \alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[2] = \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] ; + assign \alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[0] = \alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] ; + assign \alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C[3] = \alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] ; + assign \alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C[1] = \alu_in_2[2] ; + assign \alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C[0] = \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[1] ; + assign \alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_B[4] = \alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ; + assign \alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_B[3] = \alu_in_2[1] ; + assign \alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_B[2] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ; + assign \alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_B[0] = \alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[3] ; + assign \alu_output_PFUMX_Z_1_C0_LUT4_Z_C[1] = \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] ; + assign \alu_output_PFUMX_Z_1_C0_LUT4_Z_C[0] = \alu_output_PFUMX_Z_1_C0_LUT4_Z_A[0] ; + assign \alu_output_PFUMX_Z_1_C0_LUT4_Z_C_LUT4_Z_D[2] = \alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ; + assign \alu_output_PFUMX_Z_1_C0_LUT4_Z_C_LUT4_Z_D[1] = \alu_in_2[30] ; + assign \alu_output_PFUMX_Z_1_C0_LUT4_Z_C_LUT4_Z_D[0] = \alu_in_1[30] ; + assign \alu_output_PFUMX_Z_C0[3] = \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] ; + assign \alu_output_PFUMX_Z_C0_LUT4_Z_2_B[2] = \alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] ; + assign \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_B[6] = \alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ; + assign \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_B[5] = \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] ; + assign \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_B[4] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ; + assign \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_B[3] = \alu_in_2[0] ; + assign \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_B[1] = \alu_in_1[31] ; + assign \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_B[0] = \alu_in_1[30] ; + assign \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A[4] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ; + assign \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A[3] = \alu_in_2[1] ; + assign \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A[2] = \alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[3] ; + assign \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A[1] = \alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[6] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[5] = \alu_in_2[1] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[2] = \alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[1] = \alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[0] = \alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[2] ; + assign \alu_output_PFUMX_Z_C0_LUT4_Z_A[2] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] ; + assign \alu_output_PFUMX_Z_C0_LUT4_Z_A[0] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[1] ; + assign \alu_output_PFUMX_Z_C0_LUT4_Z_1_A[2] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ; + assign \alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z[0] = \alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ; + assign \alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_C[1] = \sum[7] ; + assign \alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_C[0] = \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ; + assign \alu_output_PFUMX_Z_2_C0_LUT4_Z_B[1] = \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] ; + assign \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B[3] = \alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] ; + assign \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B[2] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ; + assign \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B[0] = \alu_output_PFUMX_Z_C0_LUT4_Z_1_A[1] ; + assign \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[5] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ; + assign \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[4] = \alu_in_2[1] ; + assign \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[2] = \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] ; + assign \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[1] = \alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] ; + assign \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[0] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[5] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[4] = \alu_in_2[1] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[2] = \alu_output_LUT4_Z_A_LUT4_Z_1_C[3] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[1] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[0] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[3] ; + assign \complement2_LUT4_C_D[1] = \complement2[16] ; + assign \complement2_LUT4_C_D[0] = \alu_in_2[16] ; + assign \alu_output_LUT4_Z_9_B_LUT4_Z_1_C[3] = \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[5] ; + assign \alu_output_LUT4_Z_9_B_LUT4_Z_1_C[1] = \alu_output_LUT4_Z_9_B_LUT4_Z_1_B[0] ; + assign \alu_output_LUT4_Z_9_B_LUT4_Z_1_C[0] = \alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ; + assign \alu_output_PFUMX_Z_2_C0[3] = \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] ; + assign \alu_output_PFUMX_Z_C0_PFUMX_Z_C0[2] = \alu_in_2[3] ; + assign \alu_output_PFUMX_Z_C0_PFUMX_Z_C0[1] = \alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[1] ; + assign \alu_output_PFUMX_Z_C0_PFUMX_Z_C0[0] = \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] ; + assign \alu_output_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z_D[2] = \alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ; + assign \alu_output_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z_D[1] = \alu_in_2[31] ; + assign \alu_output_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z_D[0] = \alu_in_1[31] ; + assign \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[3] = \alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ; + assign \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[2] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] ; + assign \alu_output_LUT4_Z_3_C_LUT4_Z_A[4] = \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] ; + assign \alu_output_LUT4_Z_3_C_LUT4_Z_A[1] = \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] ; + assign \alu_output_PFUMX_Z_10_C0_LUT4_Z_C[1] = \sum[10] ; + assign \alu_output_PFUMX_Z_10_C0_LUT4_Z_C[0] = \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ; + assign \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[2] = \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] ; + assign \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[1] = \alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] ; + assign \alu_output_LUT4_Z_5_B_LUT4_Z_C_LUT4_Z_1_B[2] = \alu_output_LUT4_Z_7_A_LUT4_Z_A[1] ; + assign \alu_output_LUT4_Z_5_B_LUT4_Z_C_LUT4_Z_1_B[1] = \alu_in_2[18] ; + assign \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[1] = \sum[4] ; + assign \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[0] = \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ; + assign \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z[3] = \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] ; + assign \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[4] = \alu_in_2[3] ; + assign \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[3] = \alu_in_2[2] ; + assign \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z_D[4] = \alu_in_2[1] ; + assign \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z_D[3] = \alu_in_2[0] ; + assign \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z_D[1] = \alu_in_1[4] ; + assign \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z_D[0] = \alu_in_1[3] ; + assign \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[6] = \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] ; + assign \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[1] = \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] ; + assign \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A[4] = \alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ; + assign \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A[3] = \alu_in_2[2] ; + assign \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A[2] = \alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ; + assign \alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[5] = \alu_in_2[2] ; + assign \alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[4] = \alu_in_2[3] ; + assign \alu_output_LUT4_Z_11_C[1] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[0] ; + assign \alu_output_LUT4_Z_11_C[0] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] ; + assign \alu_output_LUT4_Z_5_B_LUT4_Z_C[1] = \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] ; + assign \alu_output_LUT4_Z_5_B_LUT4_Z_C[0] = \alu_output_LUT4_Z_5_B_LUT4_Z_A[2] ; + assign \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A[4] = \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] ; + assign \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A[1] = \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] ; + assign \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A[3] = \alu_in_2[3] ; + assign \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A[1] = \alu_in_2[2] ; + assign \alu_output_LUT4_Z_5_B[1] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[4] ; + assign \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B[4] = \alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] ; + assign \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B[3] = \alu_in_2[2] ; + assign \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B[2] = \alu_in_2[3] ; + assign \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B[0] = \alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[0] ; + assign \alu_output_LUT4_Z_8_A_LUT4_Z_1_C[3] = \alu_in_2[2] ; + assign \alu_output_LUT4_Z_8_A_LUT4_Z_1_C[2] = \alu_in_2[3] ; + assign \alu_output_LUT4_Z_11_C_LUT4_Z_C[1] = \sum[5] ; + assign \alu_output_LUT4_Z_11_C_LUT4_Z_C[0] = \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ; + assign \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A[3] = \alu_in_2[2] ; + assign \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A[2] = \alu_in_2[3] ; + assign \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A[1] = \alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A[0] ; + assign \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_BLUT_LUT4_Z_D[4] = \alu_in_2[1] ; + assign \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_BLUT_LUT4_Z_D[3] = \alu_in_2[0] ; + assign \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_BLUT_LUT4_Z_D[1] = \alu_in_1[6] ; + assign \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_BLUT_LUT4_Z_D[0] = \alu_in_1[5] ; + assign \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_LUT4_Z_1_D[2] = \alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ; + assign \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_LUT4_Z_1_D[1] = \alu_in_2[17] ; + assign \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_LUT4_Z_1_D[0] = \alu_in_1[17] ; + assign \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_C[1] = \sum[1] ; + assign \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_C[0] = \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ; + assign \alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D[4] = \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] ; + assign \alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D[1] = \alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] ; + assign \alu_output_LUT4_Z_8_A[1] = \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] ; + assign \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A[5] = \alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ; + assign \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A[4] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ; + assign \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A[2] = \alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ; + assign \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A[1] = \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[1] ; + assign \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A[0] = \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[4] = \sum[13] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[3] = \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[1] = \alu_in_1[13] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[0] = \alu_in_2[13] ; + assign \alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[4] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] ; + assign \alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] = \alu_in_2[1] ; + assign \alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[2] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ; + assign \alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z[4] = \alu_in_2[3] ; + assign \alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z[3] = \alu_in_2[2] ; + assign \alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z[0] = \alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B[2] ; + assign \alu_output_LUT4_Z_12_C[1] = \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[0] ; + assign \alu_output_LUT4_Z_12_C[0] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] ; + assign \alu_output_LUT4_Z_12_C_LUT4_Z_C[1] = \sum[2] ; + assign \alu_output_LUT4_Z_12_C_LUT4_Z_C[0] = \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ; + assign \alu_output_LUT4_Z_5_B_LUT4_Z_A[5] = \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] ; + assign \alu_output_LUT4_Z_5_B_LUT4_Z_A[4] = \alu_in_2[4] ; + assign \alu_output_LUT4_Z_5_B_LUT4_Z_A[3] = \alu_in_2[5] ; + assign \alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B[4] = \alu_in_2[2] ; + assign \alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B[3] = \alu_in_2[3] ; + assign \alu_output_LUT4_Z_7_A_LUT4_Z_A[3] = \alu_in_2[26] ; + assign \alu_output_LUT4_Z_7_A_LUT4_Z_A[2] = \alu_in_1[26] ; + assign \alu_output_PFUMX_Z_3_C0_LUT4_Z_C[1] = \sum[26] ; + assign \alu_output_PFUMX_Z_3_C0_LUT4_Z_C[0] = \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ; + assign \alu_output_LUT4_Z_9_B_LUT4_Z_C[1] = \sum[11] ; + assign \alu_output_LUT4_Z_9_B_LUT4_Z_C[0] = \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[5] = \alu_in_2[2] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[4] = \alu_in_2[3] ; + assign \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[1] = \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] ; + assign \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[0] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] ; + assign \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_C[1] = \sum[3] ; + assign \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_C[0] = \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B[1] = \alu_op_i[2] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B[4] = \alu_op_i[1] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B[3] = \alu_op_i[0] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B[2] = \sum[0] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B[1] = \sum[31] ; + assign \alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[6] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ; + assign \alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[5] = \alu_in_2[1] ; + assign \alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[4] = \alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ; + assign \alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[1] = \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] ; + assign \alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[0] = \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] ; + assign \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[5] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ; + assign \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[4] = \alu_in_2[1] ; + assign \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[2] = \alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] ; + assign \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] ; + assign \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] ; + assign \alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[5] = \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] ; + assign \alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[4] = \alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] ; + assign \alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] = \alu_in_2[3] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_1_C[6] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_1_C[5] = \alu_in_2[1] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_1_C[2] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_1_C[1] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[3] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_1_C[0] = \alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] ; + assign \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[6] = \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] ; + assign \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[5] = \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] ; + assign \alu_output_LUT4_Z_9_B_LUT4_Z_1_B[5] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[4] ; + assign \alu_output_LUT4_Z_9_B_LUT4_Z_1_B[4] = \alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ; + assign \alu_output_LUT4_Z_9_B_LUT4_Z_1_B[3] = \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[3] = \alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[2] = \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] ; + assign \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z_LUT4_Z_1_A[3] = \alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ; + assign \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z_LUT4_Z_1_A[2] = \alu_in_2[1] ; + assign \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z_LUT4_Z_1_A[1] = \alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[0] ; + assign \alu_output_LUT4_Z_10_B_LUT4_Z_C[1] = \sum[8] ; + assign \alu_output_LUT4_Z_10_B_LUT4_Z_C[0] = \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ; + assign \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[3] = \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[0] ; + assign \alu_output_LUT4_Z_1_B_LUT4_Z_1_A[5] = \alu_in_2[2] ; + assign \alu_output_LUT4_Z_1_B_LUT4_Z_1_A[4] = \alu_in_2[3] ; + assign \alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[6] = \alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ; + assign \alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[5] = \alu_in_2[2] ; + assign \alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[4] = \alu_in_2[1] ; + assign \alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[1] = \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] ; + assign \alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[0] = \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[2] ; + assign \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z_LUT4_Z_1_C[1] = \sum[16] ; + assign \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z_LUT4_Z_1_C[0] = \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ; + assign \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[5] = \alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] ; + assign \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[4] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ; + assign \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[3] = \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[2] ; + assign \alu_output_LUT4_Z_4_C_PFUMX_Z_C0[3] = \sum[19] ; + assign \alu_output_LUT4_Z_4_C_PFUMX_Z_C0[2] = \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ; + assign \alu_output_LUT4_Z_4_C_PFUMX_Z_C0[0] = \alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ; + assign \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[5] = \alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ; + assign \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[4] = \alu_in_2[2] ; + assign \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] = \alu_in_2[1] ; + assign \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[2] = \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[2] ; + assign \alu_output_LUT4_Z_3_C[1] = \sum[20] ; + assign \alu_output_LUT4_Z_3_C[0] = \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ; + assign \alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[2] = \alu_in_2[2] ; + assign \alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[1] = \alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B[0] ; + assign \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[3] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ; + assign \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[0] = \alu_op_i[2] ; + assign \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_B_Z[1] = \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] ; + assign \alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[4] = \alu_in_2[3] ; + assign \alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[3] = \alu_in_2[2] ; + assign \alu_output_PFUMX_Z_3_C0[2] = \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] ; + assign \alu_output_LUT4_Z_4_C[1] = \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] ; + assign \alu_output_LUT4_Z_4_C[0] = \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[0] ; + assign \alu_output_LUT4_Z_A_L6MUX21_Z_SD[3] = \alu_in_2[2] ; + assign \alu_output_LUT4_Z_A_L6MUX21_Z_SD[1] = \alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ; + assign \alu_output_PFUMX_Z_9_C0[2] = \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] ; + assign \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_LUT4_Z_1_C[1] = \sum[24] ; + assign \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_LUT4_Z_1_C[0] = \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ; + assign \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[6] = \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] ; + assign \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[0] = \alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] ; + assign \alu_output_LUT4_Z_1_B_LUT4_Z_C[1] = \sum[28] ; + assign \alu_output_LUT4_Z_1_B_LUT4_Z_C[0] = \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ; + assign \alu_output_LUT4_Z_8_A_LUT4_Z_1_A[2] = \alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] ; + assign \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[5] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ; + assign \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[4] = \alu_in_2[1] ; + assign \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[2] = \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] ; + assign \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] = \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] ; + assign \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[0] = \alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] ; + assign \alu_output_PFUMX_Z_10_C0[2] = \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] ; + assign \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[5] = \alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] ; + assign \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[4] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ; + assign \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[2] = \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[5] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[4] = \alu_in_2[1] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[2] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] = \alu_output_LUT4_Z_A_LUT4_Z_1_C[3] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[0] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] ; + assign \alu_output_PFUMX_Z_10_C0_LUT4_Z_1_A[3] = \alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] ; + assign \alu_output_PFUMX_Z_10_C0_LUT4_Z_1_A[2] = \alu_in_2[3] ; + assign \alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[4] = \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] ; + assign \alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[3] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_1_B[3] = \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[5] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_1_B[2] = \alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_1_B[0] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[0] ; + assign \alu_output_PFUMX_Z_1_C0_LUT4_Z_A[1] = \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] ; + assign \alu_output_LUT4_Z_10_B_LUT4_Z_2_A[3] = \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] ; + assign \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[1] = \sum[9] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_D[2] = \alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_D[1] = \alu_in_2[29] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_D[0] = \alu_in_1[29] ; + assign \alu_output_LUT4_Z_10_B_LUT4_Z_1_B[3] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] ; + assign \alu_output_LUT4_Z_10_B_LUT4_Z_1_B[0] = \alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_A[1] = \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] ; + assign \alu_output_PFUMX_Z_9_C0_PFUMX_Z_C0[3] = \sum[14] ; + assign \alu_output_PFUMX_Z_9_C0_PFUMX_Z_C0[2] = \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ; + assign \alu_output_PFUMX_Z_9_C0_PFUMX_Z_C0[0] = \alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] ; + assign \alu_output_LUT4_Z_A[2] = \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] ; + assign \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A[5] = \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] ; + assign \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A[4] = \alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] ; + assign \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A[3] = \alu_in_2[3] ; + assign \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A[1] = \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[2] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0[3] = \sum[21] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0[2] = \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0[1] = \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] ; + assign \alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0[0] = \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A[0] ; + assign \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B[2] = \alu_in_2[2] ; + assign \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B[1] = \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B[1] ; + assign \alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[2] = \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] ; + assign \alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A[3] = \alu_in_2[2] ; + assign \alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A[2] = \alu_in_2[3] ; + assign \alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A[1] = \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[0] ; + assign \alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_ALUT_LUT4_Z_D[4] = \alu_in_2[1] ; + assign \alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_ALUT_LUT4_Z_D[3] = \alu_in_2[0] ; + assign \alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_ALUT_LUT4_Z_D[1] = \alu_in_1[8] ; + assign \alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_ALUT_LUT4_Z_D[0] = \alu_in_1[7] ; + assign \alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B[2] = \alu_in_2[2] ; + assign \alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B[0] = \alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[0] ; + assign \alu_output_LUT4_Z_3_C_LUT4_Z_C[1] = \alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] ; + assign \alu_output_LUT4_Z_3_C_LUT4_Z_C[0] = \alu_output_LUT4_Z_3_C_LUT4_Z_A[0] ; + assign \alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[6] = \alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ; + assign \alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[5] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] ; + assign \alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[4] = \alu_in_2[1] ; + assign \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_1_D[2] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] ; + assign \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_1_D[1] = \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[2] ; + assign \alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_1_D[0] = \alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[3] ; + assign \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[6] = \alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[4] ; + assign \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[5] = \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] ; + assign \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[4] = \alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ; + assign \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] = \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[1] ; + assign \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[0] = \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[0] ; + assign \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[4] = \alu_in_2[2] ; + assign \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[3] = \alu_in_2[5] ; + assign \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[2] = \alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ; + assign \alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[1] = \alu_output_LUT4_Z_A_L6MUX21_Z_SD[2] ; + assign \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[5] = \alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] ; + assign \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[4] = \alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] ; + assign \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] = \alu_in_2[3] ; + assign \alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] = \alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[2] ; + assign \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[6] = \alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] ; + assign \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[5] = \alu_in_2[2] ; + assign \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[4] = \alu_in_2[1] ; + assign \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] = \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] ; + assign \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[0] = \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] ; + assign \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B[2] = \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] ; + assign \alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B[1] = \alu_output_LUT4_Z_A_LUT4_Z_1_C[4] ; +endmodule diff --git a/verilog/alu/v6/synth_alu6.v alu6.blif b/verilog/alu/v6/synth_alu6.v alu6.blif new file mode 100644 index 0000000..8186d4c --- /dev/null +++ b/verilog/alu/v6/synth_alu6.v alu6.blif @@ -0,0 +1 @@ +# Generated by Yosys 0.15+70 (git sha1 48d7a6c47, gcc 11.2.0 -march=x86-64 -mtune=generic -O2 -fno-plt -fexceptions -fstack-clash-protection -fcf-protection -fPIC -Os) diff --git a/verilog/alu/v6/tbalu.cpp b/verilog/alu/v6/tbalu.cpp new file mode 100644 index 0000000..6d02bf3 --- /dev/null +++ b/verilog/alu/v6/tbalu.cpp @@ -0,0 +1,44 @@ +#include <stdlib.h> +#include <iostream> +#include <verilated.h> +#include <verilated_vcd_c.h> +#include "Valu6.h" +#include "aluOp.h" + +vluint64_t sim_time = 0; + + +void benchmark(Valu6 * dut, VerilatedVcdC *m_trace, int opcodes, char op[6], char sign[6]) { + + dut->alu_op_i = opcodes; + for (int i = 0; i < 20; i++) { + for (int j = 0; j < 20; j++) { + int in1 = i - 10; + int in2 = j - 10; + dut->alu_in_1 = in1; + dut->alu_in_2 = in2; + dut->eval(); + std::cout << op <<(int) (dut->alu_in_1)<< sign << (int) dut->alu_in_2 << " = " << (int) dut->alu_output << "\n"; + sim_time++; + m_trace->dump(sim_time); + } + } +} + +int main(int argc, char** argv, char** env) { + Valu6 *dut = new Valu6; + + Verilated::traceEverOn(true); + VerilatedVcdC *m_trace = new VerilatedVcdC; + dut->trace(m_trace, 5); + m_trace->open("waveform.vcd"); + int opcodes[10] = { ADD, SUB, XOR, OR, AND, SLL, SRL, SRA, SLT, SLTU }; + char ops[10][6] = { "ADD: ", "SUB: ", "XOR: ", "OR: ", "AND: ", "SLL: ", "SRL: ", "SRA: ", "SLT: ", "SLTU:" }; + char signs[10][6] = { " + ", " - ", " ^ ", " | ", " & ", " << ", " >> ", " >>A ", " ? ", " ?U " }; + //for (int i = 0; i < 10; i++) + benchmark(dut, m_trace, SRA, ops[7], signs[7]); + + m_trace->close(); + delete dut; + exit(EXIT_SUCCESS); +} diff --git a/verilog/alu/v6/waveform.vcd b/verilog/alu/v6/waveform.vcd new file mode 100644 index 0000000..045e968 --- /dev/null +++ b/verilog/alu/v6/waveform.vcd @@ -0,0 +1,2336 @@ +$version Generated by VerilatedVcd $end +$date Sun Apr 24 19:01:39 2022 $end +$timescale 1ns $end + + $scope module TOP $end + $var wire 32 # alu_in_1 [31:0] $end + $var wire 32 $ alu_in_2 [31:0] $end + $var wire 4 % alu_op_i [3:0] $end + $var wire 32 & alu_output [31:0] $end + $var wire 4 ( debugop [3:0] $end + $var wire 32 ' debugsum [31:0] $end + $scope module alu6 $end + $var wire 32 # alu_in_1 [31:0] $end + $var wire 32 $ alu_in_2 [31:0] $end + $var wire 4 % alu_op_i [3:0] $end + $var wire 32 & alu_output [31:0] $end + $var wire 32 ) complement2 [31:0] $end + $var wire 4 ( debugop [3:0] $end + $var wire 32 ' debugsum [31:0] $end + $var wire 32 + right [31:0] $end + $var wire 32 * sum [31:0] $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#1 +b11111111111111111111111111110110 # +b11111111111111111111111111110110 $ +b1101 % +b11111111111111111111111111111111 & +b00000000000000000000000000000000 ' +b1101 ( +b00000000000000000000000000001010 ) +b00000000000000000000000000000000 * +b11111111111111111111111111111111 + +#2 +b11111111111111111111111111110111 $ +b11111111111111111111111111111111 ' +b00000000000000000000000000001001 ) +b11111111111111111111111111111111 * +#3 +b11111111111111111111111111111000 $ +b11111111111111111111111111111110 ' +b00000000000000000000000000001000 ) +b11111111111111111111111111111110 * +#4 +b11111111111111111111111111111001 $ +b11111111111111111111111111111101 ' +b00000000000000000000000000000111 ) +b11111111111111111111111111111101 * +#5 +b11111111111111111111111111111010 $ +b11111111111111111111111111111100 ' +b00000000000000000000000000000110 ) +b11111111111111111111111111111100 * +#6 +b11111111111111111111111111111011 $ +b11111111111111111111111111111011 ' +b00000000000000000000000000000101 ) +b11111111111111111111111111111011 * +#7 +b11111111111111111111111111111100 $ +b11111111111111111111111111111010 ' +b00000000000000000000000000000100 ) +b11111111111111111111111111111010 * +#8 +b11111111111111111111111111111101 $ +b11111111111111111111111111111001 ' +b00000000000000000000000000000011 ) +b11111111111111111111111111111001 * +#9 +b11111111111111111111111111111110 $ +b11111111111111111111111111111000 ' +b00000000000000000000000000000010 ) +b11111111111111111111111111111000 * +#10 +b11111111111111111111111111111111 $ +b11111111111111111111111111110111 ' +b00000000000000000000000000000001 ) +b11111111111111111111111111110111 * +#11 +b00000000000000000000000000000000 $ +b11111111111111111111111111110110 & +b11111111111111111111111111110110 ' +b00000000000000000000000000000000 ) +b11111111111111111111111111110110 * +b11111111111111111111111111110110 + +#12 +b00000000000000000000000000000001 $ +b11111111111111111111111111111011 & +b11111111111111111111111111110101 ' +b11111111111111111111111111111111 ) +b11111111111111111111111111110101 * +b11111111111111111111111111111011 + +#13 +b00000000000000000000000000000010 $ +b11111111111111111111111111111101 & +b11111111111111111111111111110100 ' +b11111111111111111111111111111110 ) +b11111111111111111111111111110100 * +b11111111111111111111111111111101 + +#14 +b00000000000000000000000000000011 $ +b11111111111111111111111111111110 & +b11111111111111111111111111110011 ' +b11111111111111111111111111111101 ) +b11111111111111111111111111110011 * +b11111111111111111111111111111110 + +#15 +b00000000000000000000000000000100 $ +b11111111111111111111111111111111 & +b11111111111111111111111111110010 ' +b11111111111111111111111111111100 ) +b11111111111111111111111111110010 * +b11111111111111111111111111111111 + +#16 +b00000000000000000000000000000101 $ +b11111111111111111111111111110001 ' +b11111111111111111111111111111011 ) +b11111111111111111111111111110001 * +#17 +b00000000000000000000000000000110 $ +b11111111111111111111111111110000 ' +b11111111111111111111111111111010 ) +b11111111111111111111111111110000 * +#18 +b00000000000000000000000000000111 $ +b11111111111111111111111111101111 ' +b11111111111111111111111111111001 ) +b11111111111111111111111111101111 * +#19 +b00000000000000000000000000001000 $ +b11111111111111111111111111101110 ' +b11111111111111111111111111111000 ) +b11111111111111111111111111101110 * +#20 +b00000000000000000000000000001001 $ +b11111111111111111111111111101101 ' +b11111111111111111111111111110111 ) +b11111111111111111111111111101101 * +#21 +b11111111111111111111111111110111 # +b11111111111111111111111111110110 $ +b00000000000000000000000000000001 ' +b00000000000000000000000000001010 ) +b00000000000000000000000000000001 * +#22 +b11111111111111111111111111110111 $ +b00000000000000000000000000000000 ' +b00000000000000000000000000001001 ) +b00000000000000000000000000000000 * +#23 +b11111111111111111111111111111000 $ +b11111111111111111111111111111111 ' +b00000000000000000000000000001000 ) +b11111111111111111111111111111111 * +#24 +b11111111111111111111111111111001 $ +b11111111111111111111111111111110 ' +b00000000000000000000000000000111 ) +b11111111111111111111111111111110 * +#25 +b11111111111111111111111111111010 $ +b11111111111111111111111111111101 ' +b00000000000000000000000000000110 ) +b11111111111111111111111111111101 * +#26 +b11111111111111111111111111111011 $ +b11111111111111111111111111111100 ' +b00000000000000000000000000000101 ) +b11111111111111111111111111111100 * +#27 +b11111111111111111111111111111100 $ +b11111111111111111111111111111011 ' +b00000000000000000000000000000100 ) +b11111111111111111111111111111011 * +#28 +b11111111111111111111111111111101 $ +b11111111111111111111111111111010 ' +b00000000000000000000000000000011 ) +b11111111111111111111111111111010 * +#29 +b11111111111111111111111111111110 $ +b11111111111111111111111111111001 ' +b00000000000000000000000000000010 ) +b11111111111111111111111111111001 * +#30 +b11111111111111111111111111111111 $ +b11111111111111111111111111111000 ' +b00000000000000000000000000000001 ) +b11111111111111111111111111111000 * +#31 +b00000000000000000000000000000000 $ +b11111111111111111111111111110111 & +b11111111111111111111111111110111 ' +b00000000000000000000000000000000 ) +b11111111111111111111111111110111 * +b11111111111111111111111111110111 + +#32 +b00000000000000000000000000000001 $ +b11111111111111111111111111111011 & +b11111111111111111111111111110110 ' +b11111111111111111111111111111111 ) +b11111111111111111111111111110110 * +b11111111111111111111111111111011 + +#33 +b00000000000000000000000000000010 $ +b11111111111111111111111111111101 & +b11111111111111111111111111110101 ' +b11111111111111111111111111111110 ) +b11111111111111111111111111110101 * +b11111111111111111111111111111101 + +#34 +b00000000000000000000000000000011 $ +b11111111111111111111111111111110 & +b11111111111111111111111111110100 ' +b11111111111111111111111111111101 ) +b11111111111111111111111111110100 * +b11111111111111111111111111111110 + +#35 +b00000000000000000000000000000100 $ +b11111111111111111111111111111111 & +b11111111111111111111111111110011 ' +b11111111111111111111111111111100 ) +b11111111111111111111111111110011 * +b11111111111111111111111111111111 + +#36 +b00000000000000000000000000000101 $ +b11111111111111111111111111110010 ' +b11111111111111111111111111111011 ) +b11111111111111111111111111110010 * +#37 +b00000000000000000000000000000110 $ +b11111111111111111111111111110001 ' +b11111111111111111111111111111010 ) +b11111111111111111111111111110001 * +#38 +b00000000000000000000000000000111 $ +b11111111111111111111111111110000 ' +b11111111111111111111111111111001 ) +b11111111111111111111111111110000 * +#39 +b00000000000000000000000000001000 $ +b11111111111111111111111111101111 ' +b11111111111111111111111111111000 ) +b11111111111111111111111111101111 * +#40 +b00000000000000000000000000001001 $ +b11111111111111111111111111101110 ' +b11111111111111111111111111110111 ) +b11111111111111111111111111101110 * +#41 +b11111111111111111111111111111000 # +b11111111111111111111111111110110 $ +b00000000000000000000000000000010 ' +b00000000000000000000000000001010 ) +b00000000000000000000000000000010 * +#42 +b11111111111111111111111111110111 $ +b00000000000000000000000000000001 ' +b00000000000000000000000000001001 ) +b00000000000000000000000000000001 * +#43 +b11111111111111111111111111111000 $ +b00000000000000000000000000000000 ' +b00000000000000000000000000001000 ) +b00000000000000000000000000000000 * +#44 +b11111111111111111111111111111001 $ +b11111111111111111111111111111111 ' +b00000000000000000000000000000111 ) +b11111111111111111111111111111111 * +#45 +b11111111111111111111111111111010 $ +b11111111111111111111111111111110 ' +b00000000000000000000000000000110 ) +b11111111111111111111111111111110 * +#46 +b11111111111111111111111111111011 $ +b11111111111111111111111111111101 ' +b00000000000000000000000000000101 ) +b11111111111111111111111111111101 * +#47 +b11111111111111111111111111111100 $ +b11111111111111111111111111111100 ' +b00000000000000000000000000000100 ) +b11111111111111111111111111111100 * +#48 +b11111111111111111111111111111101 $ +b11111111111111111111111111111011 ' +b00000000000000000000000000000011 ) +b11111111111111111111111111111011 * +#49 +b11111111111111111111111111111110 $ +b11111111111111111111111111111010 ' +b00000000000000000000000000000010 ) +b11111111111111111111111111111010 * +#50 +b11111111111111111111111111111111 $ +b11111111111111111111111111111001 ' +b00000000000000000000000000000001 ) +b11111111111111111111111111111001 * +#51 +b00000000000000000000000000000000 $ +b11111111111111111111111111111000 & +b11111111111111111111111111111000 ' +b00000000000000000000000000000000 ) +b11111111111111111111111111111000 * +b11111111111111111111111111111000 + +#52 +b00000000000000000000000000000001 $ +b11111111111111111111111111111100 & +b11111111111111111111111111110111 ' +b11111111111111111111111111111111 ) +b11111111111111111111111111110111 * +b11111111111111111111111111111100 + +#53 +b00000000000000000000000000000010 $ +b11111111111111111111111111111110 & +b11111111111111111111111111110110 ' +b11111111111111111111111111111110 ) +b11111111111111111111111111110110 * +b11111111111111111111111111111110 + +#54 +b00000000000000000000000000000011 $ +b11111111111111111111111111111111 & +b11111111111111111111111111110101 ' +b11111111111111111111111111111101 ) +b11111111111111111111111111110101 * +b11111111111111111111111111111111 + +#55 +b00000000000000000000000000000100 $ +b11111111111111111111111111110100 ' +b11111111111111111111111111111100 ) +b11111111111111111111111111110100 * +#56 +b00000000000000000000000000000101 $ +b11111111111111111111111111110011 ' +b11111111111111111111111111111011 ) +b11111111111111111111111111110011 * +#57 +b00000000000000000000000000000110 $ +b11111111111111111111111111110010 ' +b11111111111111111111111111111010 ) +b11111111111111111111111111110010 * +#58 +b00000000000000000000000000000111 $ +b11111111111111111111111111110001 ' +b11111111111111111111111111111001 ) +b11111111111111111111111111110001 * +#59 +b00000000000000000000000000001000 $ +b11111111111111111111111111110000 ' +b11111111111111111111111111111000 ) +b11111111111111111111111111110000 * +#60 +b00000000000000000000000000001001 $ +b11111111111111111111111111101111 ' +b11111111111111111111111111110111 ) +b11111111111111111111111111101111 * +#61 +b11111111111111111111111111111001 # +b11111111111111111111111111110110 $ +b00000000000000000000000000000011 ' +b00000000000000000000000000001010 ) +b00000000000000000000000000000011 * +#62 +b11111111111111111111111111110111 $ +b00000000000000000000000000000010 ' +b00000000000000000000000000001001 ) +b00000000000000000000000000000010 * +#63 +b11111111111111111111111111111000 $ +b00000000000000000000000000000001 ' +b00000000000000000000000000001000 ) +b00000000000000000000000000000001 * +#64 +b11111111111111111111111111111001 $ +b00000000000000000000000000000000 ' +b00000000000000000000000000000111 ) +b00000000000000000000000000000000 * +#65 +b11111111111111111111111111111010 $ +b11111111111111111111111111111111 ' +b00000000000000000000000000000110 ) +b11111111111111111111111111111111 * +#66 +b11111111111111111111111111111011 $ +b11111111111111111111111111111110 ' +b00000000000000000000000000000101 ) +b11111111111111111111111111111110 * +#67 +b11111111111111111111111111111100 $ +b11111111111111111111111111111101 ' +b00000000000000000000000000000100 ) +b11111111111111111111111111111101 * +#68 +b11111111111111111111111111111101 $ +b11111111111111111111111111111100 ' +b00000000000000000000000000000011 ) +b11111111111111111111111111111100 * +#69 +b11111111111111111111111111111110 $ +b11111111111111111111111111111011 ' +b00000000000000000000000000000010 ) +b11111111111111111111111111111011 * +#70 +b11111111111111111111111111111111 $ +b11111111111111111111111111111010 ' +b00000000000000000000000000000001 ) +b11111111111111111111111111111010 * +#71 +b00000000000000000000000000000000 $ +b11111111111111111111111111111001 & +b11111111111111111111111111111001 ' +b00000000000000000000000000000000 ) +b11111111111111111111111111111001 * +b11111111111111111111111111111001 + +#72 +b00000000000000000000000000000001 $ +b11111111111111111111111111111100 & +b11111111111111111111111111111000 ' +b11111111111111111111111111111111 ) +b11111111111111111111111111111000 * +b11111111111111111111111111111100 + +#73 +b00000000000000000000000000000010 $ +b11111111111111111111111111111110 & +b11111111111111111111111111110111 ' +b11111111111111111111111111111110 ) +b11111111111111111111111111110111 * +b11111111111111111111111111111110 + +#74 +b00000000000000000000000000000011 $ +b11111111111111111111111111111111 & +b11111111111111111111111111110110 ' +b11111111111111111111111111111101 ) +b11111111111111111111111111110110 * +b11111111111111111111111111111111 + +#75 +b00000000000000000000000000000100 $ +b11111111111111111111111111110101 ' +b11111111111111111111111111111100 ) +b11111111111111111111111111110101 * +#76 +b00000000000000000000000000000101 $ +b11111111111111111111111111110100 ' +b11111111111111111111111111111011 ) +b11111111111111111111111111110100 * +#77 +b00000000000000000000000000000110 $ +b11111111111111111111111111110011 ' +b11111111111111111111111111111010 ) +b11111111111111111111111111110011 * +#78 +b00000000000000000000000000000111 $ +b11111111111111111111111111110010 ' +b11111111111111111111111111111001 ) +b11111111111111111111111111110010 * +#79 +b00000000000000000000000000001000 $ +b11111111111111111111111111110001 ' +b11111111111111111111111111111000 ) +b11111111111111111111111111110001 * +#80 +b00000000000000000000000000001001 $ +b11111111111111111111111111110000 ' +b11111111111111111111111111110111 ) +b11111111111111111111111111110000 * +#81 +b11111111111111111111111111111010 # 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