diff options
Diffstat (limited to 'verilog/alu/v6/obj_dir/Valu6.cpp')
| -rw-r--r-- | verilog/alu/v6/obj_dir/Valu6.cpp | 207 |
1 files changed, 207 insertions, 0 deletions
diff --git a/verilog/alu/v6/obj_dir/Valu6.cpp b/verilog/alu/v6/obj_dir/Valu6.cpp new file mode 100644 index 0000000..2e02259 --- /dev/null +++ b/verilog/alu/v6/obj_dir/Valu6.cpp @@ -0,0 +1,207 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design implementation internals +// See Valu6.h for the primary calling header + +#include "Valu6.h" +#include "Valu6__Syms.h" + +//========== + +void Valu6::eval_step() { + VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate Valu6::eval\n"); ); + Valu6__Syms* __restrict vlSymsp = this->__VlSymsp; // Setup global symbol table + Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; +#ifdef VL_DEBUG + // Debug assertions + _eval_debug_assertions(); +#endif // VL_DEBUG + // Initialize + if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp); + // Evaluate till stable + int __VclockLoop = 0; + QData __Vchange = 1; + do { + VL_DEBUG_IF(VL_DBG_MSGF("+ Clock loop\n");); + vlSymsp->__Vm_activity = true; + _eval(vlSymsp); + if (VL_UNLIKELY(++__VclockLoop > 100)) { + // About to fail, so enable debug to see what's not settling. + // Note you must run make with OPT=-DVL_DEBUG for debug prints. + int __Vsaved_debug = Verilated::debug(); + Verilated::debug(1); + __Vchange = _change_request(vlSymsp); + Verilated::debug(__Vsaved_debug); + VL_FATAL_MT("alu6.v", 6, "", + "Verilated model didn't converge\n" + "- See DIDNOTCONVERGE in the Verilator manual"); + } else { + __Vchange = _change_request(vlSymsp); + } + } while (VL_UNLIKELY(__Vchange)); +} + +void Valu6::_eval_initial_loop(Valu6__Syms* __restrict vlSymsp) { + vlSymsp->__Vm_didInit = true; + _eval_initial(vlSymsp); + vlSymsp->__Vm_activity = true; + // Evaluate till stable + int __VclockLoop = 0; + QData __Vchange = 1; + do { + _eval_settle(vlSymsp); + _eval(vlSymsp); + if (VL_UNLIKELY(++__VclockLoop > 100)) { + // About to fail, so enable debug to see what's not settling. + // Note you must run make with OPT=-DVL_DEBUG for debug prints. + int __Vsaved_debug = Verilated::debug(); + Verilated::debug(1); + __Vchange = _change_request(vlSymsp); + Verilated::debug(__Vsaved_debug); + VL_FATAL_MT("alu6.v", 6, "", + "Verilated model didn't DC converge\n" + "- See DIDNOTCONVERGE in the Verilator manual"); + } else { + __Vchange = _change_request(vlSymsp); + } + } while (VL_UNLIKELY(__Vchange)); +} + +VL_INLINE_OPT void Valu6::_combo__TOP__1(Valu6__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6::_combo__TOP__1\n"); ); + Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->alu6__DOT__sum = (vlTOPp->alu_in_1 + ((1U + & (((IData)(vlTOPp->alu_op_i) + >> 3U) + | (((IData)(vlTOPp->alu_op_i) + >> 1U) + & (~ (IData)(vlTOPp->alu_op_i))))) + ? + ((IData)(1U) + + + (~ vlTOPp->alu_in_2)) + : vlTOPp->alu_in_2)); + vlTOPp->alu_output = ((0U == (7U & (IData)(vlTOPp->alu_op_i))) + ? vlTOPp->alu6__DOT__sum + : ((4U == (7U & (IData)(vlTOPp->alu_op_i))) + ? (vlTOPp->alu_in_1 + ^ vlTOPp->alu_in_2) + : ((6U == (7U & (IData)(vlTOPp->alu_op_i))) + ? (vlTOPp->alu_in_1 + | vlTOPp->alu_in_2) + : ((7U == (7U & (IData)(vlTOPp->alu_op_i))) + ? (vlTOPp->alu_in_1 + & vlTOPp->alu_in_2) + : ((1U == (7U + & (IData)(vlTOPp->alu_op_i))) + ? ((0x40U + & vlTOPp->alu_in_2) + ? 0U + : ((0x1fU + >= + (0x3fU + & vlTOPp->alu_in_2)) + ? + (vlTOPp->alu_in_1 + << + (0x3fU + & vlTOPp->alu_in_2)) + : 0U)) + : ((5U == + (7U + & (IData)(vlTOPp->alu_op_i))) + ? (( + (0x1fU + >= + (0x3fU + & vlTOPp->alu_in_2)) + ? + (vlTOPp->alu_in_1 + >> + (0x3fU + & vlTOPp->alu_in_2)) + : 0U) + | ((8U + & (IData)(vlTOPp->alu_op_i)) + ? + ((IData)(0xffffffffU) + << + ((0x80000000U + & vlTOPp->alu_in_2) + ? 0U + : + ((0x10U + & ((~ + (vlTOPp->alu_in_2 + >> 4U)) + << 4U)) + | ((8U + & ((~ + (vlTOPp->alu_in_2 + >> 3U)) + << 3U)) + | ((4U + & ((~ + (vlTOPp->alu_in_2 + >> 2U)) + << 2U)) + | ((2U + & ((~ + (vlTOPp->alu_in_2 + >> 1U)) + << 1U)) + | (1U + & (~ vlTOPp->alu_in_2)))))))) + : 0U)) + : ((2U + == + (7U + & (IData)(vlTOPp->alu_op_i))) + ? + (1U + & (vlTOPp->alu6__DOT__sum + >> 0x1fU)) + : + ((3U + == + (7U + & (IData)(vlTOPp->alu_op_i))) + ? + ((vlTOPp->alu_in_1 + < vlTOPp->alu_in_2) + ? 1U + : 0U) + : 0U)))))))); +} + +void Valu6::_eval(Valu6__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6::_eval\n"); ); + Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->_combo__TOP__1(vlSymsp); +} + +VL_INLINE_OPT QData Valu6::_change_request(Valu6__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6::_change_request\n"); ); + Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + return (vlTOPp->_change_request_1(vlSymsp)); +} + +VL_INLINE_OPT QData Valu6::_change_request_1(Valu6__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6::_change_request_1\n"); ); + Valu6* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + // Change detection + QData __req = false; // Logically a bool + return __req; +} + +#ifdef VL_DEBUG +void Valu6::_eval_debug_assertions() { + VL_DEBUG_IF(VL_DBG_MSGF("+ Valu6::_eval_debug_assertions\n"); ); + // Body + if (VL_UNLIKELY((alu_op_i & 0xf0U))) { + Verilated::overWidthError("alu_op_i");} +} +#endif // VL_DEBUG |