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Diffstat (limited to 'verilog/alu/v6/obj_dir/Valu6___024root__Slow.cpp')
-rw-r--r--verilog/alu/v6/obj_dir/Valu6___024root__Slow.cpp8
1 files changed, 4 insertions, 4 deletions
diff --git a/verilog/alu/v6/obj_dir/Valu6___024root__Slow.cpp b/verilog/alu/v6/obj_dir/Valu6___024root__Slow.cpp
index 9918041..4167b09 100644
--- a/verilog/alu/v6/obj_dir/Valu6___024root__Slow.cpp
+++ b/verilog/alu/v6/obj_dir/Valu6___024root__Slow.cpp
@@ -9,16 +9,16 @@
void Valu6___024root___ctor_var_reset(Valu6___024root* vlSelf);
-Valu6___024root::Valu6___024root(const char* _vcname__)
- : VerilatedModule(_vcname__)
+Valu6___024root::Valu6___024root(Valu6__Syms* symsp, const char* name)
+ : VerilatedModule{name}
+ , vlSymsp{symsp}
{
// Reset structure values
Valu6___024root___ctor_var_reset(this);
}
-void Valu6___024root::__Vconfigure(Valu6__Syms* _vlSymsp, bool first) {
+void Valu6___024root::__Vconfigure(bool first) {
if (false && first) {} // Prevent unused
- this->vlSymsp = _vlSymsp;
}
Valu6___024root::~Valu6___024root() {