1 files changed, 0 insertions, 36 deletions
diff --git a/verilog/fpu/fpu_3.v b/verilog/fpu/fpu_3.v
deleted file mode 100644
index 69c7cec..0000000
--- a/verilog/fpu/fpu_3.v
+++ /dev/null
@@ -1,36 +0,0 @@
-module fpu_3(
-	input wire add_not,
-	input wire [31:0] a_in, b_in,
-	output wire[31:0] out
-);
-
-wire[7:0] diff, neg_diff, exp;
-assign diff = a_in[30:23] - b_in[30:23];
-assign neg_diff = b_in[30:23] - a_in[30:23];
-assign exp = diff[7] ? b_in[30:23] : a_in[30:23];
-
-// Pull hidden bit into sig, if exp 0, no hidden bit
-wire[23:0] a_sig, b_sig;
-assign a_sig = (|a_in[30:23] ? {1'b1, a_in[22:0]} : {1'b0, a_in[22:0]});
-assign b_sig = (|b_in[30:23] ? {1'b1, b_in[22:0]} : {1'b0, b_in[22:0]});
-
-//Denormalize correct one
-wire[23:0] a_shift_sig, b_shift_sig;
-assign a_shift_sig = (diff[7] ? a_sig >> neg_diff : a_sig);
-assign b_shift_sig = (diff[7] ? b_sig : b_sig >> diff);
-
-// Set signed based on inputs and signs
-wire[23:0] a_signed_sig, b_signed_sig;
-assign a_signed_sig = b[31] & (~(add_not ^ b_in[31])) ? ~a_shift_sig + 1'b1 : a_shift_sig;
-assign b_signed_sig = ~a[31] & (add_not ^ b_in[31]) ? ~b_shift_sig + 1'b1; : b_shift_sig;
-
-
-wire[24:0] sum_sig;
-assign sum_sig = a_signed_sig + b_signed_sig;
-
-wire[24:0] signed_sum_sig;
-assign signed_sum_sig = ~(a_in[31] ^ b_in[31]) ? sum_sig :
-
-assign out[31] = ;
-
-endmodule