1 files changed, 22 insertions, 0 deletions
diff --git a/verilog/register/registers.v b/verilog/register/registers.v
new file mode 100644
index 0000000..f2dbb22
--- /dev/null
+++ b/verilog/register/registers.v
@@ -0,0 +1,22 @@
+module registers(
+	input wire writeEnable,
+	input wire clk,
+	input wire [31:0] addr1,
+	input wire [31:0] addr2,
+	input wire [31:0] addr3,
+	input wire [31:0] writeData,
+	output wire [31:0] readData1,
+	output wire [31:0] readData2
+);
+
+reg [31:0] register [0:31];
+
+always @ (posedge clk)
+begin
+	register[addr3] <= writeEnable ? writeData : register[addr3];
+end
+
+assign readData1 = register[addr1];
+assign readData2 = register[addr2];
+
+endmodule