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author | joshua <joshua@joshuayun.com> | 2022-04-16 23:00:55 -0500 |
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committer | joshua <joshua@joshuayun.com> | 2022-04-16 23:00:55 -0500 |
commit | d6b7d26cf51b4b3a7b5604f9b81bb43f55cbc33c (patch) | |
tree | c337d4454d3a4d5aa01ad3531e8c723b09fe7d0e /verilog/register/registers.v | |
parent | 2f1be3c7aabb42ac3ad4347595d5d7be0e2ad6a0 (diff) | |
download | riscv-processor-inorder-d6b7d26cf51b4b3a7b5604f9b81bb43f55cbc33c.tar.gz |
Added pdfs and more alu stuff
Diffstat (limited to 'verilog/register/registers.v')
-rw-r--r-- | verilog/register/registers.v | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/verilog/register/registers.v b/verilog/register/registers.v new file mode 100644 index 0000000..f2dbb22 --- /dev/null +++ b/verilog/register/registers.v @@ -0,0 +1,22 @@ +module registers( + input wire writeEnable, + input wire clk, + input wire [31:0] addr1, + input wire [31:0] addr2, + input wire [31:0] addr3, + input wire [31:0] writeData, + output wire [31:0] readData1, + output wire [31:0] readData2 +); + +reg [31:0] register [0:31]; + +always @ (posedge clk) +begin + register[addr3] <= writeEnable ? writeData : register[addr3]; +end + +assign readData1 = register[addr1]; +assign readData2 = register[addr2]; + +endmodule |