verilog/alu/v6/obj_dir/Valu6__Syms.cpp


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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table implementation internals

#include "Valu6__Syms.h"
#include "Valu6.h"
#include "Valu6___024root.h"

// FUNCTIONS
Valu6__Syms::~Valu6__Syms()
{
}

Valu6__Syms::Valu6__Syms(VerilatedContext* contextp, const char* namep,Valu6* modelp)
    : VerilatedSyms{contextp}
    // Setup internal state of the Syms class
    , __Vm_modelp{modelp}
    // Setup module instances
    , TOP{this, namep}
{
    // Configure time unit / time precision
    _vm_contextp__->timeunit(-6);
    _vm_contextp__->timeprecision(-9);
    // Setup each module's pointers to their submodules
    // Setup each module's pointer back to symbol table (for public functions)
    TOP.__Vconfigure(true);
}