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module registers(
input wire writeEnable,
input wire clk,
input wire [31:0] addr1,
input wire [31:0] addr2,
input wire [31:0] addr3,
input wire [31:0] writeData,
output wire [31:0] readData1,
output wire [31:0] readData2
);
reg [31:0] register [0:31];
always @ (posedge clk)
begin
register[addr3] <= writeEnable ? writeData : register[addr3];
end
assign readData1 = register[addr1];
assign readData2 = register[addr2];
endmodule
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