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| author | Joshua Yun <joshua@joshuayun.com> | 2025-03-15 23:09:39 -0500 |
|---|---|---|
| committer | Joshua Yun <joshua@joshuayun.com> | 2025-03-15 23:09:39 -0500 |
| commit | 6bd9f4f7ab48576d3fda98bef915162a7436866d (patch) | |
| tree | a0af72467af1020f9e492b177e2d95ed8998d1dc /README.md | |
| parent | 59fd8c25ee1452452cb564d6fe4163b7a9394aef (diff) | |
| download | riscv-processor-6bd9f4f7ab48576d3fda98bef915162a7436866d.tar.gz | |
feat: More setting up, got a janky decode stage that prints out the instruction it receives, added dump options to fusesoc, changed instr width back th 32 from 64
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 4 |
1 files changed, 3 insertions, 1 deletions
@@ -1,3 +1,5 @@ # RISCV_Linux -Building a project with fusesoc +Running core testbench + + fusesoc run --target sim bingchao:riscv:cpu |