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authorJoshua Yun <joshua@joshuayun.com>2025-03-15 17:35:52 -0500
committerJoshua Yun <joshua@joshuayun.com>2025-03-15 17:35:52 -0500
commit59fd8c25ee1452452cb564d6fe4163b7a9394aef (patch)
tree028688a39cd401a40939d86e3bf4a8f5d678d6a4 /core/rtl/core.sv
parentc7a29c00b143ff6ee22bb7cffbdd0ae7c21206d1 (diff)
downloadriscv-processor-59fd8c25ee1452452cb564d6fe4163b7a9394aef.tar.gz
feat: added TB support + primitives for flipflops, initial fetch stage (not complete), mem initialization for imem complete
Diffstat (limited to 'core/rtl/core.sv')
-rw-r--r--core/rtl/core.sv22
1 files changed, 22 insertions, 0 deletions
diff --git a/core/rtl/core.sv b/core/rtl/core.sv
new file mode 100644
index 0000000..5f64e7a
--- /dev/null
+++ b/core/rtl/core.sv
@@ -0,0 +1,22 @@
+module core
+(
+ input logic clk,
+ input logic rst_l,
+ // Instruction mem interface
+ output logic [63:0] if_imem_addr_IF,
+ input logic [63:0] imem_id_instr_ID
+
+ // Data mem interface
+);
+
+fetch fetch0 (
+ .clk(clk),
+ .rst_l(rst_l),
+ .if_imem_addr_IF(if_imem_addr_IF)
+);
+
+always @ (posedge clk) begin
+ $display("Instruction: %x", imem_id_instr_ID);
+end
+
+endmodule