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author | Joshua Yun <joshua@joshuayun.com> | 2025-03-15 17:35:52 -0500 |
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committer | Joshua Yun <joshua@joshuayun.com> | 2025-03-15 17:35:52 -0500 |
commit | 59fd8c25ee1452452cb564d6fe4163b7a9394aef (patch) | |
tree | 028688a39cd401a40939d86e3bf4a8f5d678d6a4 /core/rtl/fetch.sv | |
parent | c7a29c00b143ff6ee22bb7cffbdd0ae7c21206d1 (diff) | |
download | riscv-processor-59fd8c25ee1452452cb564d6fe4163b7a9394aef.tar.gz |
feat: added TB support + primitives for flipflops, initial fetch stage (not complete), mem initialization for imem complete
Diffstat (limited to 'core/rtl/fetch.sv')
-rw-r--r-- | core/rtl/fetch.sv | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/core/rtl/fetch.sv b/core/rtl/fetch.sv new file mode 100644 index 0000000..7cbff6a --- /dev/null +++ b/core/rtl/fetch.sv @@ -0,0 +1,20 @@ +module fetch +( + input logic clk, + input logic rst_l, + + // IMEM interface + output logic [63:0] if_imem_addr_IF +); + +logic [63:0] pc_IF; +logic [63:0] pcNxt_IF; + +assign if_imem_addr_IF = pc_IF; // Always fetch PC from IMEM, truncate addresses to be 64 bit aligned? + +// Program Counter (PC) +assign pcNxt_IF = pc_IF + 64'd4; + +AFFR #(.WIDTH(64)) ff_IF_pc ( .clk(clk), .rst_l(rst_l), .en(1'b1), .q(pc_IF), .d(pcNxt_IF) ); + +endmodule |