feat: added TB support + primitives for flipflops, initial fetch stage (not complete), mem initialization for imem complete

1 files changed, 0 insertions, 31 deletions

diff --git a/top.core b/top.core
deleted file mode 100644
index db67ab4..0000000
--- a/top.core
+++ /dev/null
@@ -1,31 +0,0 @@
-CAPI=2:
-name: riscv:cpu:top:1.0.0
-description: Top level module for RISC-V processor
-
-filesets:
-  rtl:
-    files:
-      - rtl/top.sv
-    file_type: systemVerilogSource
-
-  tb:
-    files:
-      - tb/top_tb.sv
-    file_type: systemVerilogSource
-
-targets:
-  default: &default
-    filesets:
-      - rtl
-    toplevel: top
-
-  sim:
-    <<: *default
-    description: Run top level testbench
-    default_tool: verilator
-    filesets_append:
-      - tb
-    toplevel: top_tb
-    tools:
-      verilator:
-        mode: binary