diff options
| author | joshua <joshua@joshuayun.com> | 2023-12-30 23:54:31 -0500 |
|---|---|---|
| committer | joshua <joshua@joshuayun.com> | 2023-12-30 23:54:31 -0500 |
| commit | 86608c6770cf08c138a2bdab5855072f64be09ef (patch) | |
| tree | 494a61b3ef37e76f9235a0d10f5c93d97290a35f /Core | |
| download | sdr-software-master.tar.gz | |
Diffstat (limited to 'Core')
| -rw-r--r-- | Core/Inc/AD9851.h | 5 | ||||
| -rw-r--r-- | Core/Inc/Si5351A-RevB-Registers.h | 265 | ||||
| -rw-r--r-- | Core/Inc/main.h | 107 | ||||
| -rw-r--r-- | Core/Inc/stm32h7xx_hal_conf.h | 515 | ||||
| -rw-r--r-- | Core/Inc/stm32h7xx_it.h | 69 | ||||
| -rw-r--r-- | Core/Src/AD9851.c | 59 | ||||
| -rw-r--r-- | Core/Src/main.c | 707 | ||||
| -rw-r--r-- | Core/Src/stm32h7xx_hal_msp.c | 476 | ||||
| -rw-r--r-- | Core/Src/stm32h7xx_it.c | 247 | ||||
| -rw-r--r-- | Core/Src/system_stm32h7xx.c | 450 |
10 files changed, 2900 insertions, 0 deletions
diff --git a/Core/Inc/AD9851.h b/Core/Inc/AD9851.h new file mode 100644 index 0000000..7d80e32 --- /dev/null +++ b/Core/Inc/AD9851.h @@ -0,0 +1,5 @@ +#include "main.h"
+
+void AD9851_reset(void);
+
+void AD9851_parallel(uint32_t freq);
\ No newline at end of file diff --git a/Core/Inc/Si5351A-RevB-Registers.h b/Core/Inc/Si5351A-RevB-Registers.h new file mode 100644 index 0000000..5ee3d06 --- /dev/null +++ b/Core/Inc/Si5351A-RevB-Registers.h @@ -0,0 +1,265 @@ +/*
+ * Si5351A Rev B Configuration Register Export Header File
+ *
+ * This file represents a series of Skyworks Si5351A Rev B
+ * register writes that can be performed to load a single configuration
+ * on a device. It was created by a Skyworks ClockBuilder Pro
+ * export tool.
+ *
+ * Part: Si5351A Rev B
+ * Design ID:
+ * Includes Pre/Post Download Control Register Writes: Yes
+ * Created By: ClockBuilder Pro v4.11.0.1 [2023-09-14]
+ * Timestamp: 2023-12-05 04:14:31 GMT-06:00
+ *
+ * A complete design report corresponding to this export is included at the end
+ * of this header file.
+ *
+ */
+
+#ifndef SI5351A_REVB_REG_CONFIG_HEADER
+#define SI5351A_REVB_REG_CONFIG_HEADER
+
+#define SI5351A_REVB_REG_CONFIG_NUM_REGS 61
+
+typedef struct
+{
+ uint8_t address; /* 16-bit register address */
+ uint8_t value; /* 8-bit register data */
+
+} si5351a_revb_register_t;
+
+si5351a_revb_register_t const si5351a_revb_registers[SI5351A_REVB_REG_CONFIG_NUM_REGS] =
+{
+ { 0x02, 0x53 },
+ { 0x03, 0x00 },
+ { 0x04, 0x20 },
+ { 0x07, 0x00 },
+ { 0x0F, 0x00 },
+ { 0x10, 0x0F },
+ { 0x11, 0x0F },
+ { 0x12, 0x0F },
+ { 0x13, 0x8C },
+ { 0x14, 0x8C },
+ { 0x15, 0x8C },
+ { 0x16, 0x8C },
+ { 0x17, 0x8C },
+ { 0x1A, 0x00 },
+ { 0x1B, 0x01 },
+ { 0x1C, 0x00 },
+ { 0x1D, 0x10 },
+ { 0x1E, 0x00 },
+ { 0x1F, 0x00 },
+ { 0x20, 0x00 },
+ { 0x21, 0x00 },
+ { 0x2A, 0x00 },
+ { 0x2B, 0x01 },
+ { 0x2C, 0x00 },
+ { 0x2D, 0x0D },
+ { 0x2E, 0x00 },
+ { 0x2F, 0x00 },
+ { 0x30, 0x00 },
+ { 0x31, 0x00 },
+ { 0x32, 0x00 },
+ { 0x33, 0x04 },
+ { 0x34, 0x62 },
+ { 0x35, 0xBD },
+ { 0x36, 0x20 },
+ { 0x37, 0x00 },
+ { 0x38, 0x00 },
+ { 0x39, 0x00 },
+ { 0x3A, 0x00 },
+ { 0x3B, 0x04 },
+ { 0x3C, 0x62 },
+ { 0x3D, 0xBD },
+ { 0x3E, 0x20 },
+ { 0x3F, 0x00 },
+ { 0x40, 0x00 },
+ { 0x41, 0x00 },
+ { 0x5A, 0x00 },
+ { 0x5B, 0x00 },
+ { 0x95, 0x00 },
+ { 0x96, 0x00 },
+ { 0x97, 0x00 },
+ { 0x98, 0x00 },
+ { 0x99, 0x00 },
+ { 0x9A, 0x00 },
+ { 0x9B, 0x00 },
+ { 0xA2, 0x00 },
+ { 0xA3, 0x00 },
+ { 0xA4, 0x00 },
+ { 0xA5, 0x00 },
+ { 0xA6, 0x00 },
+ { 0xA7, 0x00 },
+ { 0xB7, 0xD2 },
+
+};
+
+/*
+ * Design Report
+ *
+ * Overview
+ * ========
+ *
+ * Part: Si5351A
+ * Project File: C:\Users\ldu08\Downloads\Si5351A-RevB-Project.slabtimeproj
+ * Created By: ClockBuilder Pro v4.11.0.1 [2023-09-14]
+ * Timestamp: 2023-12-05 04:14:31 GMT-06:00
+ *
+ * Design Rule Check
+ * =================
+ *
+ * Errors:
+ * - No errors
+ *
+ * Warnings:
+ * - No warnings
+ *
+ * Design
+ * ======
+ * I2C Address: 0x60
+ *
+ * Inputs:
+ * IN0: 25 MHz
+ *
+ * Outputs:
+ * OUT0: 30 MHz
+ * Enabled LVCMOS 8 mA
+ * Offset 0.000 s
+ * OUT1: 10 kHz
+ * Enabled LVCMOS 8 mA
+ * Offset 0.000 s
+ * OUT2: 10 kHz
+ * Enabled LVCMOS 8 mA
+ * Offset 0.000 s
+ *
+ * Frequency Plan
+ * ==============
+ *
+ * PLL_A:
+ * Enabled Features = None
+ * Fvco = 900 MHz
+ * M = 36
+ * Input0:
+ * Source = Crystal
+ * Source Frequency = 25 MHz
+ * Fpfd = 25 MHz
+ * Load Capacitance = Load_10pF
+ * Output0:
+ * Features = None
+ * Disabled State = StopLow
+ * R = 1 (2^0)
+ * Fout = 30 MHz
+ * N = 30
+ * Output1:
+ * Features = None
+ * Disabled State = StopLow
+ * R = 64 (2^6)
+ * Fout = 10 kHz
+ * N = 1406.25
+ * Output2:
+ * Features = None
+ * Disabled State = StopLow
+ * R = 64 (2^6)
+ * Fout = 10 kHz
+ * N = 1406.25
+ *
+ * Settings
+ * ========
+ *
+ * Location Setting Name Decimal Value Hex Value
+ * ------------ -------------- ----------------- -----------------
+ * 0x0002[3] XO_LOS_MASK 0 0x0
+ * 0x0002[4] CLK_LOS_MASK 1 0x1
+ * 0x0002[5] LOL_A_MASK 0 0x0
+ * 0x0002[6] LOL_B_MASK 1 0x1
+ * 0x0002[7] SYS_INIT_MASK 0 0x0
+ * 0x0003[7:0] CLK_OEB 0 0x00
+ * 0x0004[4] DIS_RESET_LOLA 0 0x0
+ * 0x0004[5] DIS_RESET_LOLB 1 0x1
+ * 0x0007[7:4] I2C_ADDR_CTRL 0 0x0
+ * 0x000F[2] PLLA_SRC 0 0x0
+ * 0x000F[3] PLLB_SRC 0 0x0
+ * 0x000F[4] PLLA_INSELB 0 0x0
+ * 0x000F[5] PLLB_INSELB 0 0x0
+ * 0x000F[7:6] CLKIN_DIV 0 0x0
+ * 0x0010[1:0] CLK0_IDRV 3 0x3
+ * 0x0010[3:2] CLK0_SRC 3 0x3
+ * 0x0010[4] CLK0_INV 0 0x0
+ * 0x0010[5] MS0_SRC 0 0x0
+ * 0x0010[6] MS0_INT 0 0x0
+ * 0x0010[7] CLK0_PDN 0 0x0
+ * 0x0011[1:0] CLK1_IDRV 3 0x3
+ * 0x0011[3:2] CLK1_SRC 3 0x3
+ * 0x0011[4] CLK1_INV 0 0x0
+ * 0x0011[5] MS1_SRC 0 0x0
+ * 0x0011[6] MS1_INT 0 0x0
+ * 0x0011[7] CLK1_PDN 0 0x0
+ * 0x0012[1:0] CLK2_IDRV 3 0x3
+ * 0x0012[3:2] CLK2_SRC 3 0x3
+ * 0x0012[4] CLK2_INV 0 0x0
+ * 0x0012[5] MS2_SRC 0 0x0
+ * 0x0012[6] MS2_INT 0 0x0
+ * 0x0012[7] CLK2_PDN 0 0x0
+ * 0x0013[1:0] CLK3_IDRV 0 0x0
+ * 0x0013[3:2] CLK3_SRC 3 0x3
+ * 0x0013[4] CLK3_INV 0 0x0
+ * 0x0013[5] MS3_SRC 0 0x0
+ * 0x0013[6] MS3_INT 0 0x0
+ * 0x0013[7] CLK3_PDN 1 0x1
+ * 0x0014[1:0] CLK4_IDRV 0 0x0
+ * 0x0014[3:2] CLK4_SRC 3 0x3
+ * 0x0014[4] CLK4_INV 0 0x0
+ * 0x0014[5] MS4_SRC 0 0x0
+ * 0x0014[6] MS4_INT 0 0x0
+ * 0x0014[7] CLK4_PDN 1 0x1
+ * 0x0015[1:0] CLK5_IDRV 0 0x0
+ * 0x0015[3:2] CLK5_SRC 3 0x3
+ * 0x0015[4] CLK5_INV 0 0x0
+ * 0x0015[5] MS5_SRC 0 0x0
+ * 0x0015[6] MS5_INT 0 0x0
+ * 0x0015[7] CLK5_PDN 1 0x1
+ * 0x0016[1:0] CLK6_IDRV 0 0x0
+ * 0x0016[3:2] CLK6_SRC 3 0x3
+ * 0x0016[4] CLK6_INV 0 0x0
+ * 0x0016[5] MS6_SRC 0 0x0
+ * 0x0016[6] FBA_INT 0 0x0
+ * 0x0016[7] CLK6_PDN 1 0x1
+ * 0x0017[1:0] CLK7_IDRV 0 0x0
+ * 0x0017[3:2] CLK7_SRC 3 0x3
+ * 0x0017[4] CLK7_INV 0 0x0
+ * 0x0017[5] MS7_SRC 0 0x0
+ * 0x0017[6] FBB_INT 0 0x0
+ * 0x0017[7] CLK7_PDN 1 0x1
+ * 0x001C[17:0] MSNA_P1 4096 0x01000
+ * 0x001F[19:0] MSNA_P2 0 0x00000
+ * 0x001F[23:4] MSNA_P3 1 0x00001
+ * 0x002C[17:0] MS0_P1 3328 0x00D00
+ * 0x002F[19:0] MS0_P2 0 0x00000
+ * 0x002F[23:4] MS0_P4 1 0x00001
+ * 0x0034[17:0] MS1_P1 179488 0x2BD20
+ * 0x0034[6:4] R1_DIV 6 0x6
+ * 0x0037[19:0] MS1_P2 0 0x00000
+ * 0x0037[23:4] MS1_P4 4 0x00004
+ * 0x003C[17:0] MS2_P1 179488 0x2BD20
+ * 0x003C[6:4] R2_DIV 6 0x6
+ * 0x003F[19:0] MS2_P2 0 0x00000
+ * 0x003F[23:4] MS2_P4 4 0x00004
+ * 0x005A[7:0] MS6_P2 0 0x00
+ * 0x005B[7:0] MS7_P2 0 0x00
+ * 0x0095[14:0] SSDN_P2 0 0x0000
+ * 0x0095[7] SSC_EN 0 0x0
+ * 0x0097[14:0] SSDN_P3 0 0x0000
+ * 0x0097[7] SSC_MODE 0 0x0
+ * 0x0099[11:0] SSDN_P1 0 0x000
+ * 0x009A[15:4] SSUDP 0 0x000
+ * 0x00A2[21:0] VCXO_PARAM 0 0x000000
+ * 0x00A5[7:0] CLK0_PHOFF 0 0x00
+ * 0x00A6[7:0] CLK1_PHOFF 0 0x00
+ * 0x00A7[7:0] CLK2_PHOFF 0 0x00
+ * 0x00B7[7:6] XTAL_CL 3 0x3
+ *
+ *
+ */
+
+#endif
\ No newline at end of file diff --git a/Core/Inc/main.h b/Core/Inc/main.h new file mode 100644 index 0000000..979acea --- /dev/null +++ b/Core/Inc/main.h @@ -0,0 +1,107 @@ +/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file : main.h
+ * @brief : Header for main.c file.
+ * This file contains the common defines of the application.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define FQ_UD_Pin GPIO_PIN_13
+#define FQ_UD_GPIO_Port GPIOC
+#define RESET_Pin GPIO_PIN_14
+#define RESET_GPIO_Port GPIOC
+#define W_CLK_Pin GPIO_PIN_15
+#define W_CLK_GPIO_Port GPIOC
+#define D7_Pin GPIO_PIN_8
+#define D7_GPIO_Port GPIOD
+#define D6_Pin GPIO_PIN_9
+#define D6_GPIO_Port GPIOD
+#define D5_Pin GPIO_PIN_10
+#define D5_GPIO_Port GPIOD
+#define D4_Pin GPIO_PIN_11
+#define D4_GPIO_Port GPIOD
+#define D3_Pin GPIO_PIN_12
+#define D3_GPIO_Port GPIOD
+#define D2_Pin GPIO_PIN_13
+#define D2_GPIO_Port GPIOD
+#define D1_Pin GPIO_PIN_14
+#define D1_GPIO_Port GPIOD
+#define D0_Pin GPIO_PIN_15
+#define D0_GPIO_Port GPIOD
+#define D13_Pin GPIO_PIN_11
+#define D13_GPIO_Port GPIOC
+#define D12_Pin GPIO_PIN_12
+#define D12_GPIO_Port GPIOC
+#define D11_Pin GPIO_PIN_0
+#define D11_GPIO_Port GPIOD
+#define D10_Pin GPIO_PIN_1
+#define D10_GPIO_Port GPIOD
+#define D14_Pin GPIO_PIN_2
+#define D14_GPIO_Port GPIOD
+#define D15_Pin GPIO_PIN_3
+#define D15_GPIO_Port GPIOD
+#define D16_Pin GPIO_PIN_4
+#define D16_GPIO_Port GPIOD
+#define D17_Pin GPIO_PIN_5
+#define D17_GPIO_Port GPIOD
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
diff --git a/Core/Inc/stm32h7xx_hal_conf.h b/Core/Inc/stm32h7xx_hal_conf.h new file mode 100644 index 0000000..8866b62 --- /dev/null +++ b/Core/Inc/stm32h7xx_hal_conf.h @@ -0,0 +1,515 @@ +/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file stm32h7xx_hal_conf.h
+ * @author MCD Application Team
+ * @brief HAL configuration file.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_CONF_H
+#define STM32H7xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
+
+ #define HAL_ADC_MODULE_ENABLED
+/* #define HAL_FDCAN_MODULE_ENABLED */
+/* #define HAL_FMAC_MODULE_ENABLED */
+/* #define HAL_CEC_MODULE_ENABLED */
+/* #define HAL_COMP_MODULE_ENABLED */
+/* #define HAL_CORDIC_MODULE_ENABLED */
+/* #define HAL_CRC_MODULE_ENABLED */
+/* #define HAL_CRYP_MODULE_ENABLED */
+#define HAL_DAC_MODULE_ENABLED
+/* #define HAL_DCMI_MODULE_ENABLED */
+/* #define HAL_DMA2D_MODULE_ENABLED */
+/* #define HAL_ETH_MODULE_ENABLED */
+/* #define HAL_ETH_LEGACY_MODULE_ENABLED */
+/* #define HAL_NAND_MODULE_ENABLED */
+/* #define HAL_NOR_MODULE_ENABLED */
+/* #define HAL_OTFDEC_MODULE_ENABLED */
+/* #define HAL_SRAM_MODULE_ENABLED */
+/* #define HAL_SDRAM_MODULE_ENABLED */
+/* #define HAL_HASH_MODULE_ENABLED */
+/* #define HAL_HRTIM_MODULE_ENABLED */
+/* #define HAL_HSEM_MODULE_ENABLED */
+/* #define HAL_GFXMMU_MODULE_ENABLED */
+/* #define HAL_JPEG_MODULE_ENABLED */
+/* #define HAL_OPAMP_MODULE_ENABLED */
+/* #define HAL_OSPI_MODULE_ENABLED */
+/* #define HAL_OSPI_MODULE_ENABLED */
+/* #define HAL_I2S_MODULE_ENABLED */
+/* #define HAL_SMBUS_MODULE_ENABLED */
+/* #define HAL_IWDG_MODULE_ENABLED */
+/* #define HAL_LPTIM_MODULE_ENABLED */
+/* #define HAL_LTDC_MODULE_ENABLED */
+/* #define HAL_QSPI_MODULE_ENABLED */
+/* #define HAL_RAMECC_MODULE_ENABLED */
+/* #define HAL_RNG_MODULE_ENABLED */
+/* #define HAL_RTC_MODULE_ENABLED */
+/* #define HAL_SAI_MODULE_ENABLED */
+/* #define HAL_SD_MODULE_ENABLED */
+/* #define HAL_MMC_MODULE_ENABLED */
+/* #define HAL_SPDIFRX_MODULE_ENABLED */
+/* #define HAL_SPI_MODULE_ENABLED */
+/* #define HAL_SWPMI_MODULE_ENABLED */
+/* #define HAL_TIM_MODULE_ENABLED */
+#define HAL_UART_MODULE_ENABLED
+/* #define HAL_USART_MODULE_ENABLED */
+/* #define HAL_IRDA_MODULE_ENABLED */
+/* #define HAL_SMARTCARD_MODULE_ENABLED */
+/* #define HAL_WWDG_MODULE_ENABLED */
+/* #define HAL_PCD_MODULE_ENABLED */
+/* #define HAL_HCD_MODULE_ENABLED */
+/* #define HAL_DFSDM_MODULE_ENABLED */
+/* #define HAL_DSI_MODULE_ENABLED */
+/* #define HAL_JPEG_MODULE_ENABLED */
+/* #define HAL_MDIOS_MODULE_ENABLED */
+/* #define HAL_PSSI_MODULE_ENABLED */
+/* #define HAL_DTS_MODULE_ENABLED */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_MDMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_HSEM_MODULE_ENABLED
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+#define HSE_VALUE (25000000UL) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal oscillator (CSI) default value.
+ * This value is the default CSI value after Reset.
+ */
+#if !defined (CSI_VALUE)
+ #define CSI_VALUE (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE (64000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ * This value is used by the UART, RTC HAL module to compute the system frequency
+ */
+#if !defined (LSE_VALUE)
+ #define LSE_VALUE (32768UL) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined (LSE_STARTUP_TIMEOUT)
+ #define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature.*/
+
+/**
+ * @brief External clock source for I2S peripheral
+ * This value is used by the I2S HAL module to compute the I2S clock source
+ * frequency, this source is inserted directly through I2S_CKIN pad.
+ */
+#if !defined (EXTERNAL_CLOCK_VALUE)
+ #define EXTERNAL_CLOCK_VALUE 12288000UL /*!< Value of the External clock in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority */
+#define USE_RTOS 0
+#define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */
+#define USE_SPI_CRC 0U /*!< use CRC in SPI */
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
+#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
+#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */
+#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U /* CORDIC register callback disabled */
+#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
+#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
+#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
+#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */
+#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */
+#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */
+#define USE_HAL_DTS_REGISTER_CALLBACKS 0U /* DTS register callback disabled */
+#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */
+#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */
+#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U /* FMAC register callback disabled */
+#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
+#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
+#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */
+#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
+#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */
+#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
+#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U /* GFXMMU register callback disabled */
+#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U /* HRTIM register callback disabled */
+#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
+#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
+#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
+#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */
+#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */
+#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */
+#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */
+#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */
+#define USE_HAL_OSPI_REGISTER_CALLBACKS 0U /* OSPI register callback disabled */
+#define USE_HAL_OTFDEC_REGISTER_CALLBACKS 0U /* OTFDEC register callback disabled */
+#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
+#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */
+#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */
+#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
+#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */
+#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
+#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
+#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
+#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U /* SWPMI register callback disabled */
+#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
+#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
+#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
+#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
+
+/* ########################### Ethernet Configuration ######################### */
+#define ETH_TX_DESC_CNT 4U /* number of Ethernet Tx DMA descriptors */
+#define ETH_RX_DESC_CNT 4U /* number of Ethernet Rx DMA descriptors */
+
+#define ETH_MAC_ADDR0 (0x02UL)
+#define ETH_MAC_ADDR1 (0x00UL)
+#define ETH_MAC_ADDR2 (0x00UL)
+#define ETH_MAC_ADDR3 (0x00UL)
+#define ETH_MAC_ADDR4 (0x00UL)
+#define ETH_MAC_ADDR5 (0x00UL)
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/* #define USE_FULL_ASSERT 1U */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32h7xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32h7xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+ #include "stm32h7xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_MDMA_MODULE_ENABLED
+ #include "stm32h7xx_hal_mdma.h"
+#endif /* HAL_MDMA_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32h7xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+ #include "stm32h7xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+ #include "stm32h7xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DSI_MODULE_ENABLED
+ #include "stm32h7xx_hal_dsi.h"
+#endif /* HAL_DSI_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+ #include "stm32h7xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_DTS_MODULE_ENABLED
+ #include "stm32h7xx_hal_dts.h"
+#endif /* HAL_DTS_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+ #include "stm32h7xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_ETH_LEGACY_MODULE_ENABLED
+ #include "stm32h7xx_hal_eth_legacy.h"
+#endif /* HAL_ETH_LEGACY_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+ #include "stm32h7xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32h7xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32h7xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+ #include "stm32h7xx_hal_fdcan.h"
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+ #include "stm32h7xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+ #include "stm32h7xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORDIC_MODULE_ENABLED
+ #include "stm32h7xx_hal_cordic.h"
+#endif /* HAL_CORDIC_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32h7xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+ #include "stm32h7xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+ #include "stm32h7xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32h7xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GFXMMU_MODULE_ENABLED
+ #include "stm32h7xx_hal_gfxmmu.h"
+#endif /* HAL_GFXMMU_MODULE_ENABLED */
+
+#ifdef HAL_FMAC_MODULE_ENABLED
+ #include "stm32h7xx_hal_fmac.h"
+#endif /* HAL_FMAC_MODULE_ENABLED */
+
+#ifdef HAL_HRTIM_MODULE_ENABLED
+ #include "stm32h7xx_hal_hrtim.h"
+#endif /* HAL_HRTIM_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+ #include "stm32h7xx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+ #include "stm32h7xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+ #include "stm32h7xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+ #include "stm32h7xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32h7xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32h7xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32h7xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_JPEG_MODULE_ENABLED
+ #include "stm32h7xx_hal_jpeg.h"
+#endif /* HAL_JPEG_MODULE_ENABLED */
+
+#ifdef HAL_MDIOS_MODULE_ENABLED
+ #include "stm32h7xx_hal_mdios.h"
+#endif /* HAL_MDIOS_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32h7xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32h7xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+#include "stm32h7xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+#include "stm32h7xx_hal_opamp.h"
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+ #include "stm32h7xx_hal_ospi.h"
+#endif /* HAL_OSPI_MODULE_ENABLED */
+
+#ifdef HAL_OTFDEC_MODULE_ENABLED
+#include "stm32h7xx_hal_otfdec.h"
+#endif /* HAL_OTFDEC_MODULE_ENABLED */
+
+#ifdef HAL_PSSI_MODULE_ENABLED
+ #include "stm32h7xx_hal_pssi.h"
+#endif /* HAL_PSSI_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32h7xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32h7xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RAMECC_MODULE_ENABLED
+ #include "stm32h7xx_hal_ramecc.h"
+#endif /* HAL_RAMECC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32h7xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32h7xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32h7xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32h7xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+ #include "stm32h7xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32h7xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+ #include "stm32h7xx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_SWPMI_MODULE_ENABLED
+ #include "stm32h7xx_hal_swpmi.h"
+#endif /* HAL_SWPMI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32h7xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32h7xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32h7xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32h7xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32h7xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32h7xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32h7xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32h7xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32h7xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(uint8_t *file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_CONF_H */
diff --git a/Core/Inc/stm32h7xx_it.h b/Core/Inc/stm32h7xx_it.h new file mode 100644 index 0000000..35e20ef --- /dev/null +++ b/Core/Inc/stm32h7xx_it.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file stm32h7xx_it.h
+ * @brief This file contains the headers of the interrupt handlers.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32H7xx_IT_H
+#define __STM32H7xx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void DMA1_Stream0_IRQHandler(void);
+void DMA1_Stream1_IRQHandler(void);
+void DMA1_Stream2_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H7xx_IT_H */
diff --git a/Core/Src/AD9851.c b/Core/Src/AD9851.c new file mode 100644 index 0000000..4c4652a --- /dev/null +++ b/Core/Src/AD9851.c @@ -0,0 +1,59 @@ +#include "AD9851.h"
+
+void AD9851_reset(void) {
+ HAL_GPIO_WritePin(RESET_GPIO_Port, RESET_Pin, GPIO_PIN_RESET);
+ HAL_GPIO_WritePin(W_CLK_GPIO_Port, W_CLK_Pin, GPIO_PIN_RESET);
+ HAL_GPIO_WritePin(FQ_UD_GPIO_Port, FQ_UD_Pin, GPIO_PIN_RESET);
+ HAL_Delay(50);
+ HAL_GPIO_WritePin(RESET_GPIO_Port, RESET_Pin, GPIO_PIN_SET);
+ HAL_Delay(50);
+ HAL_GPIO_WritePin(RESET_GPIO_Port, RESET_Pin, GPIO_PIN_RESET);
+ HAL_Delay(50);
+}
+
+void AD9851_parallel(uint32_t freq) {
+
+ uint32_t tword = (freq/100) * 2386;
+ uint8_t W[5];
+
+ W[4] = tword;
+ W[3] = tword >> 8;
+ W[2] = tword >> 16;
+ W[1] = tword >> 24;
+
+ W[0] = 0x01; //phase and 6xREFCLK mult enable
+
+ HAL_GPIO_WritePin(FQ_UD_GPIO_Port, FQ_UD_Pin, GPIO_PIN_RESET);
+ for (int i=0;i<5;i++) {
+ HAL_GPIO_WritePin(D0_GPIO_Port, D0_Pin, W[i] & 0x01);
+ HAL_GPIO_WritePin(D1_GPIO_Port, D1_Pin, (W[i] >> 1) & 0x01);
+ HAL_GPIO_WritePin(D2_GPIO_Port, D2_Pin, (W[i] >> 2) & 0x01);
+ HAL_GPIO_WritePin(D3_GPIO_Port, D3_Pin, (W[i] >> 3) & 0x01);
+ HAL_GPIO_WritePin(D4_GPIO_Port, D4_Pin, (W[i] >> 4) & 0x01);
+ HAL_GPIO_WritePin(D5_GPIO_Port, D5_Pin, (W[i] >> 5) & 0x01);
+ if (i==0) {
+ HAL_GPIO_WritePin(D6_GPIO_Port, D6_Pin, 1);
+ } else {
+ HAL_GPIO_WritePin(D6_GPIO_Port, D6_Pin, (W[i] >> 6) & 0x01);
+ }
+ HAL_GPIO_WritePin(D7_GPIO_Port, D7_Pin, (W[i] >> 7) & 0x01);
+
+ HAL_GPIO_WritePin(D10_GPIO_Port, D10_Pin, W[i] & 0x01);
+ HAL_GPIO_WritePin(D11_GPIO_Port, D11_Pin, (W[i] >> 1) & 0x01);
+ HAL_GPIO_WritePin(D12_GPIO_Port, D12_Pin, (W[i] >> 2) & 0x01);
+ HAL_GPIO_WritePin(D13_GPIO_Port, D13_Pin, (W[i] >> 3) & 0x01);
+ HAL_GPIO_WritePin(D14_GPIO_Port, D14_Pin, (W[i] >> 4) & 0x01);
+ HAL_GPIO_WritePin(D15_GPIO_Port, D15_Pin, (W[i] >> 5) & 0x01);
+ HAL_GPIO_WritePin(D16_GPIO_Port, D16_Pin, (W[i] >> 6) & 0x01);
+ HAL_GPIO_WritePin(D17_GPIO_Port, D17_Pin, (W[i] >> 7) & 0x01);
+
+ HAL_GPIO_WritePin(W_CLK_GPIO_Port, W_CLK_Pin, GPIO_PIN_SET);
+ HAL_Delay(50);
+ HAL_GPIO_WritePin(W_CLK_GPIO_Port, W_CLK_Pin, GPIO_PIN_RESET);
+ }
+
+ HAL_GPIO_WritePin(FQ_UD_GPIO_Port, FQ_UD_Pin, GPIO_PIN_SET);
+ HAL_Delay(50);
+ //below may be unnecessary
+ HAL_GPIO_WritePin(FQ_UD_GPIO_Port, FQ_UD_Pin, GPIO_PIN_RESET);
+}
\ No newline at end of file diff --git a/Core/Src/main.c b/Core/Src/main.c new file mode 100644 index 0000000..bc7e67c --- /dev/null +++ b/Core/Src/main.c @@ -0,0 +1,707 @@ +/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file : main.c
+ * @brief : Main program body
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include "AD9851.h"
+#include "Si5351A-RevB-Registers.h"
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+#define NS 1000
+#define FULL_BUF_SIZE 256
+#define HALF_BUF_SIZE FULL_BUF_SIZE / 2
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+ADC_HandleTypeDef hadc1;
+ADC_HandleTypeDef hadc2;
+DMA_HandleTypeDef hdma_adc1;
+DMA_HandleTypeDef hdma_adc2;
+
+DAC_HandleTypeDef hdac1;
+DMA_HandleTypeDef hdma_dac1_ch2;
+
+I2C_HandleTypeDef hi2c1;
+
+UART_HandleTypeDef huart1;
+
+/* USER CODE BEGIN PV */
+volatile uint32_t adc_val[FULL_BUF_SIZE];
+volatile uint32_t dac_val[FULL_BUF_SIZE];
+
+uint32_t* in_buf_ptr;
+uint32_t* out_buf_ptr;
+uint32_t out_out_ptr = 0;
+
+int flag = 0;
+
+/* FIR filter designed with
+http://t-filter.appspot.com
+
+sampling frequency: 200000 Hz
+
+* 0 Hz - 16000 Hz
+ gain = 1
+ desired ripple = 5 dB
+ actual ripple = 0 dB
+
+*/
+
+#define FILTER_TAP_NUM 5
+
+static double filter_taps[FILTER_TAP_NUM] = {
+ -4.4408920985006264e-17,
+ 4.4408920985006264e-17,
+ 1,
+ 4.4408920985006264e-17,
+ -4.4408920985006264e-17
+};
+
+float afilter_taps[FILTER_TAP_NUM];
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+void PeriphCommonClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_DMA_Init(void);
+static void MX_ADC2_Init(void);
+static void MX_DAC1_Init(void);
+static void MX_I2C1_Init(void);
+static void MX_ADC1_Init(void);
+static void MX_USART1_UART_Init(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+uint32_t fir(uint32_t in);
+
+void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) {
+ //first half of adc buffer is full
+ in_buf_ptr = &adc_val[0];
+ out_buf_ptr = &dac_val[HALF_BUF_SIZE];// + HALF_BUF_SIZE;
+
+ for (int i=0;i<HALF_BUF_SIZE;i++) {
+ uint32_t test = fir(in_buf_ptr[i]);
+ out_buf_ptr[i] = test;
+ }
+
+ flag=1;
+}
+
+void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) {
+ //second half of adc buffer is full
+ in_buf_ptr = &adc_val[HALF_BUF_SIZE];// + HALF_BUF_SIZE;
+ out_buf_ptr = &dac_val[0];
+
+ for (int i=0;i<HALF_BUF_SIZE;i++) {
+ uint32_t test = fir(in_buf_ptr[i]);
+ out_buf_ptr[i] = test;
+ }
+
+ flag=1;
+}
+
+float ema_alpha = 0.1f;
+float ema_out = 0;
+void ema_lpf(float in) {
+ ema_out = ema_alpha * in + (1.0f - ema_alpha) * ema_out;
+}
+
+float firdata[FILTER_TAP_NUM];
+int firptr[FILTER_TAP_NUM];
+int fir_w_ptr = 0;
+
+uint32_t fir(uint32_t in) {
+ float in_f = (float)((int)in-2048);
+ float fir_out = 0;
+ for (int i=0;i<FILTER_TAP_NUM;i++) {
+ fir_out += afilter_taps[firptr[i]] * firdata[i];
+ firptr[i]++;
+ }
+ firdata[fir_w_ptr] = in_f;
+ firptr[fir_w_ptr] = 0;
+ fir_w_ptr++;
+ if (fir_w_ptr == FILTER_TAP_NUM) fir_w_ptr = 0;
+
+ return (uint32_t) (fir_out+2048);
+}
+
+void process_data() {
+ for (int i=0;i<1;i++) {
+ float in = ((float) in_buf_ptr[i]);
+ ema_lpf(in);
+ out_buf_ptr[i] = (uint32_t)(ema_out);
+ }
+}
+
+/* USER CODE END 0 */
+
+/**
+ * @brief The application entry point.
+ * @retval int
+ */
+int main(void)
+{
+ /* USER CODE BEGIN 1 */
+
+ /* USER CODE END 1 */
+
+ /* MCU Configuration--------------------------------------------------------*/
+
+ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+ HAL_Init();
+
+ /* USER CODE BEGIN Init */
+
+ /* USER CODE END Init */
+
+ /* Configure the system clock */
+ SystemClock_Config();
+
+/* Configure the peripherals common clocks */
+ PeriphCommonClock_Config();
+
+ /* USER CODE BEGIN SysInit */
+
+ /* USER CODE END SysInit */
+
+ /* Initialize all configured peripherals */
+ MX_GPIO_Init();
+ MX_DMA_Init();
+ MX_ADC2_Init();
+ MX_DAC1_Init();
+ MX_I2C1_Init();
+ MX_ADC1_Init();
+ MX_USART1_UART_Init();
+ /* USER CODE BEGIN 2 */
+ HAL_ADC_Start_DMA(&hadc1, (uint32_t*) adc_val, FULL_BUF_SIZE);
+ HAL_DAC_Start_DMA(&hdac1, DAC_CHANNEL_1, (uint32_t*) dac_val, FULL_BUF_SIZE, DAC_ALIGN_12B_R);
+
+ float maxfir = 0;
+
+ for (int i=0;i<FILTER_TAP_NUM;i++) {
+ if (filter_taps[i] < 0) maxfir -= filter_taps[i];
+ else maxfir += filter_taps[i];
+ }
+
+ for (int i=0;i<FILTER_TAP_NUM;i++) {
+ afilter_taps[i] = filter_taps[i] / maxfir;
+ }
+
+ uint8_t i2c_buf[2];
+ for (int i=0;i<SI5351A_REVB_REG_CONFIG_NUM_REGS;i++) {
+ i2c_buf[0] = si5351a_revb_registers[i].address;
+ i2c_buf[1] = si5351a_revb_registers[i].value;
+ HAL_I2C_Master_Transmit(&hi2c1, 0x60 << 1, i2c_buf, 2, 1000);
+ HAL_Delay(50);
+ }
+ AD9851_reset();
+
+ HAL_Delay(50);
+ AD9851_parallel(32881);
+
+
+
+ /* USER CODE END 2 */
+
+ /* Infinite loop */
+ /* USER CODE BEGIN WHILE */
+ while (1)
+ {
+ /* USER CODE END WHILE */
+
+ /* USER CODE BEGIN 3 */
+ }
+ /* USER CODE END 3 */
+}
+
+/**
+ * @brief System Clock Configuration
+ * @retval None
+ */
+void SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+ /** Supply configuration update enable
+ */
+ HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
+
+ /** Macro to configure the PLL clock source
+ */
+ __HAL_RCC_PLL_PLLSOURCE_CONFIG(RCC_PLLSOURCE_HSI);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_DIV1;
+ RCC_OscInitStruct.HSICalibrationValue = 64;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
+ |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+ RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV4;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV4;
+ RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
+ {
+ Error_Handler();
+ }
+}
+
+/**
+ * @brief Peripherals Common Clock Configuration
+ * @retval None
+ */
+void PeriphCommonClock_Config(void)
+{
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+ /** Initializes the peripherals clock
+ */
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC;
+ PeriphClkInitStruct.PLL2.PLL2M = 4;
+ PeriphClkInitStruct.PLL2.PLL2N = 12;
+ PeriphClkInitStruct.PLL2.PLL2P = 4;
+ PeriphClkInitStruct.PLL2.PLL2Q = 2;
+ PeriphClkInitStruct.PLL2.PLL2R = 2;
+ PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3;
+ PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE;
+ PeriphClkInitStruct.PLL2.PLL2FRACN = 0;
+ PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+ {
+ Error_Handler();
+ }
+}
+
+/**
+ * @brief ADC1 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_ADC1_Init(void)
+{
+
+ /* USER CODE BEGIN ADC1_Init 0 */
+
+ /* USER CODE END ADC1_Init 0 */
+
+ ADC_MultiModeTypeDef multimode = {0};
+ ADC_ChannelConfTypeDef sConfig = {0};
+
+ /* USER CODE BEGIN ADC1_Init 1 */
+
+ /* USER CODE END ADC1_Init 1 */
+
+ /** Common config
+ */
+ hadc1.Instance = ADC1;
+ hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV4;
+ hadc1.Init.Resolution = ADC_RESOLUTION_16B;
+ hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
+ hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
+ hadc1.Init.LowPowerAutoWait = DISABLE;
+ hadc1.Init.ContinuousConvMode = DISABLE;
+ hadc1.Init.NbrOfConversion = 1;
+ hadc1.Init.DiscontinuousConvMode = DISABLE;
+ hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+ hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+ hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR;
+ hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;
+ hadc1.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE;
+ hadc1.Init.OversamplingMode = DISABLE;
+ if (HAL_ADC_Init(&hadc1) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /** Configure the ADC multi-mode
+ */
+ multimode.Mode = ADC_MODE_INDEPENDENT;
+ if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /** Configure Regular Channel
+ */
+ sConfig.Channel = ADC_CHANNEL_3;
+ sConfig.Rank = ADC_REGULAR_RANK_1;
+ sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
+ sConfig.SingleDiff = ADC_SINGLE_ENDED;
+ sConfig.OffsetNumber = ADC_OFFSET_NONE;
+ sConfig.Offset = 0;
+ sConfig.OffsetSignedSaturation = DISABLE;
+ if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /* USER CODE BEGIN ADC1_Init 2 */
+
+ /* USER CODE END ADC1_Init 2 */
+
+}
+
+/**
+ * @brief ADC2 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_ADC2_Init(void)
+{
+
+ /* USER CODE BEGIN ADC2_Init 0 */
+
+ /* USER CODE END ADC2_Init 0 */
+
+ ADC_ChannelConfTypeDef sConfig = {0};
+
+ /* USER CODE BEGIN ADC2_Init 1 */
+
+ /* USER CODE END ADC2_Init 1 */
+
+ /** Common config
+ */
+ hadc2.Instance = ADC2;
+ hadc2.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV4;
+ hadc2.Init.Resolution = ADC_RESOLUTION_16B;
+ hadc2.Init.ScanConvMode = ADC_SCAN_DISABLE;
+ hadc2.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
+ hadc2.Init.LowPowerAutoWait = DISABLE;
+ hadc2.Init.ContinuousConvMode = DISABLE;
+ hadc2.Init.NbrOfConversion = 1;
+ hadc2.Init.DiscontinuousConvMode = DISABLE;
+ hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+ hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+ hadc2.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR;
+ hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED;
+ hadc2.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE;
+ hadc2.Init.OversamplingMode = DISABLE;
+ if (HAL_ADC_Init(&hadc2) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /** Configure Regular Channel
+ */
+ sConfig.Channel = ADC_CHANNEL_4;
+ sConfig.Rank = ADC_REGULAR_RANK_1;
+ sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
+ sConfig.SingleDiff = ADC_SINGLE_ENDED;
+ sConfig.OffsetNumber = ADC_OFFSET_NONE;
+ sConfig.Offset = 0;
+ sConfig.OffsetSignedSaturation = DISABLE;
+ if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /* USER CODE BEGIN ADC2_Init 2 */
+
+ /* USER CODE END ADC2_Init 2 */
+
+}
+
+/**
+ * @brief DAC1 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_DAC1_Init(void)
+{
+
+ /* USER CODE BEGIN DAC1_Init 0 */
+
+ /* USER CODE END DAC1_Init 0 */
+
+ DAC_ChannelConfTypeDef sConfig = {0};
+
+ /* USER CODE BEGIN DAC1_Init 1 */
+
+ /* USER CODE END DAC1_Init 1 */
+
+ /** DAC Initialization
+ */
+ hdac1.Instance = DAC1;
+ if (HAL_DAC_Init(&hdac1) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /** DAC channel OUT2 config
+ */
+ sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE;
+ sConfig.DAC_Trigger = DAC_TRIGGER_NONE;
+ sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
+ sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_DISABLE;
+ sConfig.DAC_UserTrimming = DAC_TRIMMING_FACTORY;
+ if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_2) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /* USER CODE BEGIN DAC1_Init 2 */
+
+ /* USER CODE END DAC1_Init 2 */
+
+}
+
+/**
+ * @brief I2C1 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_I2C1_Init(void)
+{
+
+ /* USER CODE BEGIN I2C1_Init 0 */
+
+ /* USER CODE END I2C1_Init 0 */
+
+ /* USER CODE BEGIN I2C1_Init 1 */
+
+ /* USER CODE END I2C1_Init 1 */
+ hi2c1.Instance = I2C1;
+ hi2c1.Init.Timing = 0x00303D5B;
+ hi2c1.Init.OwnAddress1 = 0;
+ hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
+ hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
+ hi2c1.Init.OwnAddress2 = 0;
+ hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
+ hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
+ hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
+ if (HAL_I2C_Init(&hi2c1) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /** Configure Analogue filter
+ */
+ if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /** Configure Digital filter
+ */
+ if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /* USER CODE BEGIN I2C1_Init 2 */
+
+ /* USER CODE END I2C1_Init 2 */
+
+}
+
+/**
+ * @brief USART1 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_USART1_UART_Init(void)
+{
+
+ /* USER CODE BEGIN USART1_Init 0 */
+
+ /* USER CODE END USART1_Init 0 */
+
+ /* USER CODE BEGIN USART1_Init 1 */
+
+ /* USER CODE END USART1_Init 1 */
+ huart1.Instance = USART1;
+ huart1.Init.BaudRate = 115200;
+ huart1.Init.WordLength = UART_WORDLENGTH_8B;
+ huart1.Init.StopBits = UART_STOPBITS_1;
+ huart1.Init.Parity = UART_PARITY_NONE;
+ huart1.Init.Mode = UART_MODE_TX_RX;
+ huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+ huart1.Init.OverSampling = UART_OVERSAMPLING_16;
+ huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+ huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+ huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+ if (HAL_UART_Init(&huart1) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ /* USER CODE BEGIN USART1_Init 2 */
+
+ /* USER CODE END USART1_Init 2 */
+
+}
+
+/**
+ * Enable DMA controller clock
+ */
+static void MX_DMA_Init(void)
+{
+
+ /* DMA controller clock enable */
+ __HAL_RCC_DMA1_CLK_ENABLE();
+
+ /* DMA interrupt init */
+ /* DMA1_Stream0_IRQn interrupt configuration */
+ HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 0, 0);
+ HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn);
+ /* DMA1_Stream1_IRQn interrupt configuration */
+ HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 0, 0);
+ HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn);
+ /* DMA1_Stream2_IRQn interrupt configuration */
+ HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 0, 0);
+ HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn);
+
+}
+
+/**
+ * @brief GPIO Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_GPIO_Init(void)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+/* USER CODE BEGIN MX_GPIO_Init_1 */
+/* USER CODE END MX_GPIO_Init_1 */
+
+ /* GPIO Ports Clock Enable */
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ __HAL_RCC_GPIOD_CLK_ENABLE();
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+
+ /*Configure GPIO pin Output Level */
+ HAL_GPIO_WritePin(GPIOC, FQ_UD_Pin|RESET_Pin|W_CLK_Pin|D13_Pin
+ |D12_Pin, GPIO_PIN_RESET);
+
+ /*Configure GPIO pin Output Level */
+ HAL_GPIO_WritePin(GPIOD, D7_Pin|D6_Pin|D5_Pin|D4_Pin
+ |D3_Pin|D2_Pin|D1_Pin|D0_Pin
+ |D11_Pin|D10_Pin|D14_Pin|D15_Pin
+ |D16_Pin|D17_Pin, GPIO_PIN_RESET);
+
+ /*Configure GPIO pins : FQ_UD_Pin RESET_Pin W_CLK_Pin D13_Pin
+ D12_Pin */
+ GPIO_InitStruct.Pin = FQ_UD_Pin|RESET_Pin|W_CLK_Pin|D13_Pin
+ |D12_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+ /*Configure GPIO pins : D7_Pin D6_Pin D5_Pin D4_Pin
+ D3_Pin D2_Pin D1_Pin D0_Pin
+ D11_Pin D10_Pin D14_Pin D15_Pin
+ D16_Pin D17_Pin */
+ GPIO_InitStruct.Pin = D7_Pin|D6_Pin|D5_Pin|D4_Pin
+ |D3_Pin|D2_Pin|D1_Pin|D0_Pin
+ |D11_Pin|D10_Pin|D14_Pin|D15_Pin
+ |D16_Pin|D17_Pin;
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+/* USER CODE BEGIN MX_GPIO_Init_2 */
+/* USER CODE END MX_GPIO_Init_2 */
+}
+
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+/**
+ * @brief This function is executed in case of error occurrence.
+ * @retval None
+ */
+void Error_Handler(void)
+{
+ /* USER CODE BEGIN Error_Handler_Debug */
+ /* User can add his own implementation to report the HAL error return state */
+ __disable_irq();
+ while (1)
+ {
+ }
+ /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief Reports the name of the source file and the source line number
+ * where the assert_param error has occurred.
+ * @param file: pointer to the source file name
+ * @param line: assert_param error line source number
+ * @retval None
+ */
+void assert_failed(uint8_t *file, uint32_t line)
+{
+ /* USER CODE BEGIN 6 */
+ /* User can add his own implementation to report the file name and line number,
+ ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+ /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
diff --git a/Core/Src/stm32h7xx_hal_msp.c b/Core/Src/stm32h7xx_hal_msp.c new file mode 100644 index 0000000..963b103 --- /dev/null +++ b/Core/Src/stm32h7xx_hal_msp.c @@ -0,0 +1,476 @@ +/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file stm32h7xx_hal_msp.c
+ * @brief This file provides code for the MSP Initialization
+ * and de-Initialization codes.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+extern DMA_HandleTypeDef hdma_adc1;
+
+extern DMA_HandleTypeDef hdma_adc2;
+
+extern DMA_HandleTypeDef hdma_dac1_ch2;
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+ * Initializes the Global MSP.
+ */
+void HAL_MspInit(void)
+{
+ /* USER CODE BEGIN MspInit 0 */
+
+ /* USER CODE END MspInit 0 */
+
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+ /* System interrupt init*/
+
+ /* USER CODE BEGIN MspInit 1 */
+
+ /* USER CODE END MspInit 1 */
+}
+
+static uint32_t HAL_RCC_ADC12_CLK_ENABLED=0;
+
+/**
+* @brief ADC MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hadc: ADC handle pointer
+* @retval None
+*/
+void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+ if(hadc->Instance==ADC1)
+ {
+ /* USER CODE BEGIN ADC1_MspInit 0 */
+
+ /* USER CODE END ADC1_MspInit 0 */
+ /* Peripheral clock enable */
+ HAL_RCC_ADC12_CLK_ENABLED++;
+ if(HAL_RCC_ADC12_CLK_ENABLED==1){
+ __HAL_RCC_ADC12_CLK_ENABLE();
+ }
+
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ /**ADC1 GPIO Configuration
+ PA6 ------> ADC1_INP3
+ */
+ GPIO_InitStruct.Pin = GPIO_PIN_6;
+ GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+ /* ADC1 DMA Init */
+ /* ADC1 Init */
+ hdma_adc1.Instance = DMA1_Stream0;
+ hdma_adc1.Init.Request = DMA_REQUEST_ADC1;
+ hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;
+ hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;
+ hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;
+ hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
+ hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
+ hdma_adc1.Init.Mode = DMA_NORMAL;
+ hdma_adc1.Init.Priority = DMA_PRIORITY_HIGH;
+ hdma_adc1.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+ if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1);
+
+ /* USER CODE BEGIN ADC1_MspInit 1 */
+
+ /* USER CODE END ADC1_MspInit 1 */
+ }
+ else if(hadc->Instance==ADC2)
+ {
+ /* USER CODE BEGIN ADC2_MspInit 0 */
+
+ /* USER CODE END ADC2_MspInit 0 */
+ /* Peripheral clock enable */
+ HAL_RCC_ADC12_CLK_ENABLED++;
+ if(HAL_RCC_ADC12_CLK_ENABLED==1){
+ __HAL_RCC_ADC12_CLK_ENABLE();
+ }
+
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ /**ADC2 GPIO Configuration
+ PC4 ------> ADC2_INP4
+ */
+ GPIO_InitStruct.Pin = GPIO_PIN_4;
+ GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+ /* ADC2 DMA Init */
+ /* ADC2 Init */
+ hdma_adc2.Instance = DMA1_Stream1;
+ hdma_adc2.Init.Request = DMA_REQUEST_ADC2;
+ hdma_adc2.Init.Direction = DMA_PERIPH_TO_MEMORY;
+ hdma_adc2.Init.PeriphInc = DMA_PINC_DISABLE;
+ hdma_adc2.Init.MemInc = DMA_MINC_ENABLE;
+ hdma_adc2.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
+ hdma_adc2.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
+ hdma_adc2.Init.Mode = DMA_CIRCULAR;
+ hdma_adc2.Init.Priority = DMA_PRIORITY_HIGH;
+ hdma_adc2.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+ if (HAL_DMA_Init(&hdma_adc2) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc2);
+
+ /* USER CODE BEGIN ADC2_MspInit 1 */
+
+ /* USER CODE END ADC2_MspInit 1 */
+ }
+
+}
+
+/**
+* @brief ADC MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hadc: ADC handle pointer
+* @retval None
+*/
+void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
+{
+ if(hadc->Instance==ADC1)
+ {
+ /* USER CODE BEGIN ADC1_MspDeInit 0 */
+
+ /* USER CODE END ADC1_MspDeInit 0 */
+ /* Peripheral clock disable */
+ HAL_RCC_ADC12_CLK_ENABLED--;
+ if(HAL_RCC_ADC12_CLK_ENABLED==0){
+ __HAL_RCC_ADC12_CLK_DISABLE();
+ }
+
+ /**ADC1 GPIO Configuration
+ PA6 ------> ADC1_INP3
+ */
+ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_6);
+
+ /* ADC1 DMA DeInit */
+ HAL_DMA_DeInit(hadc->DMA_Handle);
+ /* USER CODE BEGIN ADC1_MspDeInit 1 */
+
+ /* USER CODE END ADC1_MspDeInit 1 */
+ }
+ else if(hadc->Instance==ADC2)
+ {
+ /* USER CODE BEGIN ADC2_MspDeInit 0 */
+
+ /* USER CODE END ADC2_MspDeInit 0 */
+ /* Peripheral clock disable */
+ HAL_RCC_ADC12_CLK_ENABLED--;
+ if(HAL_RCC_ADC12_CLK_ENABLED==0){
+ __HAL_RCC_ADC12_CLK_DISABLE();
+ }
+
+ /**ADC2 GPIO Configuration
+ PC4 ------> ADC2_INP4
+ */
+ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_4);
+
+ /* ADC2 DMA DeInit */
+ HAL_DMA_DeInit(hadc->DMA_Handle);
+ /* USER CODE BEGIN ADC2_MspDeInit 1 */
+
+ /* USER CODE END ADC2_MspDeInit 1 */
+ }
+
+}
+
+/**
+* @brief DAC MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hdac: DAC handle pointer
+* @retval None
+*/
+void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+ if(hdac->Instance==DAC1)
+ {
+ /* USER CODE BEGIN DAC1_MspInit 0 */
+
+ /* USER CODE END DAC1_MspInit 0 */
+ /* Peripheral clock enable */
+ __HAL_RCC_DAC12_CLK_ENABLE();
+
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ /**DAC1 GPIO Configuration
+ PA5 ------> DAC1_OUT2
+ */
+ GPIO_InitStruct.Pin = GPIO_PIN_5;
+ GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+ /* DAC1 DMA Init */
+ /* DAC1_CH2 Init */
+ hdma_dac1_ch2.Instance = DMA1_Stream2;
+ hdma_dac1_ch2.Init.Request = DMA_REQUEST_DAC2;
+ hdma_dac1_ch2.Init.Direction = DMA_MEMORY_TO_PERIPH;
+ hdma_dac1_ch2.Init.PeriphInc = DMA_PINC_DISABLE;
+ hdma_dac1_ch2.Init.MemInc = DMA_MINC_ENABLE;
+ hdma_dac1_ch2.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
+ hdma_dac1_ch2.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
+ hdma_dac1_ch2.Init.Mode = DMA_CIRCULAR;
+ hdma_dac1_ch2.Init.Priority = DMA_PRIORITY_HIGH;
+ hdma_dac1_ch2.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+ if (HAL_DMA_Init(&hdma_dac1_ch2) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ __HAL_LINKDMA(hdac,DMA_Handle2,hdma_dac1_ch2);
+
+ /* USER CODE BEGIN DAC1_MspInit 1 */
+
+ /* USER CODE END DAC1_MspInit 1 */
+ }
+
+}
+
+/**
+* @brief DAC MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hdac: DAC handle pointer
+* @retval None
+*/
+void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
+{
+ if(hdac->Instance==DAC1)
+ {
+ /* USER CODE BEGIN DAC1_MspDeInit 0 */
+
+ /* USER CODE END DAC1_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_DAC12_CLK_DISABLE();
+
+ /**DAC1 GPIO Configuration
+ PA5 ------> DAC1_OUT2
+ */
+ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5);
+
+ /* DAC1 DMA DeInit */
+ HAL_DMA_DeInit(hdac->DMA_Handle2);
+ /* USER CODE BEGIN DAC1_MspDeInit 1 */
+
+ /* USER CODE END DAC1_MspDeInit 1 */
+ }
+
+}
+
+/**
+* @brief I2C MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hi2c: I2C handle pointer
+* @retval None
+*/
+void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+ if(hi2c->Instance==I2C1)
+ {
+ /* USER CODE BEGIN I2C1_MspInit 0 */
+
+ /* USER CODE END I2C1_MspInit 0 */
+
+ /** Initializes the peripherals clock
+ */
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2C1;
+ PeriphClkInitStruct.I2c123ClockSelection = RCC_I2C1235CLKSOURCE_D2PCLK1;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+ /**I2C1 GPIO Configuration
+ PB6 ------> I2C1_SCL
+ PB7 ------> I2C1_SDA
+ */
+ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
+ HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+ /* Peripheral clock enable */
+ __HAL_RCC_I2C1_CLK_ENABLE();
+ /* USER CODE BEGIN I2C1_MspInit 1 */
+
+ /* USER CODE END I2C1_MspInit 1 */
+ }
+
+}
+
+/**
+* @brief I2C MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hi2c: I2C handle pointer
+* @retval None
+*/
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c)
+{
+ if(hi2c->Instance==I2C1)
+ {
+ /* USER CODE BEGIN I2C1_MspDeInit 0 */
+
+ /* USER CODE END I2C1_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_I2C1_CLK_DISABLE();
+
+ /**I2C1 GPIO Configuration
+ PB6 ------> I2C1_SCL
+ PB7 ------> I2C1_SDA
+ */
+ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6);
+
+ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_7);
+
+ /* USER CODE BEGIN I2C1_MspDeInit 1 */
+
+ /* USER CODE END I2C1_MspDeInit 1 */
+ }
+
+}
+
+/**
+* @brief UART MSP Initialization
+* This function configures the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+ if(huart->Instance==USART1)
+ {
+ /* USER CODE BEGIN USART1_MspInit 0 */
+
+ /* USER CODE END USART1_MspInit 0 */
+
+ /** Initializes the peripherals clock
+ */
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1;
+ PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16910CLKSOURCE_D2PCLK2;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /* Peripheral clock enable */
+ __HAL_RCC_USART1_CLK_ENABLE();
+
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ /**USART1 GPIO Configuration
+ PA9 ------> USART1_TX
+ PA10 ------> USART1_RX
+ */
+ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+ HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+ /* USER CODE BEGIN USART1_MspInit 1 */
+
+ /* USER CODE END USART1_MspInit 1 */
+ }
+
+}
+
+/**
+* @brief UART MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+ if(huart->Instance==USART1)
+ {
+ /* USER CODE BEGIN USART1_MspDeInit 0 */
+
+ /* USER CODE END USART1_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __HAL_RCC_USART1_CLK_DISABLE();
+
+ /**USART1 GPIO Configuration
+ PA9 ------> USART1_TX
+ PA10 ------> USART1_RX
+ */
+ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10);
+
+ /* USER CODE BEGIN USART1_MspDeInit 1 */
+
+ /* USER CODE END USART1_MspDeInit 1 */
+ }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
diff --git a/Core/Src/stm32h7xx_it.c b/Core/Src/stm32h7xx_it.c new file mode 100644 index 0000000..f386243 --- /dev/null +++ b/Core/Src/stm32h7xx_it.c @@ -0,0 +1,247 @@ +/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file stm32h7xx_it.c
+ * @brief Interrupt Service Routines.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2023 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32h7xx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern DMA_HandleTypeDef hdma_adc1;
+extern DMA_HandleTypeDef hdma_adc2;
+extern DMA_HandleTypeDef hdma_dac1_ch2;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/* Cortex Processor Interruption and Exception Handlers */
+/******************************************************************************/
+/**
+ * @brief This function handles Non maskable interrupt.
+ */
+void NMI_Handler(void)
+{
+ /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+ /* USER CODE END NonMaskableInt_IRQn 0 */
+ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+ while (1)
+ {
+ }
+ /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+ * @brief This function handles Hard fault interrupt.
+ */
+void HardFault_Handler(void)
+{
+ /* USER CODE BEGIN HardFault_IRQn 0 */
+
+ /* USER CODE END HardFault_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+ /* USER CODE END W1_HardFault_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles Memory management fault.
+ */
+void MemManage_Handler(void)
+{
+ /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+ /* USER CODE END MemoryManagement_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+ /* USER CODE END W1_MemoryManagement_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles Pre-fetch fault, memory access fault.
+ */
+void BusFault_Handler(void)
+{
+ /* USER CODE BEGIN BusFault_IRQn 0 */
+
+ /* USER CODE END BusFault_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+ /* USER CODE END W1_BusFault_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles Undefined instruction or illegal state.
+ */
+void UsageFault_Handler(void)
+{
+ /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+ /* USER CODE END UsageFault_IRQn 0 */
+ while (1)
+ {
+ /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+ /* USER CODE END W1_UsageFault_IRQn 0 */
+ }
+}
+
+/**
+ * @brief This function handles System service call via SWI instruction.
+ */
+void SVC_Handler(void)
+{
+ /* USER CODE BEGIN SVCall_IRQn 0 */
+
+ /* USER CODE END SVCall_IRQn 0 */
+ /* USER CODE BEGIN SVCall_IRQn 1 */
+
+ /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+ * @brief This function handles Debug monitor.
+ */
+void DebugMon_Handler(void)
+{
+ /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+ /* USER CODE END DebugMonitor_IRQn 0 */
+ /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+ /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+ * @brief This function handles Pendable request for system service.
+ */
+void PendSV_Handler(void)
+{
+ /* USER CODE BEGIN PendSV_IRQn 0 */
+
+ /* USER CODE END PendSV_IRQn 0 */
+ /* USER CODE BEGIN PendSV_IRQn 1 */
+
+ /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+ * @brief This function handles System tick timer.
+ */
+void SysTick_Handler(void)
+{
+ /* USER CODE BEGIN SysTick_IRQn 0 */
+
+ /* USER CODE END SysTick_IRQn 0 */
+ HAL_IncTick();
+ /* USER CODE BEGIN SysTick_IRQn 1 */
+
+ /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32H7xx Peripheral Interrupt Handlers */
+/* Add here the Interrupt Handlers for the used peripherals. */
+/* For the available peripheral interrupt handler names, */
+/* please refer to the startup file (startup_stm32h7xx.s). */
+/******************************************************************************/
+
+/**
+ * @brief This function handles DMA1 stream0 global interrupt.
+ */
+void DMA1_Stream0_IRQHandler(void)
+{
+ /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */
+
+ /* USER CODE END DMA1_Stream0_IRQn 0 */
+ HAL_DMA_IRQHandler(&hdma_adc1);
+ /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */
+
+ /* USER CODE END DMA1_Stream0_IRQn 1 */
+}
+
+/**
+ * @brief This function handles DMA1 stream1 global interrupt.
+ */
+void DMA1_Stream1_IRQHandler(void)
+{
+ /* USER CODE BEGIN DMA1_Stream1_IRQn 0 */
+
+ /* USER CODE END DMA1_Stream1_IRQn 0 */
+ HAL_DMA_IRQHandler(&hdma_adc2);
+ /* USER CODE BEGIN DMA1_Stream1_IRQn 1 */
+
+ /* USER CODE END DMA1_Stream1_IRQn 1 */
+}
+
+/**
+ * @brief This function handles DMA1 stream2 global interrupt.
+ */
+void DMA1_Stream2_IRQHandler(void)
+{
+ /* USER CODE BEGIN DMA1_Stream2_IRQn 0 */
+
+ /* USER CODE END DMA1_Stream2_IRQn 0 */
+ HAL_DMA_IRQHandler(&hdma_dac1_ch2);
+ /* USER CODE BEGIN DMA1_Stream2_IRQn 1 */
+
+ /* USER CODE END DMA1_Stream2_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
diff --git a/Core/Src/system_stm32h7xx.c b/Core/Src/system_stm32h7xx.c new file mode 100644 index 0000000..851ebcb --- /dev/null +++ b/Core/Src/system_stm32h7xx.c @@ -0,0 +1,450 @@ +/**
+ ******************************************************************************
+ * @file system_stm32h7xx.c
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
+ *
+ * This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32h7xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock, it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32h7xx_system
+ * @{
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32h7xx.h"
+#include <math.h>
+
+#if !defined (HSE_VALUE)
+#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (CSI_VALUE)
+ #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Defines
+ * @{
+ */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) */
+/* #define DATA_IN_D2_SRAM */
+
+/* Note: Following vector table addresses must be defined in line with linker
+ configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+ anywhere in FLASH BANK1 or AXI SRAM, else the vector table is kept at the automatic
+ remap of boot address selected */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+/*!< Uncomment the following line if you need to relocate your vector Table
+ in D2 AXI SRAM else user remap will be done in FLASH BANK2. */
+/* #define VECT_TAB_SRAM */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS D2_AXISRAM_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x400. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x400. */
+#else
+#define VECT_TAB_BASE_ADDRESS FLASH_BANK2_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x400. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x400. */
+#endif /* VECT_TAB_SRAM */
+#else
+/*!< Uncomment the following line if you need to relocate your vector Table
+ in D1 AXI SRAM else user remap will be done in FLASH BANK1. */
+/* #define VECT_TAB_SRAM */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x400. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x400. */
+#else
+#define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x400. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x400. */
+#endif /* VECT_TAB_SRAM */
+#endif /* DUAL_CORE && CORE_CM4 */
+#endif /* USER_VECT_TAB_ADDRESS */
+/******************************************************************************/
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Variables
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+ uint32_t SystemCoreClock = 64000000;
+ uint32_t SystemD2Clock = 64000000;
+ const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting and vector table location
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit (void)
+{
+#if defined (DATA_IN_D2_SRAM)
+ __IO uint32_t tmpreg;
+#endif /* DATA_IN_D2_SRAM */
+
+ /* FPU settings ------------------------------------------------------------*/
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
+ #endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+
+ /* Increasing the CPU frequency */
+ if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+ }
+
+ /* Set HSION bit */
+ RCC->CR |= RCC_CR_HSION;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */
+ RCC->CR &= 0xEAF6ED7FU;
+
+ /* Decreasing the number of wait states because of lower CPU frequency */
+ if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+ }
+
+#if defined(D3_SRAM_BASE)
+ /* Reset D1CFGR register */
+ RCC->D1CFGR = 0x00000000;
+
+ /* Reset D2CFGR register */
+ RCC->D2CFGR = 0x00000000;
+
+ /* Reset D3CFGR register */
+ RCC->D3CFGR = 0x00000000;
+#else
+ /* Reset CDCFGR1 register */
+ RCC->CDCFGR1 = 0x00000000;
+
+ /* Reset CDCFGR2 register */
+ RCC->CDCFGR2 = 0x00000000;
+
+ /* Reset SRDCFGR register */
+ RCC->SRDCFGR = 0x00000000;
+#endif
+ /* Reset PLLCKSELR register */
+ RCC->PLLCKSELR = 0x02020200;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x01FF0000;
+ /* Reset PLL1DIVR register */
+ RCC->PLL1DIVR = 0x01010280;
+ /* Reset PLL1FRACR register */
+ RCC->PLL1FRACR = 0x00000000;
+
+ /* Reset PLL2DIVR register */
+ RCC->PLL2DIVR = 0x01010280;
+
+ /* Reset PLL2FRACR register */
+
+ RCC->PLL2FRACR = 0x00000000;
+ /* Reset PLL3DIVR register */
+ RCC->PLL3DIVR = 0x01010280;
+
+ /* Reset PLL3FRACR register */
+ RCC->PLL3FRACR = 0x00000000;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= 0xFFFBFFFFU;
+
+ /* Disable all interrupts */
+ RCC->CIER = 0x00000000;
+
+#if (STM32H7_DEV_ID == 0x450UL)
+ /* dual core CM7 or single core line */
+ if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
+ {
+ /* if stm32h7 revY*/
+ /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
+ *((__IO uint32_t*)0x51008108) = 0x000000001U;
+ }
+#endif /* STM32H7_DEV_ID */
+
+#if defined(DATA_IN_D2_SRAM)
+ /* in case of initialized data in D2 SRAM (AHB SRAM), enable the D2 SRAM clock (AHB SRAM clock) */
+#if defined(RCC_AHB2ENR_D2SRAM3EN)
+ RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
+#elif defined(RCC_AHB2ENR_D2SRAM2EN)
+ RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN);
+#else
+ RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
+#endif /* RCC_AHB2ENR_D2SRAM3EN */
+
+ tmpreg = RCC->AHB2ENR;
+ (void) tmpreg;
+#endif /* DATA_IN_D2_SRAM */
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+ /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D2 AXI-RAM or in Internal FLASH */
+#endif /* USER_VECT_TAB_ADDRESS */
+
+#else
+ /*
+ * Disable the FMC bank1 (enabled after reset).
+ * This, prevents CPU speculation access on this bank which blocks the use of FMC during
+ * 24us. During this time the others FMC master (such as LTDC) cannot use it!
+ */
+ FMC_Bank1_R->BTCR[0] = 0x000030D2;
+
+ /* Configure the Vector Table location -------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */
+#endif /* USER_VECT_TAB_ADDRESS */
+
+#endif /*DUAL_CORE && CORE_CM4*/
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock , it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
+ * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
+ *
+ * (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+ * 4 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ * (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+ * 64 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+ * 25 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
+ uint32_t common_system_clock;
+ float_t fracn1, pllvco;
+
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+
+ switch (RCC->CFGR & RCC_CFGR_SWS)
+ {
+ case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
+ common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
+ break;
+
+ case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
+ common_system_clock = CSI_VALUE;
+ break;
+
+ case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
+ common_system_clock = HSE_VALUE;
+ break;
+
+ case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
+
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
+ SYSCLK = PLL_VCO / PLLR
+ */
+ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+ pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ;
+ pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
+ fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
+
+ if (pllm != 0U)
+ {
+ switch (pllsource)
+ {
+ case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */
+
+ hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
+ pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+
+ break;
+
+ case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */
+ pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+ break;
+
+ case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */
+ pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+ break;
+
+ default:
+ hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
+ pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+ break;
+ }
+ pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
+ common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
+ }
+ else
+ {
+ common_system_clock = 0U;
+ }
+ break;
+
+ default:
+ common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
+ break;
+ }
+
+ /* Compute SystemClock frequency --------------------------------------------------*/
+#if defined (RCC_D1CFGR_D1CPRE)
+ tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
+
+ /* common_system_clock frequency : CM7 CPU frequency */
+ common_system_clock >>= tmp;
+
+ /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
+ SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+
+#else
+ tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos];
+
+ /* common_system_clock frequency : CM7 CPU frequency */
+ common_system_clock >>= tmp;
+
+ /* SystemD2Clock frequency : AXI and AHBs Clock frequency */
+ SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+ SystemCoreClock = SystemD2Clock;
+#else
+ SystemCoreClock = common_system_clock;
+#endif /* DUAL_CORE && CORE_CM4 */
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
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