diff options
| author | joshua <joshua@joshuayun.com> | 2023-12-30 23:54:31 -0500 |
|---|---|---|
| committer | joshua <joshua@joshuayun.com> | 2023-12-30 23:54:31 -0500 |
| commit | 86608c6770cf08c138a2bdab5855072f64be09ef (patch) | |
| tree | 494a61b3ef37e76f9235a0d10f5c93d97290a35f /Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5 | |
| download | sdr-software-master.tar.gz | |
Diffstat (limited to 'Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5')
10 files changed, 1473 insertions, 0 deletions
diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/RTX_Config.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/RTX_Config.c new file mode 100644 index 0000000..719a5ca --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,63 @@ +/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * $Revision: V5.1.0
+ *
+ * Project: CMSIS-RTOS RTX
+ * Title: RTX Configuration
+ *
+ * -----------------------------------------------------------------------------
+ */
+
+#include "cmsis_compiler.h"
+#include "rtx_os.h"
+
+// OS Idle Thread
+__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {
+ (void)argument;
+
+ for (;;) {}
+}
+
+// OS Error Callback function
+__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {
+ (void)object_id;
+
+ switch (code) {
+ case osRtxErrorStackUnderflow:
+ // Stack underflow detected for thread (thread_id=object_id)
+ break;
+ case osRtxErrorISRQueueOverflow:
+ // ISR Queue overflow detected when inserting object (object_id)
+ break;
+ case osRtxErrorTimerQueueOverflow:
+ // User Timer Callback Queue overflow detected for timer (timer_id=object_id)
+ break;
+ case osRtxErrorClibSpace:
+ // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM
+ break;
+ case osRtxErrorClibMutex:
+ // Standard C/C++ library mutex initialization failed
+ break;
+ default:
+ break;
+ }
+ for (;;) {}
+return 0U;
+}
diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/RTX_Config.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/RTX_Config.h new file mode 100644 index 0000000..f9bb303 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,578 @@ +/*
+ * Copyright (c) 2013-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * $Revision: V5.5.0
+ *
+ * Project: CMSIS-RTOS RTX
+ * Title: RTX Configuration definitions
+ *
+ * -----------------------------------------------------------------------------
+ */
+
+#ifndef RTX_CONFIG_H_
+#define RTX_CONFIG_H_
+
+#ifdef _RTE_
+#include "RTE_Components.h"
+#ifdef RTE_RTX_CONFIG_H
+#include RTE_RTX_CONFIG_H
+#endif
+#endif
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// <h>System Configuration
+// =======================
+
+// <o>Global Dynamic Memory size [bytes] <0-1073741824:8>
+// <i> Defines the combined global dynamic memory size.
+// <i> Default: 4096
+#ifndef OS_DYNAMIC_MEM_SIZE
+#define OS_DYNAMIC_MEM_SIZE 4096
+#endif
+
+// <o>Kernel Tick Frequency [Hz] <1-1000000>
+// <i> Defines base time unit for delays and timeouts.
+// <i> Default: 1000 (1ms tick)
+#ifndef OS_TICK_FREQ
+#define OS_TICK_FREQ 1000
+#endif
+
+// <e>Round-Robin Thread switching
+// <i> Enables Round-Robin Thread switching.
+#ifndef OS_ROBIN_ENABLE
+#define OS_ROBIN_ENABLE 1
+#endif
+
+// <o>Round-Robin Timeout <1-1000>
+// <i> Defines how many ticks a thread will execute before a thread switch.
+// <i> Default: 5
+#ifndef OS_ROBIN_TIMEOUT
+#define OS_ROBIN_TIMEOUT 5
+#endif
+
+// </e>
+
+// <o>ISR FIFO Queue
+// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries
+// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries
+// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries
+// <i> RTOS Functions called from ISR store requests to this buffer.
+// <i> Default: 16 entries
+#ifndef OS_ISR_FIFO_QUEUE
+#define OS_ISR_FIFO_QUEUE 16
+#endif
+
+// <q>Object Memory usage counters
+// <i> Enables object memory usage counters (requires RTX source variant).
+#ifndef OS_OBJ_MEM_USAGE
+#define OS_OBJ_MEM_USAGE 0
+#endif
+
+// </h>
+
+// <h>Thread Configuration
+// =======================
+
+// <e>Object specific Memory allocation
+// <i> Enables object specific memory allocation.
+#ifndef OS_THREAD_OBJ_MEM
+#define OS_THREAD_OBJ_MEM 0
+#endif
+
+// <o>Number of user Threads <1-1000>
+// <i> Defines maximum number of user threads that can be active at the same time.
+// <i> Applies to user threads with system provided memory for control blocks.
+#ifndef OS_THREAD_NUM
+#define OS_THREAD_NUM 1
+#endif
+
+// <o>Number of user Threads with default Stack size <0-1000>
+// <i> Defines maximum number of user threads with default stack size.
+// <i> Applies to user threads with zero stack size specified.
+#ifndef OS_THREAD_DEF_STACK_NUM
+#define OS_THREAD_DEF_STACK_NUM 0
+#endif
+
+// <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>
+// <i> Defines the combined stack size for user threads with user-provided stack size.
+// <i> Applies to user threads with user-provided stack size and system provided memory for stack.
+// <i> Default: 0
+#ifndef OS_THREAD_USER_STACK_SIZE
+#define OS_THREAD_USER_STACK_SIZE 0
+#endif
+
+// </e>
+
+// <o>Default Thread Stack size [bytes] <96-1073741824:8>
+// <i> Defines stack size for threads with zero stack size specified.
+// <i> Default: 256
+#ifndef OS_STACK_SIZE
+#define OS_STACK_SIZE 512
+#endif
+
+// <o>Idle Thread Stack size [bytes] <72-1073741824:8>
+// <i> Defines stack size for Idle thread.
+// <i> Default: 256
+#ifndef OS_IDLE_THREAD_STACK_SIZE
+#define OS_IDLE_THREAD_STACK_SIZE 512
+#endif
+
+// <o>Idle Thread TrustZone Module Identifier
+// <i> Defines TrustZone Thread Context Management Identifier.
+// <i> Applies only to cores with TrustZone technology.
+// <i> Default: 0 (not used)
+#ifndef OS_IDLE_THREAD_TZ_MOD_ID
+#define OS_IDLE_THREAD_TZ_MOD_ID 0
+#endif
+
+// <q>Stack overrun checking
+// <i> Enables stack overrun check at thread switch.
+// <i> Enabling this option increases slightly the execution time of a thread switch.
+#ifndef OS_STACK_CHECK
+#define OS_STACK_CHECK 1
+#endif
+
+// <q>Stack usage watermark
+// <i> Initializes thread stack with watermark pattern for analyzing stack usage.
+// <i> Enabling this option increases significantly the execution time of thread creation.
+#ifndef OS_STACK_WATERMARK
+#define OS_STACK_WATERMARK 0
+#endif
+
+// <o>Processor mode for Thread execution
+// <0=> Unprivileged mode
+// <1=> Privileged mode
+// <i> Default: Privileged mode
+#ifndef OS_PRIVILEGE_MODE
+#define OS_PRIVILEGE_MODE 1
+#endif
+
+// </h>
+
+// <h>Timer Configuration
+// ======================
+
+// <e>Object specific Memory allocation
+// <i> Enables object specific memory allocation.
+#ifndef OS_TIMER_OBJ_MEM
+#define OS_TIMER_OBJ_MEM 0
+#endif
+
+// <o>Number of Timer objects <1-1000>
+// <i> Defines maximum number of objects that can be active at the same time.
+// <i> Applies to objects with system provided memory for control blocks.
+#ifndef OS_TIMER_NUM
+#define OS_TIMER_NUM 1
+#endif
+
+// </e>
+
+// <o>Timer Thread Priority
+// <8=> Low
+// <16=> Below Normal <24=> Normal <32=> Above Normal
+// <40=> High
+// <48=> Realtime
+// <i> Defines priority for timer thread
+// <i> Default: High
+#ifndef OS_TIMER_THREAD_PRIO
+#define OS_TIMER_THREAD_PRIO 40
+#endif
+
+// <o>Timer Thread Stack size [bytes] <0-1073741824:8>
+// <i> Defines stack size for Timer thread.
+// <i> May be set to 0 when timers are not used.
+// <i> Default: 256
+#ifndef OS_TIMER_THREAD_STACK_SIZE
+#define OS_TIMER_THREAD_STACK_SIZE 256
+#endif
+
+// <o>Timer Thread TrustZone Module Identifier
+// <i> Defines TrustZone Thread Context Management Identifier.
+// <i> Applies only to cores with TrustZone technology.
+// <i> Default: 0 (not used)
+#ifndef OS_TIMER_THREAD_TZ_MOD_ID
+#define OS_TIMER_THREAD_TZ_MOD_ID 0
+#endif
+
+// <o>Timer Callback Queue entries <0-256>
+// <i> Number of concurrent active timer callback functions.
+// <i> May be set to 0 when timers are not used.
+// <i> Default: 4
+#ifndef OS_TIMER_CB_QUEUE
+#define OS_TIMER_CB_QUEUE 4
+#endif
+
+// </h>
+
+// <h>Event Flags Configuration
+// ============================
+
+// <e>Object specific Memory allocation
+// <i> Enables object specific memory allocation.
+#ifndef OS_EVFLAGS_OBJ_MEM
+#define OS_EVFLAGS_OBJ_MEM 0
+#endif
+
+// <o>Number of Event Flags objects <1-1000>
+// <i> Defines maximum number of objects that can be active at the same time.
+// <i> Applies to objects with system provided memory for control blocks.
+#ifndef OS_EVFLAGS_NUM
+#define OS_EVFLAGS_NUM 1
+#endif
+
+// </e>
+
+// </h>
+
+// <h>Mutex Configuration
+// ======================
+
+// <e>Object specific Memory allocation
+// <i> Enables object specific memory allocation.
+#ifndef OS_MUTEX_OBJ_MEM
+#define OS_MUTEX_OBJ_MEM 0
+#endif
+
+// <o>Number of Mutex objects <1-1000>
+// <i> Defines maximum number of objects that can be active at the same time.
+// <i> Applies to objects with system provided memory for control blocks.
+#ifndef OS_MUTEX_NUM
+#define OS_MUTEX_NUM 1
+#endif
+
+// </e>
+
+// </h>
+
+// <h>Semaphore Configuration
+// ==========================
+
+// <e>Object specific Memory allocation
+// <i> Enables object specific memory allocation.
+#ifndef OS_SEMAPHORE_OBJ_MEM
+#define OS_SEMAPHORE_OBJ_MEM 0
+#endif
+
+// <o>Number of Semaphore objects <1-1000>
+// <i> Defines maximum number of objects that can be active at the same time.
+// <i> Applies to objects with system provided memory for control blocks.
+#ifndef OS_SEMAPHORE_NUM
+#define OS_SEMAPHORE_NUM 1
+#endif
+
+// </e>
+
+// </h>
+
+// <h>Memory Pool Configuration
+// ============================
+
+// <e>Object specific Memory allocation
+// <i> Enables object specific memory allocation.
+#ifndef OS_MEMPOOL_OBJ_MEM
+#define OS_MEMPOOL_OBJ_MEM 0
+#endif
+
+// <o>Number of Memory Pool objects <1-1000>
+// <i> Defines maximum number of objects that can be active at the same time.
+// <i> Applies to objects with system provided memory for control blocks.
+#ifndef OS_MEMPOOL_NUM
+#define OS_MEMPOOL_NUM 1
+#endif
+
+// <o>Data Storage Memory size [bytes] <0-1073741824:8>
+// <i> Defines the combined data storage memory size.
+// <i> Applies to objects with system provided memory for data storage.
+// <i> Default: 0
+#ifndef OS_MEMPOOL_DATA_SIZE
+#define OS_MEMPOOL_DATA_SIZE 0
+#endif
+
+// </e>
+
+// </h>
+
+// <h>Message Queue Configuration
+// ==============================
+
+// <e>Object specific Memory allocation
+// <i> Enables object specific memory allocation.
+#ifndef OS_MSGQUEUE_OBJ_MEM
+#define OS_MSGQUEUE_OBJ_MEM 0
+#endif
+
+// <o>Number of Message Queue objects <1-1000>
+// <i> Defines maximum number of objects that can be active at the same time.
+// <i> Applies to objects with system provided memory for control blocks.
+#ifndef OS_MSGQUEUE_NUM
+#define OS_MSGQUEUE_NUM 1
+#endif
+
+// <o>Data Storage Memory size [bytes] <0-1073741824:8>
+// <i> Defines the combined data storage memory size.
+// <i> Applies to objects with system provided memory for data storage.
+// <i> Default: 0
+#ifndef OS_MSGQUEUE_DATA_SIZE
+#define OS_MSGQUEUE_DATA_SIZE 0
+#endif
+
+// </e>
+
+// </h>
+
+// <h>Event Recorder Configuration
+// ===============================
+
+// <e>Global Initialization
+// <i> Initialize Event Recorder during 'osKernelInitialize'.
+#ifndef OS_EVR_INIT
+#define OS_EVR_INIT 0
+#endif
+
+// <q>Start recording
+// <i> Start event recording after initialization.
+#ifndef OS_EVR_START
+#define OS_EVR_START 1
+#endif
+
+// <h>Global Event Filter Setup
+// <i> Initial recording level applied to all components.
+// <o.0>Error events
+// <o.1>API function call events
+// <o.2>Operation events
+// <o.3>Detailed operation events
+// </h>
+#ifndef OS_EVR_LEVEL
+#define OS_EVR_LEVEL 0x00U
+#endif
+
+// <h>RTOS Event Filter Setup
+// <i> Recording levels for RTX components.
+// <i> Only applicable if events for the respective component are generated.
+
+// <h>Memory Management
+// <i> Recording level for Memory Management events.
+// <o.0>Error events
+// <o.1>API function call events
+// <o.2>Operation events
+// <o.3>Detailed operation events
+// </h>
+#ifndef OS_EVR_MEMORY_LEVEL
+#define OS_EVR_MEMORY_LEVEL 0x01U
+#endif
+
+// <h>Kernel
+// <i> Recording level for Kernel events.
+// <o.0>Error events
+// <o.1>API function call events
+// <o.2>Operation events
+// <o.3>Detailed operation events
+// </h>
+#ifndef OS_EVR_KERNEL_LEVEL
+#define OS_EVR_KERNEL_LEVEL 0x01U
+#endif
+
+// <h>Thread
+// <i> Recording level for Thread events.
+// <o.0>Error events
+// <o.1>API function call events
+// <o.2>Operation events
+// <o.3>Detailed operation events
+// </h>
+#ifndef OS_EVR_THREAD_LEVEL
+#define OS_EVR_THREAD_LEVEL 0x05U
+#endif
+
+// <h>Generic Wait
+// <i> Recording level for Generic Wait events.
+// <o.0>Error events
+// <o.1>API function call events
+// <o.2>Operation events
+// <o.3>Detailed operation events
+// </h>
+#ifndef OS_EVR_WAIT_LEVEL
+#define OS_EVR_WAIT_LEVEL 0x01U
+#endif
+
+// <h>Thread Flags
+// <i> Recording level for Thread Flags events.
+// <o.0>Error events
+// <o.1>API function call events
+// <o.2>Operation events
+// <o.3>Detailed operation events
+// </h>
+#ifndef OS_EVR_THFLAGS_LEVEL
+#define OS_EVR_THFLAGS_LEVEL 0x01U
+#endif
+
+// <h>Event Flags
+// <i> Recording level for Event Flags events.
+// <o.0>Error events
+// <o.1>API function call events
+// <o.2>Operation events
+// <o.3>Detailed operation events
+// </h>
+#ifndef OS_EVR_EVFLAGS_LEVEL
+#define OS_EVR_EVFLAGS_LEVEL 0x01U
+#endif
+
+// <h>Timer
+// <i> Recording level for Timer events.
+// <o.0>Error events
+// <o.1>API function call events
+// <o.2>Operation events
+// <o.3>Detailed operation events
+// </h>
+#ifndef OS_EVR_TIMER_LEVEL
+#define OS_EVR_TIMER_LEVEL 0x01U
+#endif
+
+// <h>Mutex
+// <i> Recording level for Mutex events.
+// <o.0>Error events
+// <o.1>API function call events
+// <o.2>Operation events
+// <o.3>Detailed operation events
+// </h>
+#ifndef OS_EVR_MUTEX_LEVEL
+#define OS_EVR_MUTEX_LEVEL 0x01U
+#endif
+
+// <h>Semaphore
+// <i> Recording level for Semaphore events.
+// <o.0>Error events
+// <o.1>API function call events
+// <o.2>Operation events
+// <o.3>Detailed operation events
+// </h>
+#ifndef OS_EVR_SEMAPHORE_LEVEL
+#define OS_EVR_SEMAPHORE_LEVEL 0x01U
+#endif
+
+// <h>Memory Pool
+// <i> Recording level for Memory Pool events.
+// <o.0>Error events
+// <o.1>API function call events
+// <o.2>Operation events
+// <o.3>Detailed operation events
+// </h>
+#ifndef OS_EVR_MEMPOOL_LEVEL
+#define OS_EVR_MEMPOOL_LEVEL 0x01U
+#endif
+
+// <h>Message Queue
+// <i> Recording level for Message Queue events.
+// <o.0>Error events
+// <o.1>API function call events
+// <o.2>Operation events
+// <o.3>Detailed operation events
+// </h>
+#ifndef OS_EVR_MSGQUEUE_LEVEL
+#define OS_EVR_MSGQUEUE_LEVEL 0x01U
+#endif
+
+// </h>
+
+// </e>
+
+// <h>RTOS Event Generation
+// <i> Enables event generation for RTX components (requires RTX source variant).
+
+// <q>Memory Management
+// <i> Enables Memory Management event generation.
+#ifndef OS_EVR_MEMORY
+#define OS_EVR_MEMORY 1
+#endif
+
+// <q>Kernel
+// <i> Enables Kernel event generation.
+#ifndef OS_EVR_KERNEL
+#define OS_EVR_KERNEL 1
+#endif
+
+// <q>Thread
+// <i> Enables Thread event generation.
+#ifndef OS_EVR_THREAD
+#define OS_EVR_THREAD 1
+#endif
+
+// <q>Generic Wait
+// <i> Enables Generic Wait event generation.
+#ifndef OS_EVR_WAIT
+#define OS_EVR_WAIT 1
+#endif
+
+// <q>Thread Flags
+// <i> Enables Thread Flags event generation.
+#ifndef OS_EVR_THFLAGS
+#define OS_EVR_THFLAGS 1
+#endif
+
+// <q>Event Flags
+// <i> Enables Event Flags event generation.
+#ifndef OS_EVR_EVFLAGS
+#define OS_EVR_EVFLAGS 1
+#endif
+
+// <q>Timer
+// <i> Enables Timer event generation.
+#ifndef OS_EVR_TIMER
+#define OS_EVR_TIMER 1
+#endif
+
+// <q>Mutex
+// <i> Enables Mutex event generation.
+#ifndef OS_EVR_MUTEX
+#define OS_EVR_MUTEX 1
+#endif
+
+// <q>Semaphore
+// <i> Enables Semaphore event generation.
+#ifndef OS_EVR_SEMAPHORE
+#define OS_EVR_SEMAPHORE 1
+#endif
+
+// <q>Memory Pool
+// <i> Enables Memory Pool event generation.
+#ifndef OS_EVR_MEMPOOL
+#define OS_EVR_MEMPOOL 1
+#endif
+
+// <q>Message Queue
+// <i> Enables Message Queue event generation.
+#ifndef OS_EVR_MSGQUEUE
+#define OS_EVR_MSGQUEUE 1
+#endif
+
+// </h>
+
+// </h>
+
+// Number of Threads which use standard C/C++ library libspace
+// (when thread specific memory allocation is not used).
+#if (OS_THREAD_OBJ_MEM == 0)
+#define OS_THREAD_LIBSPACE_NUM 4
+#else
+#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM
+#endif
+
+//------------- <<< end of configuration section >>> ---------------------------
+
+#endif // RTX_CONFIG_H_
diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/handlers.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/handlers.c new file mode 100644 index 0000000..ee65ce4 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/handlers.c @@ -0,0 +1,153 @@ +/*
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * -----------------------------------------------------------------------------
+ *
+ * Project: CMSIS-RTOS RTX
+ * Title: Exception handlers (C functions)
+ *
+ * -----------------------------------------------------------------------------
+ */
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+
+//Fault Status Register (IFSR/DFSR) definitions
+#define FSR_ALIGNMENT_FAULT 0x01 //DFSR only. Fault on first lookup
+#define FSR_INSTRUCTION_CACHE_MAINTENANCE 0x04 //DFSR only - async/external
+#define FSR_SYNC_EXT_TTB_WALK_FIRST 0x0c //sync/external
+#define FSR_SYNC_EXT_TTB_WALK_SECOND 0x0e //sync/external
+#define FSR_SYNC_PARITY_TTB_WALK_FIRST 0x1c //sync/external
+#define FSR_SYNC_PARITY_TTB_WALK_SECOND 0x1e //sync/external
+#define FSR_TRANSLATION_FAULT_FIRST 0x05 //MMU Fault - internal
+#define FSR_TRANSLATION_FAULT_SECOND 0x07 //MMU Fault - internal
+#define FSR_ACCESS_FLAG_FAULT_FIRST 0x03 //MMU Fault - internal
+#define FSR_ACCESS_FLAG_FAULT_SECOND 0x06 //MMU Fault - internal
+#define FSR_DOMAIN_FAULT_FIRST 0x09 //MMU Fault - internal
+#define FSR_DOMAIN_FAULT_SECOND 0x0b //MMU Fault - internal
+#define FSR_PERMISSION_FAULT_FIRST 0x0f //MMU Fault - internal
+#define FSR_PERMISSION_FAULT_SECOND 0x0d //MMU Fault - internal
+#define FSR_DEBUG_EVENT 0x02 //internal
+#define FSR_SYNC_EXT_ABORT 0x08 //sync/external
+#define FSR_TLB_CONFLICT_ABORT 0x10 //sync/external
+#define FSR_LOCKDOWN 0x14 //internal
+#define FSR_COPROCESSOR_ABORT 0x1a //internal
+#define FSR_SYNC_PARITY_ERROR 0x19 //sync/external
+#define FSR_ASYNC_EXTERNAL_ABORT 0x16 //DFSR only - async/external
+#define FSR_ASYNC_PARITY_ERROR 0x18 //DFSR only - async/external
+
+void CDAbtHandler(uint32_t DFSR, uint32_t DFAR, uint32_t LR) {
+ uint32_t FS = (DFSR & (1 << 10)) >> 6 | (DFSR & 0x0f); //Store Fault Status
+
+ switch(FS) {
+ //Synchronous parity errors - retry
+ case FSR_SYNC_PARITY_ERROR:
+ case FSR_SYNC_PARITY_TTB_WALK_FIRST:
+ case FSR_SYNC_PARITY_TTB_WALK_SECOND:
+ return;
+
+ //Your code here. Value in DFAR is invalid for some fault statuses.
+ case FSR_ALIGNMENT_FAULT:
+ case FSR_INSTRUCTION_CACHE_MAINTENANCE:
+ case FSR_SYNC_EXT_TTB_WALK_FIRST:
+ case FSR_SYNC_EXT_TTB_WALK_SECOND:
+ case FSR_TRANSLATION_FAULT_FIRST:
+ case FSR_TRANSLATION_FAULT_SECOND:
+ case FSR_ACCESS_FLAG_FAULT_FIRST:
+ case FSR_ACCESS_FLAG_FAULT_SECOND:
+ case FSR_DOMAIN_FAULT_FIRST:
+ case FSR_DOMAIN_FAULT_SECOND:
+ case FSR_PERMISSION_FAULT_FIRST:
+ case FSR_PERMISSION_FAULT_SECOND:
+ case FSR_DEBUG_EVENT:
+ case FSR_SYNC_EXT_ABORT:
+ case FSR_TLB_CONFLICT_ABORT:
+ case FSR_LOCKDOWN:
+ case FSR_COPROCESSOR_ABORT:
+ case FSR_ASYNC_EXTERNAL_ABORT: //DFAR invalid
+ case FSR_ASYNC_PARITY_ERROR: //DFAR invalid
+ default:
+ while(1);
+ }
+}
+
+void CPAbtHandler(uint32_t IFSR, uint32_t IFAR, uint32_t LR) {
+ uint32_t FS = (IFSR & (1 << 10)) >> 6 | (IFSR & 0x0f); //Store Fault Status
+
+ switch(FS) {
+ //Synchronous parity errors - retry
+ case FSR_SYNC_PARITY_ERROR:
+ case FSR_SYNC_PARITY_TTB_WALK_FIRST:
+ case FSR_SYNC_PARITY_TTB_WALK_SECOND:
+ return;
+
+ //Your code here. Value in IFAR is invalid for some fault statuses.
+ case FSR_SYNC_EXT_TTB_WALK_FIRST:
+ case FSR_SYNC_EXT_TTB_WALK_SECOND:
+ case FSR_TRANSLATION_FAULT_FIRST:
+ case FSR_TRANSLATION_FAULT_SECOND:
+ case FSR_ACCESS_FLAG_FAULT_FIRST:
+ case FSR_ACCESS_FLAG_FAULT_SECOND:
+ case FSR_DOMAIN_FAULT_FIRST:
+ case FSR_DOMAIN_FAULT_SECOND:
+ case FSR_PERMISSION_FAULT_FIRST:
+ case FSR_PERMISSION_FAULT_SECOND:
+ case FSR_DEBUG_EVENT: //IFAR invalid
+ case FSR_SYNC_EXT_ABORT:
+ case FSR_TLB_CONFLICT_ABORT:
+ case FSR_LOCKDOWN:
+ case FSR_COPROCESSOR_ABORT:
+ default:
+ while(1);
+ }
+}
+
+
+//returns amount to decrement lr by
+//this will be 0 when we have emulated the instruction and want to execute the next instruction
+//this will be 2 when we have performed some maintenance and want to retry the instruction in Thumb (state == 2)
+//this will be 4 when we have performed some maintenance and want to retry the instruction in ARM (state == 4)
+uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) {
+ const int THUMB = 2;
+ const int ARM = 4;
+ //Lazy VFP/NEON initialisation and switching
+
+ // (ARM ARM section A7.5) VFP data processing instruction?
+ // (ARM ARM section A7.6) VFP/NEON register load/store instruction?
+ // (ARM ARM section A7.8) VFP/NEON register data transfer instruction?
+ // (ARM ARM section A7.9) VFP/NEON 64-bit register data transfer instruction?
+ if ((state == ARM && ((opcode & 0x0C000000) >> 26 == 0x03)) ||
+ (state == THUMB && ((opcode & 0xEC000000) >> 26 == 0x3B))) {
+ if (((opcode & 0x00000E00) >> 9) == 5) {
+ __FPU_Enable();
+ return state;
+ }
+ }
+
+ // (ARM ARM section A7.4) NEON data processing instruction?
+ if ((state == ARM && ((opcode & 0xFE000000) >> 24 == 0xF2)) ||
+ (state == THUMB && ((opcode & 0xEF000000) >> 24 == 0xEF)) ||
+ // (ARM ARM section A7.7) NEON load/store instruction?
+ (state == ARM && ((opcode >> 24) == 0xF4)) ||
+ (state == THUMB && ((opcode >> 24) == 0xF9))) {
+ __FPU_Enable();
+ return state;
+ }
+
+ //Add code here for other Undef cases
+ while(1);
+}
diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/mem_ARMCA5.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/mem_ARMCA5.h new file mode 100644 index 0000000..96fc081 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/mem_ARMCA5.h @@ -0,0 +1,94 @@ +/**************************************************************************//**
+ * @file mem_ARMCA5.h
+ * @brief Memory base and size definitions (used in scatter file)
+ * @version V1.00
+ * @date 10. January 2018
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MEM_ARMCA5_H
+#define __MEM_ARMCA5_H
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap size definition
+ *----------------------------------------------------------------------------*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- ROM Configuration ------------------------------------
+//
+// <h> ROM Configuration
+// <o0> ROM Base Address <0x0-0xFFFFFFFF:8>
+// <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x80000000
+#define __ROM_SIZE 0x00200000
+
+/*--------------------- RAM Configuration -----------------------------------
+// <h> RAM Configuration
+// <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+// <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <h> Stack / Heap Configuration
+// <o4> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o5> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <h> Exceptional Modes
+// <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+// </h>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE 0x80200000
+#define __RAM_SIZE 0x00200000
+
+#define __RW_DATA_SIZE 0x00100000
+#define __ZI_DATA_SIZE 0x000F0000
+
+#define __STACK_SIZE 0x00001000
+#define __HEAP_SIZE 0x00008000
+
+#define __UND_STACK_SIZE 0x00000100
+#define __ABT_STACK_SIZE 0x00000100
+#define __SVC_STACK_SIZE 0x00000100
+#define __IRQ_STACK_SIZE 0x00000100
+#define __FIQ_STACK_SIZE 0x00000100
+
+/*----------------------------------------------------------------------------*/
+
+/*--------------------- TTB Configuration ------------------------------------
+//
+// <h> TTB Configuration
+// <o0> TTB Base Address <0x0-0xFFFFFFFF:8>
+// <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __TTB_BASE 0x80500000
+#define __TTB_SIZE 0x00004000
+
+#endif /* __MEM_ARMCA5_H */
diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/mmu_ARMCA5.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/mmu_ARMCA5.c new file mode 100644 index 0000000..91f1432 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/mmu_ARMCA5.c @@ -0,0 +1,235 @@ +/**************************************************************************//**
+ * @file mmu_ARMCA5.c
+ * @brief MMU Configuration for ARM Cortex-A5 Device Series
+ * @version V1.1.0
+ * @date 23. November 2018
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 ARM Cortex-A Series memory map
+
+ Memory Type
+0xffffffff |--------------------------| ------------
+ | FLAG SYNC | Device Memory
+0xfffff000 |--------------------------| ------------
+ | Fault | Fault
+0xfff00000 |--------------------------| ------------
+ | | Normal
+ | |
+ | Daughterboard |
+ | memory |
+ | |
+0x80505000 |--------------------------| ------------
+ |TTB (L2 Sync Flags ) 4k | Normal
+0x80504C00 |--------------------------| ------------
+ |TTB (L2 Peripherals-B) 16k| Normal
+0x80504800 |--------------------------| ------------
+ |TTB (L2 Peripherals-A) 16k| Normal
+0x80504400 |--------------------------| ------------
+ |TTB (L2 Priv Periphs) 4k | Normal
+0x80504000 |--------------------------| ------------
+ | TTB (L1 Descriptors) | Normal
+0x80500000 |--------------------------| ------------
+ | Heap | Normal
+ |--------------------------| ------------
+ | Stack | Normal
+0x80400000 |--------------------------| ------------
+ | ZI Data | Normal
+0x80300000 |--------------------------| ------------
+ | RW Data | Normal
+0x80200000 |--------------------------| ------------
+ | RO Data | Normal
+ |--------------------------| ------------
+ | RO Code | USH Normal
+0x80000000 |--------------------------| ------------
+ | Daughterboard | Fault
+ | HSB AXI buses |
+0x40000000 |--------------------------| ------------
+ | Daughterboard | Fault
+ | test chips peripherals |
+0x2c002000 |--------------------------| ------------
+ | Private Address | Device Memory
+0x2c000000 |--------------------------| ------------
+ | Daughterboard | Fault
+ | test chips peripherals |
+0x20000000 |--------------------------| ------------
+ | Peripherals | Device Memory RW/RO
+ | | & Fault
+0x00000000 |--------------------------|
+*/
+
+// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
+// Write-Through support *not* available
+// Write-Back support available.
+// Read allocation support available.
+// Write allocation support available.
+
+//Note: You should use the Shareable attribute carefully.
+//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
+//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
+//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
+
+//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
+//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
+//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
+
+
+//Following MMU configuration is expected
+//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
+//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
+//Domain 0 is always the Client domain
+//Descriptors should place all memory in domain 0
+
+#include "ARMCA5.h"
+
+
+// L2 table pointers
+//----------------------------------------
+#define PRIVATE_TABLE_L2_BASE_4k (0x80504000) //Map 4k Private Address space
+#define SYNC_FLAGS_TABLE_L2_BASE_4k (0x80504C00) //Map 4k Flag synchronization
+#define PERIPHERAL_A_TABLE_L2_BASE_64k (0x80504400) //Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF
+#define PERIPHERAL_B_TABLE_L2_BASE_64k (0x80504800) //Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF
+
+//--------------------- PERIPHERALS -------------------
+#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M)
+#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M)
+
+//--------------------- SYNC FLAGS --------------------
+#define FLAG_SYNC 0xFFFFF000
+#define F_SYNC_BASE 0xFFF00000 //1M aligned
+
+//Import symbols from linker
+extern uint32_t Image$$VECTORS$$Base;
+extern uint32_t Image$$RW_DATA$$Base;
+extern uint32_t Image$$ZI_DATA$$Base;
+extern uint32_t Image$$TTB$$ZI$$Base;
+
+static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
+static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
+static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable
+static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable
+static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0
+static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable
+
+/* Define global descriptors */
+static uint32_t Page_L1_4k = 0x0; //generic
+static uint32_t Page_L1_64k = 0x0; //generic
+static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0
+static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
+
+void MMU_CreateTranslationTable(void)
+{
+ mmu_region_attributes_Type region;
+
+ //Create 4GB of faulting entries
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
+
+ /*
+ * Generate descriptors. Refer to core_ca.h to get information about attributes
+ *
+ */
+ //Create descriptors for Vectors, RO, RW, ZI sections
+ section_normal(Sect_Normal, region);
+ section_normal_cod(Sect_Normal_Cod, region);
+ section_normal_ro(Sect_Normal_RO, region);
+ section_normal_rw(Sect_Normal_RW, region);
+ //Create descriptors for peripherals
+ section_device_ro(Sect_Device_RO, region);
+ section_device_rw(Sect_Device_RW, region);
+ //Create descriptors for 64k pages
+ page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
+ //Create descriptors for 4k pages
+ page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
+
+
+ /*
+ * Define MMU flat-map regions and attributes
+ *
+ */
+
+ //Define Image
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, 2, Sect_Normal_Cod);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, 1, Sect_Normal_RW);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base, 1, Sect_Normal_RW);
+
+ //all DRAM executable, rw, cacheable - applications may choose to divide memory into ro executable
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$TTB$$ZI$$Base, 2043, Sect_Normal);
+
+ //--------------------- PERIPHERALS -------------------
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_FLASH_BASE0 , 64, Sect_Device_RO);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_FLASH_BASE1 , 64, Sect_Device_RO);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_SRAM_BASE , 64, Sect_Device_RW);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_VRAM_BASE , 32, Sect_Device_RW);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_ETHERNET_BASE , 16, Sect_Device_RW);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_USB_BASE , 16, Sect_Device_RW);
+
+ // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_A_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
+ // Define peripheral range 0x1C000000-0x1C00FFFF
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_DAP_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_SYSTEM_REG_BASE, 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_SERIAL_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_AACI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_MMCI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_KMI0_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_UART_BASE , 4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_WDT_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+
+ // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_B_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
+ // Define peripheral range 0x1C100000-0x1C10FFFF
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_TIMER_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_DVI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_RTC_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_UART4_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_CLCD_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+
+ // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory
+ MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR() ,256, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
+ // Define private address space entry.
+ MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR() , 3, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+ // Define L2CC entry. Uncomment if PL310 is present
+ // MMU_TTPage4k (&Image$$TTB$$ZI$$Base, VE_A5_MP_PL310_BASE , 1, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+
+ // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)
+ MMU_TTPage4k (&Image$$TTB$$ZI$$Base, F_SYNC_BASE , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
+ // Define synchronization space entry.
+ MMU_TTPage4k (&Image$$TTB$$ZI$$Base, FLAG_SYNC , 1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+
+ /* Set location of level 1 page table
+ ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
+ ; 13:7 - 0x0
+ ; 6 - IRGN[0] 0x1 (Inner WB WA)
+ ; 5 - NOS 0x0 (Non-shared)
+ ; 4:3 - RGN 0x01 (Outer WB WA)
+ ; 2 - IMP 0x0 (Implementation Defined)
+ ; 1 - S 0x0 (Non-shared)
+ ; 0 - IRGN[1] 0x0 (Inner WB WA) */
+ __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 0x48);
+ __ISB();
+
+ /* Set up domain access control register
+ ; We set domain 0 to Client and all other domains to No Access.
+ ; All translation table entries specify domain 0 */
+ __set_DACR(1);
+ __ISB();
+}
diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/startup_ARMCA5.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/startup_ARMCA5.c new file mode 100644 index 0000000..19c343b --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/startup_ARMCA5.c @@ -0,0 +1,138 @@ +/******************************************************************************
+ * @file startup_ARMCA5.c
+ * @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series
+ * @version V1.00
+ * @date 10. January 2018
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ARMCA5.h>
+
+/*----------------------------------------------------------------------------
+ Definitions
+ *----------------------------------------------------------------------------*/
+#define USR_MODE 0x10 // User mode
+#define FIQ_MODE 0x11 // Fast Interrupt Request mode
+#define IRQ_MODE 0x12 // Interrupt Request mode
+#define SVC_MODE 0x13 // Supervisor mode
+#define ABT_MODE 0x17 // Abort mode
+#define UND_MODE 0x1B // Undefined Instruction mode
+#define SYS_MODE 0x1F // System mode
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Vectors (void) __attribute__ ((naked, section("RESET")));
+void Reset_Handler (void) __attribute__ ((naked));
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+void Vectors(void) {
+ __ASM volatile(
+ "LDR PC, =Reset_Handler \n"
+ "LDR PC, =Undef_Handler \n"
+ "LDR PC, =SVC_Handler \n"
+ "LDR PC, =PAbt_Handler \n"
+ "LDR PC, =DAbt_Handler \n"
+ "NOP \n"
+ "LDR PC, =IRQ_Handler \n"
+ "LDR PC, =FIQ_Handler \n"
+ );
+}
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+ __ASM volatile(
+
+ // Mask interrupts
+ "CPSID if \n"
+
+ // Put any cores other than 0 to sleep
+ "MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR
+ "ANDS R0, R0, #3 \n"
+ "goToSleep: \n"
+ "WFINE \n"
+ "BNE goToSleep \n"
+
+ // Reset SCTLR Settings
+ "MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register
+ "BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache
+ "BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache
+ "BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU
+ "BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction
+ "BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs
+ "MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register
+ "ISB \n"
+
+ // Configure ACTLR
+ "MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register
+ "ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1)
+ "MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register
+
+ // Set Vector Base Address Register (VBAR) to point to this application's vector table
+ "LDR R0, =Vectors \n"
+ "MCR p15, 0, R0, c12, c0, 0 \n"
+
+ // Setup Stack for each exceptional mode
+ "CPS #0x11 \n"
+ "LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n"
+ "CPS #0x12 \n"
+ "LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n"
+ "CPS #0x13 \n"
+ "LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n"
+ "CPS #0x17 \n"
+ "LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n"
+ "CPS #0x1B \n"
+ "LDR SP, =Image$$UND_STACK$$ZI$$Limit \n"
+ "CPS #0x1F \n"
+ "LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n"
+
+ // Call SystemInit
+ "BL SystemInit \n"
+
+ // Unmask interrupts
+ "CPSIE if \n"
+
+ // Call __main
+ "BL __main \n"
+ );
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+ while(1);
+}
diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/system_ARMCA5.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/system_ARMCA5.c new file mode 100644 index 0000000..cca3026 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/system_ARMCA5.c @@ -0,0 +1,93 @@ +/******************************************************************************
+ * @file system_ARMCA5.c
+ * @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series
+ * @version V1.0.1
+ * @date 13. February 2019
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+#include "irq_ctrl.h"
+
+#define SYSTEM_CLOCK 12000000U
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System Initialization
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+/* do not use global variables because this function is called before
+ reaching pre-main. RW section may be overwritten afterwards. */
+
+ // Invalidate entire Unified TLB
+ __set_TLBIALL(0);
+
+ // Invalidate entire branch predictor array
+ __set_BPIALL(0);
+ __DSB();
+ __ISB();
+
+ // Invalidate instruction cache and flush branch target cache
+ __set_ICIALLU(0);
+ __DSB();
+ __ISB();
+
+ // Invalidate data cache
+ L1C_InvalidateDCacheAll();
+
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+ // Enable FPU
+ __FPU_Enable();
+#endif
+
+ // Create Translation Table
+ MMU_CreateTranslationTable();
+
+ // Enable MMU
+ MMU_Enable();
+
+ // Enable Caches
+ L1C_EnableCaches();
+ L1C_EnableBTAC();
+
+#if (__L2C_PRESENT == 1)
+ // Enable GIC
+ L2C_Enable();
+#endif
+
+ // IRQ Initialize
+ IRQ_Initialize();
+}
diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/system_ARMCA5.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/system_ARMCA5.h new file mode 100644 index 0000000..4b61321 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/system_ARMCA5.h @@ -0,0 +1,65 @@ +/******************************************************************************
+ * @file system_ARMCA5.h
+ * @brief CMSIS Device System Header File for Arm Cortex-A5 Device Series
+ * @version V1.00
+ * @date 10. January 2018
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SYSTEM_ARMCA5_H
+#define __SYSTEM_ARMCA5_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ \brief Setup the microcontroller system.
+
+ Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+ \brief Update SystemCoreClock variable.
+
+ Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+ \brief Create Translation Table.
+
+ Creates Memory Management Unit Translation Table.
+ */
+extern void MMU_CreateTranslationTable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_ARMCA5_H */
diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/RTE_Components.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/RTE_Components.h new file mode 100644 index 0000000..ca6dcf3 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/RTE_Components.h @@ -0,0 +1,20 @@ +/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: DspLibTest_FVP_A5
+ * RTE configuration: DspLibTest_FVP_A5.rteconfig
+*/
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+/*
+ * Define the Device Header File:
+*/
+#define CMSIS_device_header "ARMCA5.h"
+
+#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */
+ #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */
+ #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/main.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/main.c new file mode 100644 index 0000000..a6b31da --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/main.c @@ -0,0 +1,34 @@ +/* --------------------------------------------------------------------------
+ * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ *---------------------------------------------------------------------------*/
+
+#include <stdio.h>
+
+#include "jtest.h"
+#include "all_tests.h"
+#include "arm_math.h"
+
+
+int main (void) {
+
+ JTEST_INIT(); /* Initialize test framework. */
+ JTEST_GROUP_CALL(all_tests); /* Run all tests. */
+ JTEST_ACT_EXIT_FW(); /* Exit test framework. */
+
+ while(1); /* Never return */
+}
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