diff options
| author | joshua <joshua@joshuayun.com> | 2023-12-30 23:54:31 -0500 |
|---|---|---|
| committer | joshua <joshua@joshuayun.com> | 2023-12-30 23:54:31 -0500 |
| commit | 86608c6770cf08c138a2bdab5855072f64be09ef (patch) | |
| tree | 494a61b3ef37e76f9235a0d10f5c93d97290a35f /Drivers/CMSIS/Device/ST/STM32H7xx/Source | |
| download | sdr-software-86608c6770cf08c138a2bdab5855072f64be09ef.tar.gz | |
Diffstat (limited to 'Drivers/CMSIS/Device/ST/STM32H7xx/Source')
217 files changed, 58859 insertions, 0 deletions
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h723xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h723xx.s new file mode 100644 index 0000000..d8b3b63 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h723xx.s @@ -0,0 +1,616 @@ +;********************************************************************************
+;* File Name : startup_stm32h723xx.s
+;* @author MCD Application Team
+;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it)
+ DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_PSSI_IRQHandler ; DCMI, PSSI
+ DCD 0 ; Reserved
+ DCD RNG_IRQHandler ; Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD 0 ; Reserved
+ DCD OCTOSPI1_IRQHandler ; OCTOSPI1
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD 0 ; Reserved
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD 0 ; Reserved
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD 0 ; Reserved
+ DCD ADC3_IRQHandler ; ADC3 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP1_IRQHandler ; COMP1 global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
+ DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD 0 ; Reserved
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
+ DCD SAI4_IRQHandler ; SAI4 global interrupt
+ DCD DTS_IRQHandler ; DTS interrupt
+ DCD 0 ; Reserved
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+ DCD OCTOSPI2_IRQHandler ; OCTOSPI2 Interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FMAC_IRQHandler ; FMAC Interrupt
+ DCD CORDIC_IRQHandler ; CORDIC Interrupt
+ DCD UART9_IRQHandler ; UART9 Interrupt
+ DCD USART10_IRQHandler ; UART10 Interrupt
+ DCD I2C5_EV_IRQHandler ; I2C5 Event Interrupt
+ DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt
+ DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0
+ DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1
+ DCD TIM23_IRQHandler ; TIM23 global interrupt
+ DCD TIM24_IRQHandler ; TIM24 global interrupt
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_AVD_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream0_IRQHandler [WEAK]
+ EXPORT DMA1_Stream1_IRQHandler [WEAK]
+ EXPORT DMA1_Stream2_IRQHandler [WEAK]
+ EXPORT DMA1_Stream3_IRQHandler [WEAK]
+ EXPORT DMA1_Stream4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream5_IRQHandler [WEAK]
+ EXPORT DMA1_Stream6_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT1_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT1_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
+ EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT SDMMC1_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Stream0_IRQHandler [WEAK]
+ EXPORT DMA2_Stream1_IRQHandler [WEAK]
+ EXPORT DMA2_Stream2_IRQHandler [WEAK]
+ EXPORT DMA2_Stream3_IRQHandler [WEAK]
+ EXPORT DMA2_Stream4_IRQHandler [WEAK]
+ EXPORT ETH_IRQHandler [WEAK]
+ EXPORT ETH_WKUP_IRQHandler [WEAK]
+ EXPORT FDCAN_CAL_IRQHandler [WEAK]
+ EXPORT DMA2_Stream5_IRQHandler [WEAK]
+ EXPORT DMA2_Stream6_IRQHandler [WEAK]
+ EXPORT DMA2_Stream7_IRQHandler [WEAK]
+ EXPORT USART6_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_HS_IRQHandler [WEAK]
+ EXPORT DCMI_PSSI_IRQHandler [WEAK]
+ EXPORT RNG_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT UART7_IRQHandler [WEAK]
+ EXPORT UART8_IRQHandler [WEAK]
+ EXPORT SPI4_IRQHandler [WEAK]
+ EXPORT SPI5_IRQHandler [WEAK]
+ EXPORT SPI6_IRQHandler [WEAK]
+ EXPORT SAI1_IRQHandler [WEAK]
+ EXPORT LTDC_IRQHandler [WEAK]
+ EXPORT LTDC_ER_IRQHandler [WEAK]
+ EXPORT DMA2D_IRQHandler [WEAK]
+ EXPORT OCTOSPI1_IRQHandler [WEAK]
+ EXPORT LPTIM1_IRQHandler [WEAK]
+ EXPORT CEC_IRQHandler [WEAK]
+ EXPORT I2C4_EV_IRQHandler [WEAK]
+ EXPORT I2C4_ER_IRQHandler [WEAK]
+ EXPORT SPDIF_RX_IRQHandler [WEAK]
+ EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
+ EXPORT SWPMI1_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT MDIOS_WKUP_IRQHandler [WEAK]
+ EXPORT MDIOS_IRQHandler [WEAK]
+ EXPORT MDMA_IRQHandler [WEAK]
+ EXPORT SDMMC2_IRQHandler [WEAK]
+ EXPORT HSEM1_IRQHandler [WEAK]
+ EXPORT ADC3_IRQHandler [WEAK]
+ EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
+ EXPORT BDMA_Channel0_IRQHandler [WEAK]
+ EXPORT BDMA_Channel1_IRQHandler [WEAK]
+ EXPORT BDMA_Channel2_IRQHandler [WEAK]
+ EXPORT BDMA_Channel3_IRQHandler [WEAK]
+ EXPORT BDMA_Channel4_IRQHandler [WEAK]
+ EXPORT BDMA_Channel5_IRQHandler [WEAK]
+ EXPORT BDMA_Channel6_IRQHandler [WEAK]
+ EXPORT BDMA_Channel7_IRQHandler [WEAK]
+ EXPORT COMP1_IRQHandler [WEAK]
+ EXPORT LPTIM2_IRQHandler [WEAK]
+ EXPORT LPTIM3_IRQHandler [WEAK]
+ EXPORT LPTIM4_IRQHandler [WEAK]
+ EXPORT LPTIM5_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT CRS_IRQHandler [WEAK]
+ EXPORT ECC_IRQHandler [WEAK]
+ EXPORT SAI4_IRQHandler [WEAK]
+ EXPORT DTS_IRQHandler [WEAK]
+ EXPORT WAKEUP_PIN_IRQHandler [WEAK]
+ EXPORT OCTOSPI2_IRQHandler [WEAK]
+ EXPORT FMAC_IRQHandler [WEAK]
+ EXPORT CORDIC_IRQHandler [WEAK]
+ EXPORT UART9_IRQHandler [WEAK]
+ EXPORT USART10_IRQHandler [WEAK]
+ EXPORT I2C5_EV_IRQHandler [WEAK]
+ EXPORT I2C5_ER_IRQHandler [WEAK]
+ EXPORT FDCAN3_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN3_IT1_IRQHandler [WEAK]
+ EXPORT TIM23_IRQHandler [WEAK]
+ EXPORT TIM24_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_AVD_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler
+DMA1_Stream2_IRQHandler
+DMA1_Stream3_IRQHandler
+DMA1_Stream4_IRQHandler
+DMA1_Stream5_IRQHandler
+DMA1_Stream6_IRQHandler
+ADC_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+FDCAN2_IT1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+TIM8_BRK_TIM12_IRQHandler
+TIM8_UP_TIM13_IRQHandler
+TIM8_TRG_COM_TIM14_IRQHandler
+TIM8_CC_IRQHandler
+DMA1_Stream7_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Stream0_IRQHandler
+DMA2_Stream1_IRQHandler
+DMA2_Stream2_IRQHandler
+DMA2_Stream3_IRQHandler
+DMA2_Stream4_IRQHandler
+ETH_IRQHandler
+ETH_WKUP_IRQHandler
+FDCAN_CAL_IRQHandler
+DMA2_Stream5_IRQHandler
+DMA2_Stream6_IRQHandler
+DMA2_Stream7_IRQHandler
+USART6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+OTG_HS_EP1_OUT_IRQHandler
+OTG_HS_EP1_IN_IRQHandler
+OTG_HS_WKUP_IRQHandler
+OTG_HS_IRQHandler
+DCMI_PSSI_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+SAI1_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+DMA2D_IRQHandler
+OCTOSPI1_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+DMAMUX1_OVR_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+DFSDM1_FLT3_IRQHandler
+SWPMI1_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+MDIOS_WKUP_IRQHandler
+MDIOS_IRQHandler
+MDMA_IRQHandler
+SDMMC2_IRQHandler
+HSEM1_IRQHandler
+ADC3_IRQHandler
+DMAMUX2_OVR_IRQHandler
+BDMA_Channel0_IRQHandler
+BDMA_Channel1_IRQHandler
+BDMA_Channel2_IRQHandler
+BDMA_Channel3_IRQHandler
+BDMA_Channel4_IRQHandler
+BDMA_Channel5_IRQHandler
+BDMA_Channel6_IRQHandler
+BDMA_Channel7_IRQHandler
+COMP1_IRQHandler
+LPTIM2_IRQHandler
+LPTIM3_IRQHandler
+LPTIM4_IRQHandler
+LPTIM5_IRQHandler
+LPUART1_IRQHandler
+CRS_IRQHandler
+ECC_IRQHandler
+SAI4_IRQHandler
+DTS_IRQHandler
+WAKEUP_PIN_IRQHandler
+OCTOSPI2_IRQHandler
+FMAC_IRQHandler
+CORDIC_IRQHandler
+UART9_IRQHandler
+USART10_IRQHandler
+I2C5_EV_IRQHandler
+I2C5_ER_IRQHandler
+FDCAN3_IT0_IRQHandler
+FDCAN3_IT1_IRQHandler
+TIM23_IRQHandler
+TIM24_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h725xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h725xx.s new file mode 100644 index 0000000..6f16b26 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h725xx.s @@ -0,0 +1,616 @@ +;********************************************************************************
+;* File Name : startup_stm32h725xx.s
+;* @author MCD Application Team
+;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it)
+ DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_PSSI_IRQHandler ; DCMI, PSSI
+ DCD 0 ; Reserved
+ DCD RNG_IRQHandler ; Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD 0 ; Reserved
+ DCD OCTOSPI1_IRQHandler ; OCTOSPI1
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD 0 ; Reserved
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD 0 ; Reserved
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD 0 ; Reserved
+ DCD ADC3_IRQHandler ; ADC3 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP1_IRQHandler ; COMP1 global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
+ DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD 0 ; Reserved
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
+ DCD SAI4_IRQHandler ; SAI4 global interrupt
+ DCD DTS_IRQHandler ; DTS interrupt
+ DCD 0 ; Reserved
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+ DCD OCTOSPI2_IRQHandler ; OCTOSPI2 Interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FMAC_IRQHandler ; FMAC Interrupt
+ DCD CORDIC_IRQHandler ; CORDIC Interrupt
+ DCD UART9_IRQHandler ; UART9 Interrupt
+ DCD USART10_IRQHandler ; UART10 Interrupt
+ DCD I2C5_EV_IRQHandler ; I2C5 Event Interrupt
+ DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt
+ DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0
+ DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1
+ DCD TIM23_IRQHandler ; TIM23 global interrupt
+ DCD TIM24_IRQHandler ; TIM24 global interrupt
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_AVD_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream0_IRQHandler [WEAK]
+ EXPORT DMA1_Stream1_IRQHandler [WEAK]
+ EXPORT DMA1_Stream2_IRQHandler [WEAK]
+ EXPORT DMA1_Stream3_IRQHandler [WEAK]
+ EXPORT DMA1_Stream4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream5_IRQHandler [WEAK]
+ EXPORT DMA1_Stream6_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT1_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT1_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
+ EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT SDMMC1_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Stream0_IRQHandler [WEAK]
+ EXPORT DMA2_Stream1_IRQHandler [WEAK]
+ EXPORT DMA2_Stream2_IRQHandler [WEAK]
+ EXPORT DMA2_Stream3_IRQHandler [WEAK]
+ EXPORT DMA2_Stream4_IRQHandler [WEAK]
+ EXPORT ETH_IRQHandler [WEAK]
+ EXPORT ETH_WKUP_IRQHandler [WEAK]
+ EXPORT FDCAN_CAL_IRQHandler [WEAK]
+ EXPORT DMA2_Stream5_IRQHandler [WEAK]
+ EXPORT DMA2_Stream6_IRQHandler [WEAK]
+ EXPORT DMA2_Stream7_IRQHandler [WEAK]
+ EXPORT USART6_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_HS_IRQHandler [WEAK]
+ EXPORT DCMI_PSSI_IRQHandler [WEAK]
+ EXPORT RNG_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT UART7_IRQHandler [WEAK]
+ EXPORT UART8_IRQHandler [WEAK]
+ EXPORT SPI4_IRQHandler [WEAK]
+ EXPORT SPI5_IRQHandler [WEAK]
+ EXPORT SPI6_IRQHandler [WEAK]
+ EXPORT SAI1_IRQHandler [WEAK]
+ EXPORT LTDC_IRQHandler [WEAK]
+ EXPORT LTDC_ER_IRQHandler [WEAK]
+ EXPORT DMA2D_IRQHandler [WEAK]
+ EXPORT OCTOSPI1_IRQHandler [WEAK]
+ EXPORT LPTIM1_IRQHandler [WEAK]
+ EXPORT CEC_IRQHandler [WEAK]
+ EXPORT I2C4_EV_IRQHandler [WEAK]
+ EXPORT I2C4_ER_IRQHandler [WEAK]
+ EXPORT SPDIF_RX_IRQHandler [WEAK]
+ EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
+ EXPORT SWPMI1_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT MDIOS_WKUP_IRQHandler [WEAK]
+ EXPORT MDIOS_IRQHandler [WEAK]
+ EXPORT MDMA_IRQHandler [WEAK]
+ EXPORT SDMMC2_IRQHandler [WEAK]
+ EXPORT HSEM1_IRQHandler [WEAK]
+ EXPORT ADC3_IRQHandler [WEAK]
+ EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
+ EXPORT BDMA_Channel0_IRQHandler [WEAK]
+ EXPORT BDMA_Channel1_IRQHandler [WEAK]
+ EXPORT BDMA_Channel2_IRQHandler [WEAK]
+ EXPORT BDMA_Channel3_IRQHandler [WEAK]
+ EXPORT BDMA_Channel4_IRQHandler [WEAK]
+ EXPORT BDMA_Channel5_IRQHandler [WEAK]
+ EXPORT BDMA_Channel6_IRQHandler [WEAK]
+ EXPORT BDMA_Channel7_IRQHandler [WEAK]
+ EXPORT COMP1_IRQHandler [WEAK]
+ EXPORT LPTIM2_IRQHandler [WEAK]
+ EXPORT LPTIM3_IRQHandler [WEAK]
+ EXPORT LPTIM4_IRQHandler [WEAK]
+ EXPORT LPTIM5_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT CRS_IRQHandler [WEAK]
+ EXPORT ECC_IRQHandler [WEAK]
+ EXPORT SAI4_IRQHandler [WEAK]
+ EXPORT DTS_IRQHandler [WEAK]
+ EXPORT WAKEUP_PIN_IRQHandler [WEAK]
+ EXPORT OCTOSPI2_IRQHandler [WEAK]
+ EXPORT FMAC_IRQHandler [WEAK]
+ EXPORT CORDIC_IRQHandler [WEAK]
+ EXPORT UART9_IRQHandler [WEAK]
+ EXPORT USART10_IRQHandler [WEAK]
+ EXPORT I2C5_EV_IRQHandler [WEAK]
+ EXPORT I2C5_ER_IRQHandler [WEAK]
+ EXPORT FDCAN3_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN3_IT1_IRQHandler [WEAK]
+ EXPORT TIM23_IRQHandler [WEAK]
+ EXPORT TIM24_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_AVD_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler
+DMA1_Stream2_IRQHandler
+DMA1_Stream3_IRQHandler
+DMA1_Stream4_IRQHandler
+DMA1_Stream5_IRQHandler
+DMA1_Stream6_IRQHandler
+ADC_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+FDCAN2_IT1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+TIM8_BRK_TIM12_IRQHandler
+TIM8_UP_TIM13_IRQHandler
+TIM8_TRG_COM_TIM14_IRQHandler
+TIM8_CC_IRQHandler
+DMA1_Stream7_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Stream0_IRQHandler
+DMA2_Stream1_IRQHandler
+DMA2_Stream2_IRQHandler
+DMA2_Stream3_IRQHandler
+DMA2_Stream4_IRQHandler
+ETH_IRQHandler
+ETH_WKUP_IRQHandler
+FDCAN_CAL_IRQHandler
+DMA2_Stream5_IRQHandler
+DMA2_Stream6_IRQHandler
+DMA2_Stream7_IRQHandler
+USART6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+OTG_HS_EP1_OUT_IRQHandler
+OTG_HS_EP1_IN_IRQHandler
+OTG_HS_WKUP_IRQHandler
+OTG_HS_IRQHandler
+DCMI_PSSI_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+SAI1_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+DMA2D_IRQHandler
+OCTOSPI1_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+DMAMUX1_OVR_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+DFSDM1_FLT3_IRQHandler
+SWPMI1_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+MDIOS_WKUP_IRQHandler
+MDIOS_IRQHandler
+MDMA_IRQHandler
+SDMMC2_IRQHandler
+HSEM1_IRQHandler
+ADC3_IRQHandler
+DMAMUX2_OVR_IRQHandler
+BDMA_Channel0_IRQHandler
+BDMA_Channel1_IRQHandler
+BDMA_Channel2_IRQHandler
+BDMA_Channel3_IRQHandler
+BDMA_Channel4_IRQHandler
+BDMA_Channel5_IRQHandler
+BDMA_Channel6_IRQHandler
+BDMA_Channel7_IRQHandler
+COMP1_IRQHandler
+LPTIM2_IRQHandler
+LPTIM3_IRQHandler
+LPTIM4_IRQHandler
+LPTIM5_IRQHandler
+LPUART1_IRQHandler
+CRS_IRQHandler
+ECC_IRQHandler
+SAI4_IRQHandler
+DTS_IRQHandler
+WAKEUP_PIN_IRQHandler
+OCTOSPI2_IRQHandler
+FMAC_IRQHandler
+CORDIC_IRQHandler
+UART9_IRQHandler
+USART10_IRQHandler
+I2C5_EV_IRQHandler
+I2C5_ER_IRQHandler
+FDCAN3_IT0_IRQHandler
+FDCAN3_IT1_IRQHandler
+TIM23_IRQHandler
+TIM24_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h730xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h730xx.s new file mode 100644 index 0000000..dbd497e --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h730xx.s @@ -0,0 +1,622 @@ +;********************************************************************************
+;* File Name : startup_stm32h730xx.s
+;* @author MCD Application Team
+;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it)
+ DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_PSSI_IRQHandler ; DCMI, PSSI
+ DCD CRYP_IRQHandler ; CRYP
+ DCD HASH_RNG_IRQHandler ; Hash and Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD 0 ; Reserved
+ DCD OCTOSPI1_IRQHandler ; OCTOSPI1
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD 0 ; Reserved
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD 0 ; Reserved
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD 0 ; Reserved
+ DCD ADC3_IRQHandler ; ADC3 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP1_IRQHandler ; COMP1 global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
+ DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD 0 ; Reserved
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
+ DCD SAI4_IRQHandler ; SAI4 global interrupt
+ DCD DTS_IRQHandler ; DTS interrupt
+ DCD 0 ; Reserved
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+ DCD OCTOSPI2_IRQHandler ; OCTOSPI2 Interrupt
+ DCD OTFDEC1_IRQHandler ; OTFDEC1 Interrupt
+ DCD OTFDEC2_IRQHandler ; OTFDEC2 Interrupt
+ DCD FMAC_IRQHandler ; FMAC Interrupt
+ DCD CORDIC_IRQHandler ; CORDIC Interrupt
+ DCD UART9_IRQHandler ; UART9 Interrupt
+ DCD USART10_IRQHandler ; UART10 Interrupt
+ DCD I2C5_EV_IRQHandler ; I2C5 Event Interrupt
+ DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt
+ DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0
+ DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1
+ DCD TIM23_IRQHandler ; TIM23 global interrupt
+ DCD TIM24_IRQHandler ; TIM24 global interrupt
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_AVD_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream0_IRQHandler [WEAK]
+ EXPORT DMA1_Stream1_IRQHandler [WEAK]
+ EXPORT DMA1_Stream2_IRQHandler [WEAK]
+ EXPORT DMA1_Stream3_IRQHandler [WEAK]
+ EXPORT DMA1_Stream4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream5_IRQHandler [WEAK]
+ EXPORT DMA1_Stream6_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT1_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT1_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
+ EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT SDMMC1_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Stream0_IRQHandler [WEAK]
+ EXPORT DMA2_Stream1_IRQHandler [WEAK]
+ EXPORT DMA2_Stream2_IRQHandler [WEAK]
+ EXPORT DMA2_Stream3_IRQHandler [WEAK]
+ EXPORT DMA2_Stream4_IRQHandler [WEAK]
+ EXPORT ETH_IRQHandler [WEAK]
+ EXPORT ETH_WKUP_IRQHandler [WEAK]
+ EXPORT FDCAN_CAL_IRQHandler [WEAK]
+ EXPORT DMA2_Stream5_IRQHandler [WEAK]
+ EXPORT DMA2_Stream6_IRQHandler [WEAK]
+ EXPORT DMA2_Stream7_IRQHandler [WEAK]
+ EXPORT USART6_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_HS_IRQHandler [WEAK]
+ EXPORT DCMI_PSSI_IRQHandler [WEAK]
+ EXPORT CRYP_IRQHandler [WEAK]
+ EXPORT HASH_RNG_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT UART7_IRQHandler [WEAK]
+ EXPORT UART8_IRQHandler [WEAK]
+ EXPORT SPI4_IRQHandler [WEAK]
+ EXPORT SPI5_IRQHandler [WEAK]
+ EXPORT SPI6_IRQHandler [WEAK]
+ EXPORT SAI1_IRQHandler [WEAK]
+ EXPORT LTDC_IRQHandler [WEAK]
+ EXPORT LTDC_ER_IRQHandler [WEAK]
+ EXPORT DMA2D_IRQHandler [WEAK]
+ EXPORT OCTOSPI1_IRQHandler [WEAK]
+ EXPORT LPTIM1_IRQHandler [WEAK]
+ EXPORT CEC_IRQHandler [WEAK]
+ EXPORT I2C4_EV_IRQHandler [WEAK]
+ EXPORT I2C4_ER_IRQHandler [WEAK]
+ EXPORT SPDIF_RX_IRQHandler [WEAK]
+ EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
+ EXPORT SWPMI1_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT MDIOS_WKUP_IRQHandler [WEAK]
+ EXPORT MDIOS_IRQHandler [WEAK]
+ EXPORT MDMA_IRQHandler [WEAK]
+ EXPORT SDMMC2_IRQHandler [WEAK]
+ EXPORT HSEM1_IRQHandler [WEAK]
+ EXPORT ADC3_IRQHandler [WEAK]
+ EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
+ EXPORT BDMA_Channel0_IRQHandler [WEAK]
+ EXPORT BDMA_Channel1_IRQHandler [WEAK]
+ EXPORT BDMA_Channel2_IRQHandler [WEAK]
+ EXPORT BDMA_Channel3_IRQHandler [WEAK]
+ EXPORT BDMA_Channel4_IRQHandler [WEAK]
+ EXPORT BDMA_Channel5_IRQHandler [WEAK]
+ EXPORT BDMA_Channel6_IRQHandler [WEAK]
+ EXPORT BDMA_Channel7_IRQHandler [WEAK]
+ EXPORT COMP1_IRQHandler [WEAK]
+ EXPORT LPTIM2_IRQHandler [WEAK]
+ EXPORT LPTIM3_IRQHandler [WEAK]
+ EXPORT LPTIM4_IRQHandler [WEAK]
+ EXPORT LPTIM5_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT CRS_IRQHandler [WEAK]
+ EXPORT ECC_IRQHandler [WEAK]
+ EXPORT SAI4_IRQHandler [WEAK]
+ EXPORT DTS_IRQHandler [WEAK]
+ EXPORT WAKEUP_PIN_IRQHandler [WEAK]
+ EXPORT OCTOSPI2_IRQHandler [WEAK]
+ EXPORT OTFDEC1_IRQHandler [WEAK]
+ EXPORT OTFDEC2_IRQHandler [WEAK]
+ EXPORT FMAC_IRQHandler [WEAK]
+ EXPORT CORDIC_IRQHandler [WEAK]
+ EXPORT UART9_IRQHandler [WEAK]
+ EXPORT USART10_IRQHandler [WEAK]
+ EXPORT I2C5_EV_IRQHandler [WEAK]
+ EXPORT I2C5_ER_IRQHandler [WEAK]
+ EXPORT FDCAN3_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN3_IT1_IRQHandler [WEAK]
+ EXPORT TIM23_IRQHandler [WEAK]
+ EXPORT TIM24_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_AVD_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler
+DMA1_Stream2_IRQHandler
+DMA1_Stream3_IRQHandler
+DMA1_Stream4_IRQHandler
+DMA1_Stream5_IRQHandler
+DMA1_Stream6_IRQHandler
+ADC_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+FDCAN2_IT1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+TIM8_BRK_TIM12_IRQHandler
+TIM8_UP_TIM13_IRQHandler
+TIM8_TRG_COM_TIM14_IRQHandler
+TIM8_CC_IRQHandler
+DMA1_Stream7_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Stream0_IRQHandler
+DMA2_Stream1_IRQHandler
+DMA2_Stream2_IRQHandler
+DMA2_Stream3_IRQHandler
+DMA2_Stream4_IRQHandler
+ETH_IRQHandler
+ETH_WKUP_IRQHandler
+FDCAN_CAL_IRQHandler
+DMA2_Stream5_IRQHandler
+DMA2_Stream6_IRQHandler
+DMA2_Stream7_IRQHandler
+USART6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+OTG_HS_EP1_OUT_IRQHandler
+OTG_HS_EP1_IN_IRQHandler
+OTG_HS_WKUP_IRQHandler
+OTG_HS_IRQHandler
+DCMI_PSSI_IRQHandler
+CRYP_IRQHandler
+HASH_RNG_IRQHandler
+FPU_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+SAI1_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+DMA2D_IRQHandler
+OCTOSPI1_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+DMAMUX1_OVR_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+DFSDM1_FLT3_IRQHandler
+SWPMI1_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+MDIOS_WKUP_IRQHandler
+MDIOS_IRQHandler
+MDMA_IRQHandler
+SDMMC2_IRQHandler
+HSEM1_IRQHandler
+ADC3_IRQHandler
+DMAMUX2_OVR_IRQHandler
+BDMA_Channel0_IRQHandler
+BDMA_Channel1_IRQHandler
+BDMA_Channel2_IRQHandler
+BDMA_Channel3_IRQHandler
+BDMA_Channel4_IRQHandler
+BDMA_Channel5_IRQHandler
+BDMA_Channel6_IRQHandler
+BDMA_Channel7_IRQHandler
+COMP1_IRQHandler
+LPTIM2_IRQHandler
+LPTIM3_IRQHandler
+LPTIM4_IRQHandler
+LPTIM5_IRQHandler
+LPUART1_IRQHandler
+CRS_IRQHandler
+ECC_IRQHandler
+SAI4_IRQHandler
+DTS_IRQHandler
+WAKEUP_PIN_IRQHandler
+OCTOSPI2_IRQHandler
+OTFDEC1_IRQHandler
+OTFDEC2_IRQHandler
+FMAC_IRQHandler
+CORDIC_IRQHandler
+UART9_IRQHandler
+USART10_IRQHandler
+I2C5_EV_IRQHandler
+I2C5_ER_IRQHandler
+FDCAN3_IT0_IRQHandler
+FDCAN3_IT1_IRQHandler
+TIM23_IRQHandler
+TIM24_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h730xxq.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h730xxq.s new file mode 100644 index 0000000..15c2981 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h730xxq.s @@ -0,0 +1,622 @@ +;********************************************************************************
+;* File Name : startup_stm32h730xxq.s
+;* @author MCD Application Team
+;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it)
+ DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_PSSI_IRQHandler ; DCMI, PSSI
+ DCD CRYP_IRQHandler ; CRYP
+ DCD HASH_RNG_IRQHandler ; Hash and Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD 0 ; Reserved
+ DCD OCTOSPI1_IRQHandler ; OCTOSPI1
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD 0 ; Reserved
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD 0 ; Reserved
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD 0 ; Reserved
+ DCD ADC3_IRQHandler ; ADC3 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP1_IRQHandler ; COMP1 global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
+ DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD 0 ; Reserved
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
+ DCD SAI4_IRQHandler ; SAI4 global interrupt
+ DCD DTS_IRQHandler ; DTS interrupt
+ DCD 0 ; Reserved
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+ DCD OCTOSPI2_IRQHandler ; OCTOSPI2 Interrupt
+ DCD OTFDEC1_IRQHandler ; OTFDEC1 Interrupt
+ DCD OTFDEC2_IRQHandler ; OTFDEC2 Interrupt
+ DCD FMAC_IRQHandler ; FMAC Interrupt
+ DCD CORDIC_IRQHandler ; CORDIC Interrupt
+ DCD UART9_IRQHandler ; UART9 Interrupt
+ DCD USART10_IRQHandler ; UART10 Interrupt
+ DCD I2C5_EV_IRQHandler ; I2C5 Event Interrupt
+ DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt
+ DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0
+ DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1
+ DCD TIM23_IRQHandler ; TIM23 global interrupt
+ DCD TIM24_IRQHandler ; TIM24 global interrupt
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_AVD_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream0_IRQHandler [WEAK]
+ EXPORT DMA1_Stream1_IRQHandler [WEAK]
+ EXPORT DMA1_Stream2_IRQHandler [WEAK]
+ EXPORT DMA1_Stream3_IRQHandler [WEAK]
+ EXPORT DMA1_Stream4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream5_IRQHandler [WEAK]
+ EXPORT DMA1_Stream6_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT1_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT1_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
+ EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT SDMMC1_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Stream0_IRQHandler [WEAK]
+ EXPORT DMA2_Stream1_IRQHandler [WEAK]
+ EXPORT DMA2_Stream2_IRQHandler [WEAK]
+ EXPORT DMA2_Stream3_IRQHandler [WEAK]
+ EXPORT DMA2_Stream4_IRQHandler [WEAK]
+ EXPORT ETH_IRQHandler [WEAK]
+ EXPORT ETH_WKUP_IRQHandler [WEAK]
+ EXPORT FDCAN_CAL_IRQHandler [WEAK]
+ EXPORT DMA2_Stream5_IRQHandler [WEAK]
+ EXPORT DMA2_Stream6_IRQHandler [WEAK]
+ EXPORT DMA2_Stream7_IRQHandler [WEAK]
+ EXPORT USART6_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_HS_IRQHandler [WEAK]
+ EXPORT DCMI_PSSI_IRQHandler [WEAK]
+ EXPORT CRYP_IRQHandler [WEAK]
+ EXPORT HASH_RNG_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT UART7_IRQHandler [WEAK]
+ EXPORT UART8_IRQHandler [WEAK]
+ EXPORT SPI4_IRQHandler [WEAK]
+ EXPORT SPI5_IRQHandler [WEAK]
+ EXPORT SPI6_IRQHandler [WEAK]
+ EXPORT SAI1_IRQHandler [WEAK]
+ EXPORT LTDC_IRQHandler [WEAK]
+ EXPORT LTDC_ER_IRQHandler [WEAK]
+ EXPORT DMA2D_IRQHandler [WEAK]
+ EXPORT OCTOSPI1_IRQHandler [WEAK]
+ EXPORT LPTIM1_IRQHandler [WEAK]
+ EXPORT CEC_IRQHandler [WEAK]
+ EXPORT I2C4_EV_IRQHandler [WEAK]
+ EXPORT I2C4_ER_IRQHandler [WEAK]
+ EXPORT SPDIF_RX_IRQHandler [WEAK]
+ EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
+ EXPORT SWPMI1_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT MDIOS_WKUP_IRQHandler [WEAK]
+ EXPORT MDIOS_IRQHandler [WEAK]
+ EXPORT MDMA_IRQHandler [WEAK]
+ EXPORT SDMMC2_IRQHandler [WEAK]
+ EXPORT HSEM1_IRQHandler [WEAK]
+ EXPORT ADC3_IRQHandler [WEAK]
+ EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
+ EXPORT BDMA_Channel0_IRQHandler [WEAK]
+ EXPORT BDMA_Channel1_IRQHandler [WEAK]
+ EXPORT BDMA_Channel2_IRQHandler [WEAK]
+ EXPORT BDMA_Channel3_IRQHandler [WEAK]
+ EXPORT BDMA_Channel4_IRQHandler [WEAK]
+ EXPORT BDMA_Channel5_IRQHandler [WEAK]
+ EXPORT BDMA_Channel6_IRQHandler [WEAK]
+ EXPORT BDMA_Channel7_IRQHandler [WEAK]
+ EXPORT COMP1_IRQHandler [WEAK]
+ EXPORT LPTIM2_IRQHandler [WEAK]
+ EXPORT LPTIM3_IRQHandler [WEAK]
+ EXPORT LPTIM4_IRQHandler [WEAK]
+ EXPORT LPTIM5_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT CRS_IRQHandler [WEAK]
+ EXPORT ECC_IRQHandler [WEAK]
+ EXPORT SAI4_IRQHandler [WEAK]
+ EXPORT DTS_IRQHandler [WEAK]
+ EXPORT WAKEUP_PIN_IRQHandler [WEAK]
+ EXPORT OCTOSPI2_IRQHandler [WEAK]
+ EXPORT OTFDEC1_IRQHandler [WEAK]
+ EXPORT OTFDEC2_IRQHandler [WEAK]
+ EXPORT FMAC_IRQHandler [WEAK]
+ EXPORT CORDIC_IRQHandler [WEAK]
+ EXPORT UART9_IRQHandler [WEAK]
+ EXPORT USART10_IRQHandler [WEAK]
+ EXPORT I2C5_EV_IRQHandler [WEAK]
+ EXPORT I2C5_ER_IRQHandler [WEAK]
+ EXPORT FDCAN3_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN3_IT1_IRQHandler [WEAK]
+ EXPORT TIM23_IRQHandler [WEAK]
+ EXPORT TIM24_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_AVD_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler
+DMA1_Stream2_IRQHandler
+DMA1_Stream3_IRQHandler
+DMA1_Stream4_IRQHandler
+DMA1_Stream5_IRQHandler
+DMA1_Stream6_IRQHandler
+ADC_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+FDCAN2_IT1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+TIM8_BRK_TIM12_IRQHandler
+TIM8_UP_TIM13_IRQHandler
+TIM8_TRG_COM_TIM14_IRQHandler
+TIM8_CC_IRQHandler
+DMA1_Stream7_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Stream0_IRQHandler
+DMA2_Stream1_IRQHandler
+DMA2_Stream2_IRQHandler
+DMA2_Stream3_IRQHandler
+DMA2_Stream4_IRQHandler
+ETH_IRQHandler
+ETH_WKUP_IRQHandler
+FDCAN_CAL_IRQHandler
+DMA2_Stream5_IRQHandler
+DMA2_Stream6_IRQHandler
+DMA2_Stream7_IRQHandler
+USART6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+OTG_HS_EP1_OUT_IRQHandler
+OTG_HS_EP1_IN_IRQHandler
+OTG_HS_WKUP_IRQHandler
+OTG_HS_IRQHandler
+DCMI_PSSI_IRQHandler
+CRYP_IRQHandler
+HASH_RNG_IRQHandler
+FPU_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+SAI1_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+DMA2D_IRQHandler
+OCTOSPI1_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+DMAMUX1_OVR_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+DFSDM1_FLT3_IRQHandler
+SWPMI1_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+MDIOS_WKUP_IRQHandler
+MDIOS_IRQHandler
+MDMA_IRQHandler
+SDMMC2_IRQHandler
+HSEM1_IRQHandler
+ADC3_IRQHandler
+DMAMUX2_OVR_IRQHandler
+BDMA_Channel0_IRQHandler
+BDMA_Channel1_IRQHandler
+BDMA_Channel2_IRQHandler
+BDMA_Channel3_IRQHandler
+BDMA_Channel4_IRQHandler
+BDMA_Channel5_IRQHandler
+BDMA_Channel6_IRQHandler
+BDMA_Channel7_IRQHandler
+COMP1_IRQHandler
+LPTIM2_IRQHandler
+LPTIM3_IRQHandler
+LPTIM4_IRQHandler
+LPTIM5_IRQHandler
+LPUART1_IRQHandler
+CRS_IRQHandler
+ECC_IRQHandler
+SAI4_IRQHandler
+DTS_IRQHandler
+WAKEUP_PIN_IRQHandler
+OCTOSPI2_IRQHandler
+OTFDEC1_IRQHandler
+OTFDEC2_IRQHandler
+FMAC_IRQHandler
+CORDIC_IRQHandler
+UART9_IRQHandler
+USART10_IRQHandler
+I2C5_EV_IRQHandler
+I2C5_ER_IRQHandler
+FDCAN3_IT0_IRQHandler
+FDCAN3_IT1_IRQHandler
+TIM23_IRQHandler
+TIM24_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h733xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h733xx.s new file mode 100644 index 0000000..fd4f140 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h733xx.s @@ -0,0 +1,622 @@ +;********************************************************************************
+;* File Name : startup_stm32h733xx.s
+;* @author MCD Application Team
+;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it)
+ DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_PSSI_IRQHandler ; DCMI, PSSI
+ DCD CRYP_IRQHandler ; CRYP
+ DCD HASH_RNG_IRQHandler ; Hash and Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD 0 ; Reserved
+ DCD OCTOSPI1_IRQHandler ; OCTOSPI1
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD 0 ; Reserved
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD 0 ; Reserved
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD 0 ; Reserved
+ DCD ADC3_IRQHandler ; ADC3 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP1_IRQHandler ; COMP1 global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
+ DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD 0 ; Reserved
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
+ DCD SAI4_IRQHandler ; SAI4 global interrupt
+ DCD DTS_IRQHandler ; DTS interrupt
+ DCD 0 ; Reserved
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+ DCD OCTOSPI2_IRQHandler ; OCTOSPI2 Interrupt
+ DCD OTFDEC1_IRQHandler ; OTFDEC1 Interrupt
+ DCD OTFDEC2_IRQHandler ; OTFDEC2 Interrupt
+ DCD FMAC_IRQHandler ; FMAC Interrupt
+ DCD CORDIC_IRQHandler ; CORDIC Interrupt
+ DCD UART9_IRQHandler ; UART9 Interrupt
+ DCD USART10_IRQHandler ; UART10 Interrupt
+ DCD I2C5_EV_IRQHandler ; I2C5 Event Interrupt
+ DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt
+ DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0
+ DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1
+ DCD TIM23_IRQHandler ; TIM23 global interrupt
+ DCD TIM24_IRQHandler ; TIM24 global interrupt
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_AVD_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream0_IRQHandler [WEAK]
+ EXPORT DMA1_Stream1_IRQHandler [WEAK]
+ EXPORT DMA1_Stream2_IRQHandler [WEAK]
+ EXPORT DMA1_Stream3_IRQHandler [WEAK]
+ EXPORT DMA1_Stream4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream5_IRQHandler [WEAK]
+ EXPORT DMA1_Stream6_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT1_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT1_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
+ EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT SDMMC1_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Stream0_IRQHandler [WEAK]
+ EXPORT DMA2_Stream1_IRQHandler [WEAK]
+ EXPORT DMA2_Stream2_IRQHandler [WEAK]
+ EXPORT DMA2_Stream3_IRQHandler [WEAK]
+ EXPORT DMA2_Stream4_IRQHandler [WEAK]
+ EXPORT ETH_IRQHandler [WEAK]
+ EXPORT ETH_WKUP_IRQHandler [WEAK]
+ EXPORT FDCAN_CAL_IRQHandler [WEAK]
+ EXPORT DMA2_Stream5_IRQHandler [WEAK]
+ EXPORT DMA2_Stream6_IRQHandler [WEAK]
+ EXPORT DMA2_Stream7_IRQHandler [WEAK]
+ EXPORT USART6_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_HS_IRQHandler [WEAK]
+ EXPORT DCMI_PSSI_IRQHandler [WEAK]
+ EXPORT CRYP_IRQHandler [WEAK]
+ EXPORT HASH_RNG_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT UART7_IRQHandler [WEAK]
+ EXPORT UART8_IRQHandler [WEAK]
+ EXPORT SPI4_IRQHandler [WEAK]
+ EXPORT SPI5_IRQHandler [WEAK]
+ EXPORT SPI6_IRQHandler [WEAK]
+ EXPORT SAI1_IRQHandler [WEAK]
+ EXPORT LTDC_IRQHandler [WEAK]
+ EXPORT LTDC_ER_IRQHandler [WEAK]
+ EXPORT DMA2D_IRQHandler [WEAK]
+ EXPORT OCTOSPI1_IRQHandler [WEAK]
+ EXPORT LPTIM1_IRQHandler [WEAK]
+ EXPORT CEC_IRQHandler [WEAK]
+ EXPORT I2C4_EV_IRQHandler [WEAK]
+ EXPORT I2C4_ER_IRQHandler [WEAK]
+ EXPORT SPDIF_RX_IRQHandler [WEAK]
+ EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
+ EXPORT SWPMI1_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT MDIOS_WKUP_IRQHandler [WEAK]
+ EXPORT MDIOS_IRQHandler [WEAK]
+ EXPORT MDMA_IRQHandler [WEAK]
+ EXPORT SDMMC2_IRQHandler [WEAK]
+ EXPORT HSEM1_IRQHandler [WEAK]
+ EXPORT ADC3_IRQHandler [WEAK]
+ EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
+ EXPORT BDMA_Channel0_IRQHandler [WEAK]
+ EXPORT BDMA_Channel1_IRQHandler [WEAK]
+ EXPORT BDMA_Channel2_IRQHandler [WEAK]
+ EXPORT BDMA_Channel3_IRQHandler [WEAK]
+ EXPORT BDMA_Channel4_IRQHandler [WEAK]
+ EXPORT BDMA_Channel5_IRQHandler [WEAK]
+ EXPORT BDMA_Channel6_IRQHandler [WEAK]
+ EXPORT BDMA_Channel7_IRQHandler [WEAK]
+ EXPORT COMP1_IRQHandler [WEAK]
+ EXPORT LPTIM2_IRQHandler [WEAK]
+ EXPORT LPTIM3_IRQHandler [WEAK]
+ EXPORT LPTIM4_IRQHandler [WEAK]
+ EXPORT LPTIM5_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT CRS_IRQHandler [WEAK]
+ EXPORT ECC_IRQHandler [WEAK]
+ EXPORT SAI4_IRQHandler [WEAK]
+ EXPORT DTS_IRQHandler [WEAK]
+ EXPORT WAKEUP_PIN_IRQHandler [WEAK]
+ EXPORT OCTOSPI2_IRQHandler [WEAK]
+ EXPORT OTFDEC1_IRQHandler [WEAK]
+ EXPORT OTFDEC2_IRQHandler [WEAK]
+ EXPORT FMAC_IRQHandler [WEAK]
+ EXPORT CORDIC_IRQHandler [WEAK]
+ EXPORT UART9_IRQHandler [WEAK]
+ EXPORT USART10_IRQHandler [WEAK]
+ EXPORT I2C5_EV_IRQHandler [WEAK]
+ EXPORT I2C5_ER_IRQHandler [WEAK]
+ EXPORT FDCAN3_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN3_IT1_IRQHandler [WEAK]
+ EXPORT TIM23_IRQHandler [WEAK]
+ EXPORT TIM24_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_AVD_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler
+DMA1_Stream2_IRQHandler
+DMA1_Stream3_IRQHandler
+DMA1_Stream4_IRQHandler
+DMA1_Stream5_IRQHandler
+DMA1_Stream6_IRQHandler
+ADC_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+FDCAN2_IT1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+TIM8_BRK_TIM12_IRQHandler
+TIM8_UP_TIM13_IRQHandler
+TIM8_TRG_COM_TIM14_IRQHandler
+TIM8_CC_IRQHandler
+DMA1_Stream7_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Stream0_IRQHandler
+DMA2_Stream1_IRQHandler
+DMA2_Stream2_IRQHandler
+DMA2_Stream3_IRQHandler
+DMA2_Stream4_IRQHandler
+ETH_IRQHandler
+ETH_WKUP_IRQHandler
+FDCAN_CAL_IRQHandler
+DMA2_Stream5_IRQHandler
+DMA2_Stream6_IRQHandler
+DMA2_Stream7_IRQHandler
+USART6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+OTG_HS_EP1_OUT_IRQHandler
+OTG_HS_EP1_IN_IRQHandler
+OTG_HS_WKUP_IRQHandler
+OTG_HS_IRQHandler
+DCMI_PSSI_IRQHandler
+CRYP_IRQHandler
+HASH_RNG_IRQHandler
+FPU_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+SAI1_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+DMA2D_IRQHandler
+OCTOSPI1_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+DMAMUX1_OVR_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+DFSDM1_FLT3_IRQHandler
+SWPMI1_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+MDIOS_WKUP_IRQHandler
+MDIOS_IRQHandler
+MDMA_IRQHandler
+SDMMC2_IRQHandler
+HSEM1_IRQHandler
+ADC3_IRQHandler
+DMAMUX2_OVR_IRQHandler
+BDMA_Channel0_IRQHandler
+BDMA_Channel1_IRQHandler
+BDMA_Channel2_IRQHandler
+BDMA_Channel3_IRQHandler
+BDMA_Channel4_IRQHandler
+BDMA_Channel5_IRQHandler
+BDMA_Channel6_IRQHandler
+BDMA_Channel7_IRQHandler
+COMP1_IRQHandler
+LPTIM2_IRQHandler
+LPTIM3_IRQHandler
+LPTIM4_IRQHandler
+LPTIM5_IRQHandler
+LPUART1_IRQHandler
+CRS_IRQHandler
+ECC_IRQHandler
+SAI4_IRQHandler
+DTS_IRQHandler
+WAKEUP_PIN_IRQHandler
+OCTOSPI2_IRQHandler
+OTFDEC1_IRQHandler
+OTFDEC2_IRQHandler
+FMAC_IRQHandler
+CORDIC_IRQHandler
+UART9_IRQHandler
+USART10_IRQHandler
+I2C5_EV_IRQHandler
+I2C5_ER_IRQHandler
+FDCAN3_IT0_IRQHandler
+FDCAN3_IT1_IRQHandler
+TIM23_IRQHandler
+TIM24_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h735xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h735xx.s new file mode 100644 index 0000000..d60ea19 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h735xx.s @@ -0,0 +1,622 @@ +;********************************************************************************
+;* File Name : startup_stm32h735xx.s
+;* @author MCD Application Team
+;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it)
+ DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_PSSI_IRQHandler ; DCMI, PSSI
+ DCD CRYP_IRQHandler ; CRYP
+ DCD HASH_RNG_IRQHandler ; Hash and Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD 0 ; Reserved
+ DCD OCTOSPI1_IRQHandler ; OCTOSPI1
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD 0 ; Reserved
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD 0 ; Reserved
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD 0 ; Reserved
+ DCD ADC3_IRQHandler ; ADC3 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP1_IRQHandler ; COMP1 global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
+ DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD 0 ; Reserved
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
+ DCD SAI4_IRQHandler ; SAI4 global interrupt
+ DCD DTS_IRQHandler ; DTS interrupt
+ DCD 0 ; Reserved
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+ DCD OCTOSPI2_IRQHandler ; OCTOSPI2 Interrupt
+ DCD OTFDEC1_IRQHandler ; OTFDEC1 Interrupt
+ DCD OTFDEC2_IRQHandler ; OTFDEC2 Interrupt
+ DCD FMAC_IRQHandler ; FMAC Interrupt
+ DCD CORDIC_IRQHandler ; CORDIC Interrupt
+ DCD UART9_IRQHandler ; UART9 Interrupt
+ DCD USART10_IRQHandler ; UART10 Interrupt
+ DCD I2C5_EV_IRQHandler ; I2C5 Event Interrupt
+ DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt
+ DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0
+ DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1
+ DCD TIM23_IRQHandler ; TIM23 global interrupt
+ DCD TIM24_IRQHandler ; TIM24 global interrupt
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_AVD_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream0_IRQHandler [WEAK]
+ EXPORT DMA1_Stream1_IRQHandler [WEAK]
+ EXPORT DMA1_Stream2_IRQHandler [WEAK]
+ EXPORT DMA1_Stream3_IRQHandler [WEAK]
+ EXPORT DMA1_Stream4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream5_IRQHandler [WEAK]
+ EXPORT DMA1_Stream6_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT1_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT1_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
+ EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT SDMMC1_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Stream0_IRQHandler [WEAK]
+ EXPORT DMA2_Stream1_IRQHandler [WEAK]
+ EXPORT DMA2_Stream2_IRQHandler [WEAK]
+ EXPORT DMA2_Stream3_IRQHandler [WEAK]
+ EXPORT DMA2_Stream4_IRQHandler [WEAK]
+ EXPORT ETH_IRQHandler [WEAK]
+ EXPORT ETH_WKUP_IRQHandler [WEAK]
+ EXPORT FDCAN_CAL_IRQHandler [WEAK]
+ EXPORT DMA2_Stream5_IRQHandler [WEAK]
+ EXPORT DMA2_Stream6_IRQHandler [WEAK]
+ EXPORT DMA2_Stream7_IRQHandler [WEAK]
+ EXPORT USART6_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_HS_IRQHandler [WEAK]
+ EXPORT DCMI_PSSI_IRQHandler [WEAK]
+ EXPORT CRYP_IRQHandler [WEAK]
+ EXPORT HASH_RNG_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT UART7_IRQHandler [WEAK]
+ EXPORT UART8_IRQHandler [WEAK]
+ EXPORT SPI4_IRQHandler [WEAK]
+ EXPORT SPI5_IRQHandler [WEAK]
+ EXPORT SPI6_IRQHandler [WEAK]
+ EXPORT SAI1_IRQHandler [WEAK]
+ EXPORT LTDC_IRQHandler [WEAK]
+ EXPORT LTDC_ER_IRQHandler [WEAK]
+ EXPORT DMA2D_IRQHandler [WEAK]
+ EXPORT OCTOSPI1_IRQHandler [WEAK]
+ EXPORT LPTIM1_IRQHandler [WEAK]
+ EXPORT CEC_IRQHandler [WEAK]
+ EXPORT I2C4_EV_IRQHandler [WEAK]
+ EXPORT I2C4_ER_IRQHandler [WEAK]
+ EXPORT SPDIF_RX_IRQHandler [WEAK]
+ EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
+ EXPORT SWPMI1_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT MDIOS_WKUP_IRQHandler [WEAK]
+ EXPORT MDIOS_IRQHandler [WEAK]
+ EXPORT MDMA_IRQHandler [WEAK]
+ EXPORT SDMMC2_IRQHandler [WEAK]
+ EXPORT HSEM1_IRQHandler [WEAK]
+ EXPORT ADC3_IRQHandler [WEAK]
+ EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
+ EXPORT BDMA_Channel0_IRQHandler [WEAK]
+ EXPORT BDMA_Channel1_IRQHandler [WEAK]
+ EXPORT BDMA_Channel2_IRQHandler [WEAK]
+ EXPORT BDMA_Channel3_IRQHandler [WEAK]
+ EXPORT BDMA_Channel4_IRQHandler [WEAK]
+ EXPORT BDMA_Channel5_IRQHandler [WEAK]
+ EXPORT BDMA_Channel6_IRQHandler [WEAK]
+ EXPORT BDMA_Channel7_IRQHandler [WEAK]
+ EXPORT COMP1_IRQHandler [WEAK]
+ EXPORT LPTIM2_IRQHandler [WEAK]
+ EXPORT LPTIM3_IRQHandler [WEAK]
+ EXPORT LPTIM4_IRQHandler [WEAK]
+ EXPORT LPTIM5_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT CRS_IRQHandler [WEAK]
+ EXPORT ECC_IRQHandler [WEAK]
+ EXPORT SAI4_IRQHandler [WEAK]
+ EXPORT DTS_IRQHandler [WEAK]
+ EXPORT WAKEUP_PIN_IRQHandler [WEAK]
+ EXPORT OCTOSPI2_IRQHandler [WEAK]
+ EXPORT OTFDEC1_IRQHandler [WEAK]
+ EXPORT OTFDEC2_IRQHandler [WEAK]
+ EXPORT FMAC_IRQHandler [WEAK]
+ EXPORT CORDIC_IRQHandler [WEAK]
+ EXPORT UART9_IRQHandler [WEAK]
+ EXPORT USART10_IRQHandler [WEAK]
+ EXPORT I2C5_EV_IRQHandler [WEAK]
+ EXPORT I2C5_ER_IRQHandler [WEAK]
+ EXPORT FDCAN3_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN3_IT1_IRQHandler [WEAK]
+ EXPORT TIM23_IRQHandler [WEAK]
+ EXPORT TIM24_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_AVD_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler
+DMA1_Stream2_IRQHandler
+DMA1_Stream3_IRQHandler
+DMA1_Stream4_IRQHandler
+DMA1_Stream5_IRQHandler
+DMA1_Stream6_IRQHandler
+ADC_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+FDCAN2_IT1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+TIM8_BRK_TIM12_IRQHandler
+TIM8_UP_TIM13_IRQHandler
+TIM8_TRG_COM_TIM14_IRQHandler
+TIM8_CC_IRQHandler
+DMA1_Stream7_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Stream0_IRQHandler
+DMA2_Stream1_IRQHandler
+DMA2_Stream2_IRQHandler
+DMA2_Stream3_IRQHandler
+DMA2_Stream4_IRQHandler
+ETH_IRQHandler
+ETH_WKUP_IRQHandler
+FDCAN_CAL_IRQHandler
+DMA2_Stream5_IRQHandler
+DMA2_Stream6_IRQHandler
+DMA2_Stream7_IRQHandler
+USART6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+OTG_HS_EP1_OUT_IRQHandler
+OTG_HS_EP1_IN_IRQHandler
+OTG_HS_WKUP_IRQHandler
+OTG_HS_IRQHandler
+DCMI_PSSI_IRQHandler
+CRYP_IRQHandler
+HASH_RNG_IRQHandler
+FPU_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+SAI1_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+DMA2D_IRQHandler
+OCTOSPI1_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+DMAMUX1_OVR_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+DFSDM1_FLT3_IRQHandler
+SWPMI1_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+MDIOS_WKUP_IRQHandler
+MDIOS_IRQHandler
+MDMA_IRQHandler
+SDMMC2_IRQHandler
+HSEM1_IRQHandler
+ADC3_IRQHandler
+DMAMUX2_OVR_IRQHandler
+BDMA_Channel0_IRQHandler
+BDMA_Channel1_IRQHandler
+BDMA_Channel2_IRQHandler
+BDMA_Channel3_IRQHandler
+BDMA_Channel4_IRQHandler
+BDMA_Channel5_IRQHandler
+BDMA_Channel6_IRQHandler
+BDMA_Channel7_IRQHandler
+COMP1_IRQHandler
+LPTIM2_IRQHandler
+LPTIM3_IRQHandler
+LPTIM4_IRQHandler
+LPTIM5_IRQHandler
+LPUART1_IRQHandler
+CRS_IRQHandler
+ECC_IRQHandler
+SAI4_IRQHandler
+DTS_IRQHandler
+WAKEUP_PIN_IRQHandler
+OCTOSPI2_IRQHandler
+OTFDEC1_IRQHandler
+OTFDEC2_IRQHandler
+FMAC_IRQHandler
+CORDIC_IRQHandler
+UART9_IRQHandler
+USART10_IRQHandler
+I2C5_EV_IRQHandler
+I2C5_ER_IRQHandler
+FDCAN3_IT0_IRQHandler
+FDCAN3_IT1_IRQHandler
+TIM23_IRQHandler
+TIM24_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h742xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h742xx.s new file mode 100644 index 0000000..d26d678 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h742xx.s @@ -0,0 +1,603 @@ +;********************************************************************************
+;* File Name : startup_stm32h742xx.s
+;* @author MCD Application Team
+;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it)
+ DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_IRQHandler ; DCMI
+ DCD 0 ; Reserved
+ DCD RNG_IRQHandler ; Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD QUADSPI_IRQHandler ; QUADSPI
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
+ DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
+ DCD OTG_FS_IRQHandler ; USB OTG FS
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
+ DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
+ DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
+ DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
+ DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
+ DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
+ DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD SAI3_IRQHandler ; SAI3 global Interrupt
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD 0 ; Reserved
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD 0 ; Reserved
+ DCD ADC3_IRQHandler ; ADC3 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP1_IRQHandler ; COMP1 global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
+ DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD 0 ; Reserved
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
+ DCD SAI4_IRQHandler ; SAI4 global interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_AVD_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream0_IRQHandler [WEAK]
+ EXPORT DMA1_Stream1_IRQHandler [WEAK]
+ EXPORT DMA1_Stream2_IRQHandler [WEAK]
+ EXPORT DMA1_Stream3_IRQHandler [WEAK]
+ EXPORT DMA1_Stream4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream5_IRQHandler [WEAK]
+ EXPORT DMA1_Stream6_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT1_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT1_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
+ EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT SDMMC1_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Stream0_IRQHandler [WEAK]
+ EXPORT DMA2_Stream1_IRQHandler [WEAK]
+ EXPORT DMA2_Stream2_IRQHandler [WEAK]
+ EXPORT DMA2_Stream3_IRQHandler [WEAK]
+ EXPORT DMA2_Stream4_IRQHandler [WEAK]
+ EXPORT ETH_IRQHandler [WEAK]
+ EXPORT ETH_WKUP_IRQHandler [WEAK]
+ EXPORT FDCAN_CAL_IRQHandler [WEAK]
+ EXPORT DMA2_Stream5_IRQHandler [WEAK]
+ EXPORT DMA2_Stream6_IRQHandler [WEAK]
+ EXPORT DMA2_Stream7_IRQHandler [WEAK]
+ EXPORT USART6_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_HS_IRQHandler [WEAK]
+ EXPORT DCMI_IRQHandler [WEAK]
+ EXPORT RNG_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT UART7_IRQHandler [WEAK]
+ EXPORT UART8_IRQHandler [WEAK]
+ EXPORT SPI4_IRQHandler [WEAK]
+ EXPORT SPI5_IRQHandler [WEAK]
+ EXPORT SPI6_IRQHandler [WEAK]
+ EXPORT SAI1_IRQHandler [WEAK]
+ EXPORT DMA2D_IRQHandler [WEAK]
+ EXPORT SAI2_IRQHandler [WEAK]
+ EXPORT QUADSPI_IRQHandler [WEAK]
+ EXPORT LPTIM1_IRQHandler [WEAK]
+ EXPORT CEC_IRQHandler [WEAK]
+ EXPORT I2C4_EV_IRQHandler [WEAK]
+ EXPORT I2C4_ER_IRQHandler [WEAK]
+ EXPORT SPDIF_RX_IRQHandler [WEAK]
+ EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_FS_IRQHandler [WEAK]
+ EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
+ EXPORT HRTIM1_Master_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIME_IRQHandler [WEAK]
+ EXPORT HRTIM1_FLT_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
+ EXPORT SAI3_IRQHandler [WEAK]
+ EXPORT SWPMI1_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT MDIOS_WKUP_IRQHandler [WEAK]
+ EXPORT MDIOS_IRQHandler [WEAK]
+ EXPORT MDMA_IRQHandler [WEAK]
+ EXPORT SDMMC2_IRQHandler [WEAK]
+ EXPORT HSEM1_IRQHandler [WEAK]
+ EXPORT ADC3_IRQHandler [WEAK]
+ EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
+ EXPORT BDMA_Channel0_IRQHandler [WEAK]
+ EXPORT BDMA_Channel1_IRQHandler [WEAK]
+ EXPORT BDMA_Channel2_IRQHandler [WEAK]
+ EXPORT BDMA_Channel3_IRQHandler [WEAK]
+ EXPORT BDMA_Channel4_IRQHandler [WEAK]
+ EXPORT BDMA_Channel5_IRQHandler [WEAK]
+ EXPORT BDMA_Channel6_IRQHandler [WEAK]
+ EXPORT BDMA_Channel7_IRQHandler [WEAK]
+ EXPORT COMP1_IRQHandler [WEAK]
+ EXPORT LPTIM2_IRQHandler [WEAK]
+ EXPORT LPTIM3_IRQHandler [WEAK]
+ EXPORT LPTIM4_IRQHandler [WEAK]
+ EXPORT LPTIM5_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT CRS_IRQHandler [WEAK]
+ EXPORT ECC_IRQHandler [WEAK]
+ EXPORT SAI4_IRQHandler [WEAK]
+ EXPORT WAKEUP_PIN_IRQHandler [WEAK]
+
+
+WWDG_IRQHandler
+PVD_AVD_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler
+DMA1_Stream2_IRQHandler
+DMA1_Stream3_IRQHandler
+DMA1_Stream4_IRQHandler
+DMA1_Stream5_IRQHandler
+DMA1_Stream6_IRQHandler
+ADC_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+FDCAN2_IT1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+TIM8_BRK_TIM12_IRQHandler
+TIM8_UP_TIM13_IRQHandler
+TIM8_TRG_COM_TIM14_IRQHandler
+TIM8_CC_IRQHandler
+DMA1_Stream7_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Stream0_IRQHandler
+DMA2_Stream1_IRQHandler
+DMA2_Stream2_IRQHandler
+DMA2_Stream3_IRQHandler
+DMA2_Stream4_IRQHandler
+ETH_IRQHandler
+ETH_WKUP_IRQHandler
+FDCAN_CAL_IRQHandler
+DMA2_Stream5_IRQHandler
+DMA2_Stream6_IRQHandler
+DMA2_Stream7_IRQHandler
+USART6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+OTG_HS_EP1_OUT_IRQHandler
+OTG_HS_EP1_IN_IRQHandler
+OTG_HS_WKUP_IRQHandler
+OTG_HS_IRQHandler
+DCMI_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+SAI1_IRQHandler
+DMA2D_IRQHandler
+SAI2_IRQHandler
+QUADSPI_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+OTG_FS_EP1_OUT_IRQHandler
+OTG_FS_EP1_IN_IRQHandler
+OTG_FS_WKUP_IRQHandler
+OTG_FS_IRQHandler
+DMAMUX1_OVR_IRQHandler
+HRTIM1_Master_IRQHandler
+HRTIM1_TIMA_IRQHandler
+HRTIM1_TIMB_IRQHandler
+HRTIM1_TIMC_IRQHandler
+HRTIM1_TIMD_IRQHandler
+HRTIM1_TIME_IRQHandler
+HRTIM1_FLT_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+DFSDM1_FLT3_IRQHandler
+SAI3_IRQHandler
+SWPMI1_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+MDIOS_WKUP_IRQHandler
+MDIOS_IRQHandler
+MDMA_IRQHandler
+SDMMC2_IRQHandler
+HSEM1_IRQHandler
+ADC3_IRQHandler
+DMAMUX2_OVR_IRQHandler
+BDMA_Channel0_IRQHandler
+BDMA_Channel1_IRQHandler
+BDMA_Channel2_IRQHandler
+BDMA_Channel3_IRQHandler
+BDMA_Channel4_IRQHandler
+BDMA_Channel5_IRQHandler
+BDMA_Channel6_IRQHandler
+BDMA_Channel7_IRQHandler
+COMP1_IRQHandler
+LPTIM2_IRQHandler
+LPTIM3_IRQHandler
+LPTIM4_IRQHandler
+LPTIM5_IRQHandler
+LPUART1_IRQHandler
+CRS_IRQHandler
+ECC_IRQHandler
+SAI4_IRQHandler
+WAKEUP_PIN_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h743xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h743xx.s new file mode 100644 index 0000000..9d75b66 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h743xx.s @@ -0,0 +1,609 @@ +;********************************************************************************
+;* File Name : startup_stm32h743xx.s
+;* @author MCD Application Team
+;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it)
+ DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_IRQHandler ; DCMI
+ DCD 0 ; Reserved
+ DCD RNG_IRQHandler ; Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD QUADSPI_IRQHandler ; QUADSPI
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
+ DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
+ DCD OTG_FS_IRQHandler ; USB OTG FS
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
+ DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
+ DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
+ DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
+ DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
+ DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
+ DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD SAI3_IRQHandler ; SAI3 global Interrupt
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD JPEG_IRQHandler ; JPEG global Interrupt
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD 0 ; Reserved
+ DCD ADC3_IRQHandler ; ADC3 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP1_IRQHandler ; COMP1 global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
+ DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD 0 ; Reserved
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
+ DCD SAI4_IRQHandler ; SAI4 global interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_AVD_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream0_IRQHandler [WEAK]
+ EXPORT DMA1_Stream1_IRQHandler [WEAK]
+ EXPORT DMA1_Stream2_IRQHandler [WEAK]
+ EXPORT DMA1_Stream3_IRQHandler [WEAK]
+ EXPORT DMA1_Stream4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream5_IRQHandler [WEAK]
+ EXPORT DMA1_Stream6_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT1_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT1_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
+ EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT SDMMC1_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Stream0_IRQHandler [WEAK]
+ EXPORT DMA2_Stream1_IRQHandler [WEAK]
+ EXPORT DMA2_Stream2_IRQHandler [WEAK]
+ EXPORT DMA2_Stream3_IRQHandler [WEAK]
+ EXPORT DMA2_Stream4_IRQHandler [WEAK]
+ EXPORT ETH_IRQHandler [WEAK]
+ EXPORT ETH_WKUP_IRQHandler [WEAK]
+ EXPORT FDCAN_CAL_IRQHandler [WEAK]
+ EXPORT DMA2_Stream5_IRQHandler [WEAK]
+ EXPORT DMA2_Stream6_IRQHandler [WEAK]
+ EXPORT DMA2_Stream7_IRQHandler [WEAK]
+ EXPORT USART6_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_HS_IRQHandler [WEAK]
+ EXPORT DCMI_IRQHandler [WEAK]
+ EXPORT RNG_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT UART7_IRQHandler [WEAK]
+ EXPORT UART8_IRQHandler [WEAK]
+ EXPORT SPI4_IRQHandler [WEAK]
+ EXPORT SPI5_IRQHandler [WEAK]
+ EXPORT SPI6_IRQHandler [WEAK]
+ EXPORT SAI1_IRQHandler [WEAK]
+ EXPORT LTDC_IRQHandler [WEAK]
+ EXPORT LTDC_ER_IRQHandler [WEAK]
+ EXPORT DMA2D_IRQHandler [WEAK]
+ EXPORT SAI2_IRQHandler [WEAK]
+ EXPORT QUADSPI_IRQHandler [WEAK]
+ EXPORT LPTIM1_IRQHandler [WEAK]
+ EXPORT CEC_IRQHandler [WEAK]
+ EXPORT I2C4_EV_IRQHandler [WEAK]
+ EXPORT I2C4_ER_IRQHandler [WEAK]
+ EXPORT SPDIF_RX_IRQHandler [WEAK]
+ EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_FS_IRQHandler [WEAK]
+ EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
+ EXPORT HRTIM1_Master_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIME_IRQHandler [WEAK]
+ EXPORT HRTIM1_FLT_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
+ EXPORT SAI3_IRQHandler [WEAK]
+ EXPORT SWPMI1_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT MDIOS_WKUP_IRQHandler [WEAK]
+ EXPORT MDIOS_IRQHandler [WEAK]
+ EXPORT JPEG_IRQHandler [WEAK]
+ EXPORT MDMA_IRQHandler [WEAK]
+ EXPORT SDMMC2_IRQHandler [WEAK]
+ EXPORT HSEM1_IRQHandler [WEAK]
+ EXPORT ADC3_IRQHandler [WEAK]
+ EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
+ EXPORT BDMA_Channel0_IRQHandler [WEAK]
+ EXPORT BDMA_Channel1_IRQHandler [WEAK]
+ EXPORT BDMA_Channel2_IRQHandler [WEAK]
+ EXPORT BDMA_Channel3_IRQHandler [WEAK]
+ EXPORT BDMA_Channel4_IRQHandler [WEAK]
+ EXPORT BDMA_Channel5_IRQHandler [WEAK]
+ EXPORT BDMA_Channel6_IRQHandler [WEAK]
+ EXPORT BDMA_Channel7_IRQHandler [WEAK]
+ EXPORT COMP1_IRQHandler [WEAK]
+ EXPORT LPTIM2_IRQHandler [WEAK]
+ EXPORT LPTIM3_IRQHandler [WEAK]
+ EXPORT LPTIM4_IRQHandler [WEAK]
+ EXPORT LPTIM5_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT CRS_IRQHandler [WEAK]
+ EXPORT ECC_IRQHandler [WEAK]
+ EXPORT SAI4_IRQHandler [WEAK]
+ EXPORT WAKEUP_PIN_IRQHandler [WEAK]
+
+
+WWDG_IRQHandler
+PVD_AVD_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler
+DMA1_Stream2_IRQHandler
+DMA1_Stream3_IRQHandler
+DMA1_Stream4_IRQHandler
+DMA1_Stream5_IRQHandler
+DMA1_Stream6_IRQHandler
+ADC_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+FDCAN2_IT1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+TIM8_BRK_TIM12_IRQHandler
+TIM8_UP_TIM13_IRQHandler
+TIM8_TRG_COM_TIM14_IRQHandler
+TIM8_CC_IRQHandler
+DMA1_Stream7_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Stream0_IRQHandler
+DMA2_Stream1_IRQHandler
+DMA2_Stream2_IRQHandler
+DMA2_Stream3_IRQHandler
+DMA2_Stream4_IRQHandler
+ETH_IRQHandler
+ETH_WKUP_IRQHandler
+FDCAN_CAL_IRQHandler
+DMA2_Stream5_IRQHandler
+DMA2_Stream6_IRQHandler
+DMA2_Stream7_IRQHandler
+USART6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+OTG_HS_EP1_OUT_IRQHandler
+OTG_HS_EP1_IN_IRQHandler
+OTG_HS_WKUP_IRQHandler
+OTG_HS_IRQHandler
+DCMI_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+SAI1_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+DMA2D_IRQHandler
+SAI2_IRQHandler
+QUADSPI_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+OTG_FS_EP1_OUT_IRQHandler
+OTG_FS_EP1_IN_IRQHandler
+OTG_FS_WKUP_IRQHandler
+OTG_FS_IRQHandler
+DMAMUX1_OVR_IRQHandler
+HRTIM1_Master_IRQHandler
+HRTIM1_TIMA_IRQHandler
+HRTIM1_TIMB_IRQHandler
+HRTIM1_TIMC_IRQHandler
+HRTIM1_TIMD_IRQHandler
+HRTIM1_TIME_IRQHandler
+HRTIM1_FLT_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+DFSDM1_FLT3_IRQHandler
+SAI3_IRQHandler
+SWPMI1_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+MDIOS_WKUP_IRQHandler
+MDIOS_IRQHandler
+JPEG_IRQHandler
+MDMA_IRQHandler
+SDMMC2_IRQHandler
+HSEM1_IRQHandler
+ADC3_IRQHandler
+DMAMUX2_OVR_IRQHandler
+BDMA_Channel0_IRQHandler
+BDMA_Channel1_IRQHandler
+BDMA_Channel2_IRQHandler
+BDMA_Channel3_IRQHandler
+BDMA_Channel4_IRQHandler
+BDMA_Channel5_IRQHandler
+BDMA_Channel6_IRQHandler
+BDMA_Channel7_IRQHandler
+COMP1_IRQHandler
+LPTIM2_IRQHandler
+LPTIM3_IRQHandler
+LPTIM4_IRQHandler
+LPTIM5_IRQHandler
+LPUART1_IRQHandler
+CRS_IRQHandler
+ECC_IRQHandler
+SAI4_IRQHandler
+WAKEUP_PIN_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h745xg.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h745xg.s new file mode 100644 index 0000000..08f8306 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h745xg.s @@ -0,0 +1,619 @@ +;********************************************************************************
+;* File Name : startup_stm32h745xx.s
+;* @author MCD Application Team
+;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it, wwdg2_it)
+ DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4
+ DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_IRQHandler ; DCMI
+ DCD 0 ; Reserved
+ DCD RNG_IRQHandler ; Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD QUADSPI_IRQHandler ; QUADSPI
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
+ DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
+ DCD OTG_FS_IRQHandler ; USB OTG FS
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
+ DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
+ DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
+ DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
+ DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
+ DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
+ DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD SAI3_IRQHandler ; SAI3 global Interrupt
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD JPEG_IRQHandler ; JPEG global Interrupt
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD HSEM2_IRQHandler ; HSEM2 global Interrupt
+ DCD ADC3_IRQHandler ; ADC3 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP1_IRQHandler ; COMP1 global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
+ DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it)
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
+ DCD SAI4_IRQHandler ; SAI4 global interrupt
+ DCD 0 ; Reserved
+ DCD HOLD_CORE_IRQHandler ; Hold core interrupt
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_AVD_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream0_IRQHandler [WEAK]
+ EXPORT DMA1_Stream1_IRQHandler [WEAK]
+ EXPORT DMA1_Stream2_IRQHandler [WEAK]
+ EXPORT DMA1_Stream3_IRQHandler [WEAK]
+ EXPORT DMA1_Stream4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream5_IRQHandler [WEAK]
+ EXPORT DMA1_Stream6_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT1_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT1_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
+ EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT SDMMC1_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Stream0_IRQHandler [WEAK]
+ EXPORT DMA2_Stream1_IRQHandler [WEAK]
+ EXPORT DMA2_Stream2_IRQHandler [WEAK]
+ EXPORT DMA2_Stream3_IRQHandler [WEAK]
+ EXPORT DMA2_Stream4_IRQHandler [WEAK]
+ EXPORT ETH_IRQHandler [WEAK]
+ EXPORT ETH_WKUP_IRQHandler [WEAK]
+ EXPORT FDCAN_CAL_IRQHandler [WEAK]
+ EXPORT CM7_SEV_IRQHandler [WEAK]
+ EXPORT CM4_SEV_IRQHandler [WEAK]
+ EXPORT DMA2_Stream5_IRQHandler [WEAK]
+ EXPORT DMA2_Stream6_IRQHandler [WEAK]
+ EXPORT DMA2_Stream7_IRQHandler [WEAK]
+ EXPORT USART6_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_HS_IRQHandler [WEAK]
+ EXPORT DCMI_IRQHandler [WEAK]
+ EXPORT RNG_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT UART7_IRQHandler [WEAK]
+ EXPORT UART8_IRQHandler [WEAK]
+ EXPORT SPI4_IRQHandler [WEAK]
+ EXPORT SPI5_IRQHandler [WEAK]
+ EXPORT SPI6_IRQHandler [WEAK]
+ EXPORT SAI1_IRQHandler [WEAK]
+ EXPORT LTDC_IRQHandler [WEAK]
+ EXPORT LTDC_ER_IRQHandler [WEAK]
+ EXPORT DMA2D_IRQHandler [WEAK]
+ EXPORT SAI2_IRQHandler [WEAK]
+ EXPORT QUADSPI_IRQHandler [WEAK]
+ EXPORT LPTIM1_IRQHandler [WEAK]
+ EXPORT CEC_IRQHandler [WEAK]
+ EXPORT I2C4_EV_IRQHandler [WEAK]
+ EXPORT I2C4_ER_IRQHandler [WEAK]
+ EXPORT SPDIF_RX_IRQHandler [WEAK]
+ EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_FS_IRQHandler [WEAK]
+ EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
+ EXPORT HRTIM1_Master_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIME_IRQHandler [WEAK]
+ EXPORT HRTIM1_FLT_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
+ EXPORT SAI3_IRQHandler [WEAK]
+ EXPORT SWPMI1_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT MDIOS_WKUP_IRQHandler [WEAK]
+ EXPORT MDIOS_IRQHandler [WEAK]
+ EXPORT JPEG_IRQHandler [WEAK]
+ EXPORT MDMA_IRQHandler [WEAK]
+ EXPORT SDMMC2_IRQHandler [WEAK]
+ EXPORT HSEM1_IRQHandler [WEAK]
+ EXPORT HSEM2_IRQHandler [WEAK]
+ EXPORT ADC3_IRQHandler [WEAK]
+ EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
+ EXPORT BDMA_Channel0_IRQHandler [WEAK]
+ EXPORT BDMA_Channel1_IRQHandler [WEAK]
+ EXPORT BDMA_Channel2_IRQHandler [WEAK]
+ EXPORT BDMA_Channel3_IRQHandler [WEAK]
+ EXPORT BDMA_Channel4_IRQHandler [WEAK]
+ EXPORT BDMA_Channel5_IRQHandler [WEAK]
+ EXPORT BDMA_Channel6_IRQHandler [WEAK]
+ EXPORT BDMA_Channel7_IRQHandler [WEAK]
+ EXPORT COMP1_IRQHandler [WEAK]
+ EXPORT LPTIM2_IRQHandler [WEAK]
+ EXPORT LPTIM3_IRQHandler [WEAK]
+ EXPORT LPTIM4_IRQHandler [WEAK]
+ EXPORT LPTIM5_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT WWDG_RST_IRQHandler [WEAK]
+ EXPORT CRS_IRQHandler [WEAK]
+ EXPORT ECC_IRQHandler [WEAK]
+ EXPORT SAI4_IRQHandler [WEAK]
+ EXPORT HOLD_CORE_IRQHandler [WEAK]
+ EXPORT WAKEUP_PIN_IRQHandler [WEAK]
+
+
+WWDG_IRQHandler
+PVD_AVD_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler
+DMA1_Stream2_IRQHandler
+DMA1_Stream3_IRQHandler
+DMA1_Stream4_IRQHandler
+DMA1_Stream5_IRQHandler
+DMA1_Stream6_IRQHandler
+ADC_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+FDCAN2_IT1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+TIM8_BRK_TIM12_IRQHandler
+TIM8_UP_TIM13_IRQHandler
+TIM8_TRG_COM_TIM14_IRQHandler
+TIM8_CC_IRQHandler
+DMA1_Stream7_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Stream0_IRQHandler
+DMA2_Stream1_IRQHandler
+DMA2_Stream2_IRQHandler
+DMA2_Stream3_IRQHandler
+DMA2_Stream4_IRQHandler
+ETH_IRQHandler
+ETH_WKUP_IRQHandler
+FDCAN_CAL_IRQHandler
+CM7_SEV_IRQHandler
+CM4_SEV_IRQHandler
+DMA2_Stream5_IRQHandler
+DMA2_Stream6_IRQHandler
+DMA2_Stream7_IRQHandler
+USART6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+OTG_HS_EP1_OUT_IRQHandler
+OTG_HS_EP1_IN_IRQHandler
+OTG_HS_WKUP_IRQHandler
+OTG_HS_IRQHandler
+DCMI_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+SAI1_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+DMA2D_IRQHandler
+SAI2_IRQHandler
+QUADSPI_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+OTG_FS_EP1_OUT_IRQHandler
+OTG_FS_EP1_IN_IRQHandler
+OTG_FS_WKUP_IRQHandler
+OTG_FS_IRQHandler
+DMAMUX1_OVR_IRQHandler
+HRTIM1_Master_IRQHandler
+HRTIM1_TIMA_IRQHandler
+HRTIM1_TIMB_IRQHandler
+HRTIM1_TIMC_IRQHandler
+HRTIM1_TIMD_IRQHandler
+HRTIM1_TIME_IRQHandler
+HRTIM1_FLT_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+DFSDM1_FLT3_IRQHandler
+SAI3_IRQHandler
+SWPMI1_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+MDIOS_WKUP_IRQHandler
+MDIOS_IRQHandler
+JPEG_IRQHandler
+MDMA_IRQHandler
+SDMMC2_IRQHandler
+HSEM1_IRQHandler
+HSEM2_IRQHandler
+ADC3_IRQHandler
+DMAMUX2_OVR_IRQHandler
+BDMA_Channel0_IRQHandler
+BDMA_Channel1_IRQHandler
+BDMA_Channel2_IRQHandler
+BDMA_Channel3_IRQHandler
+BDMA_Channel4_IRQHandler
+BDMA_Channel5_IRQHandler
+BDMA_Channel6_IRQHandler
+BDMA_Channel7_IRQHandler
+COMP1_IRQHandler
+LPTIM2_IRQHandler
+LPTIM3_IRQHandler
+LPTIM4_IRQHandler
+LPTIM5_IRQHandler
+LPUART1_IRQHandler
+WWDG_RST_IRQHandler
+CRS_IRQHandler
+ECC_IRQHandler
+SAI4_IRQHandler
+HOLD_CORE_IRQHandler
+WAKEUP_PIN_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h745xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h745xx.s new file mode 100644 index 0000000..08f8306 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h745xx.s @@ -0,0 +1,619 @@ +;********************************************************************************
+;* File Name : startup_stm32h745xx.s
+;* @author MCD Application Team
+;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it, wwdg2_it)
+ DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4
+ DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_IRQHandler ; DCMI
+ DCD 0 ; Reserved
+ DCD RNG_IRQHandler ; Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD QUADSPI_IRQHandler ; QUADSPI
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
+ DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
+ DCD OTG_FS_IRQHandler ; USB OTG FS
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
+ DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
+ DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
+ DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
+ DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
+ DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
+ DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD SAI3_IRQHandler ; SAI3 global Interrupt
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD JPEG_IRQHandler ; JPEG global Interrupt
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD HSEM2_IRQHandler ; HSEM2 global Interrupt
+ DCD ADC3_IRQHandler ; ADC3 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP1_IRQHandler ; COMP1 global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
+ DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it)
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
+ DCD SAI4_IRQHandler ; SAI4 global interrupt
+ DCD 0 ; Reserved
+ DCD HOLD_CORE_IRQHandler ; Hold core interrupt
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_AVD_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream0_IRQHandler [WEAK]
+ EXPORT DMA1_Stream1_IRQHandler [WEAK]
+ EXPORT DMA1_Stream2_IRQHandler [WEAK]
+ EXPORT DMA1_Stream3_IRQHandler [WEAK]
+ EXPORT DMA1_Stream4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream5_IRQHandler [WEAK]
+ EXPORT DMA1_Stream6_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT1_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT1_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
+ EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT SDMMC1_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Stream0_IRQHandler [WEAK]
+ EXPORT DMA2_Stream1_IRQHandler [WEAK]
+ EXPORT DMA2_Stream2_IRQHandler [WEAK]
+ EXPORT DMA2_Stream3_IRQHandler [WEAK]
+ EXPORT DMA2_Stream4_IRQHandler [WEAK]
+ EXPORT ETH_IRQHandler [WEAK]
+ EXPORT ETH_WKUP_IRQHandler [WEAK]
+ EXPORT FDCAN_CAL_IRQHandler [WEAK]
+ EXPORT CM7_SEV_IRQHandler [WEAK]
+ EXPORT CM4_SEV_IRQHandler [WEAK]
+ EXPORT DMA2_Stream5_IRQHandler [WEAK]
+ EXPORT DMA2_Stream6_IRQHandler [WEAK]
+ EXPORT DMA2_Stream7_IRQHandler [WEAK]
+ EXPORT USART6_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_HS_IRQHandler [WEAK]
+ EXPORT DCMI_IRQHandler [WEAK]
+ EXPORT RNG_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT UART7_IRQHandler [WEAK]
+ EXPORT UART8_IRQHandler [WEAK]
+ EXPORT SPI4_IRQHandler [WEAK]
+ EXPORT SPI5_IRQHandler [WEAK]
+ EXPORT SPI6_IRQHandler [WEAK]
+ EXPORT SAI1_IRQHandler [WEAK]
+ EXPORT LTDC_IRQHandler [WEAK]
+ EXPORT LTDC_ER_IRQHandler [WEAK]
+ EXPORT DMA2D_IRQHandler [WEAK]
+ EXPORT SAI2_IRQHandler [WEAK]
+ EXPORT QUADSPI_IRQHandler [WEAK]
+ EXPORT LPTIM1_IRQHandler [WEAK]
+ EXPORT CEC_IRQHandler [WEAK]
+ EXPORT I2C4_EV_IRQHandler [WEAK]
+ EXPORT I2C4_ER_IRQHandler [WEAK]
+ EXPORT SPDIF_RX_IRQHandler [WEAK]
+ EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_FS_IRQHandler [WEAK]
+ EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
+ EXPORT HRTIM1_Master_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIME_IRQHandler [WEAK]
+ EXPORT HRTIM1_FLT_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
+ EXPORT SAI3_IRQHandler [WEAK]
+ EXPORT SWPMI1_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT MDIOS_WKUP_IRQHandler [WEAK]
+ EXPORT MDIOS_IRQHandler [WEAK]
+ EXPORT JPEG_IRQHandler [WEAK]
+ EXPORT MDMA_IRQHandler [WEAK]
+ EXPORT SDMMC2_IRQHandler [WEAK]
+ EXPORT HSEM1_IRQHandler [WEAK]
+ EXPORT HSEM2_IRQHandler [WEAK]
+ EXPORT ADC3_IRQHandler [WEAK]
+ EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
+ EXPORT BDMA_Channel0_IRQHandler [WEAK]
+ EXPORT BDMA_Channel1_IRQHandler [WEAK]
+ EXPORT BDMA_Channel2_IRQHandler [WEAK]
+ EXPORT BDMA_Channel3_IRQHandler [WEAK]
+ EXPORT BDMA_Channel4_IRQHandler [WEAK]
+ EXPORT BDMA_Channel5_IRQHandler [WEAK]
+ EXPORT BDMA_Channel6_IRQHandler [WEAK]
+ EXPORT BDMA_Channel7_IRQHandler [WEAK]
+ EXPORT COMP1_IRQHandler [WEAK]
+ EXPORT LPTIM2_IRQHandler [WEAK]
+ EXPORT LPTIM3_IRQHandler [WEAK]
+ EXPORT LPTIM4_IRQHandler [WEAK]
+ EXPORT LPTIM5_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT WWDG_RST_IRQHandler [WEAK]
+ EXPORT CRS_IRQHandler [WEAK]
+ EXPORT ECC_IRQHandler [WEAK]
+ EXPORT SAI4_IRQHandler [WEAK]
+ EXPORT HOLD_CORE_IRQHandler [WEAK]
+ EXPORT WAKEUP_PIN_IRQHandler [WEAK]
+
+
+WWDG_IRQHandler
+PVD_AVD_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler
+DMA1_Stream2_IRQHandler
+DMA1_Stream3_IRQHandler
+DMA1_Stream4_IRQHandler
+DMA1_Stream5_IRQHandler
+DMA1_Stream6_IRQHandler
+ADC_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+FDCAN2_IT1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+TIM8_BRK_TIM12_IRQHandler
+TIM8_UP_TIM13_IRQHandler
+TIM8_TRG_COM_TIM14_IRQHandler
+TIM8_CC_IRQHandler
+DMA1_Stream7_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Stream0_IRQHandler
+DMA2_Stream1_IRQHandler
+DMA2_Stream2_IRQHandler
+DMA2_Stream3_IRQHandler
+DMA2_Stream4_IRQHandler
+ETH_IRQHandler
+ETH_WKUP_IRQHandler
+FDCAN_CAL_IRQHandler
+CM7_SEV_IRQHandler
+CM4_SEV_IRQHandler
+DMA2_Stream5_IRQHandler
+DMA2_Stream6_IRQHandler
+DMA2_Stream7_IRQHandler
+USART6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+OTG_HS_EP1_OUT_IRQHandler
+OTG_HS_EP1_IN_IRQHandler
+OTG_HS_WKUP_IRQHandler
+OTG_HS_IRQHandler
+DCMI_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+SAI1_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+DMA2D_IRQHandler
+SAI2_IRQHandler
+QUADSPI_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+OTG_FS_EP1_OUT_IRQHandler
+OTG_FS_EP1_IN_IRQHandler
+OTG_FS_WKUP_IRQHandler
+OTG_FS_IRQHandler
+DMAMUX1_OVR_IRQHandler
+HRTIM1_Master_IRQHandler
+HRTIM1_TIMA_IRQHandler
+HRTIM1_TIMB_IRQHandler
+HRTIM1_TIMC_IRQHandler
+HRTIM1_TIMD_IRQHandler
+HRTIM1_TIME_IRQHandler
+HRTIM1_FLT_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+DFSDM1_FLT3_IRQHandler
+SAI3_IRQHandler
+SWPMI1_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+MDIOS_WKUP_IRQHandler
+MDIOS_IRQHandler
+JPEG_IRQHandler
+MDMA_IRQHandler
+SDMMC2_IRQHandler
+HSEM1_IRQHandler
+HSEM2_IRQHandler
+ADC3_IRQHandler
+DMAMUX2_OVR_IRQHandler
+BDMA_Channel0_IRQHandler
+BDMA_Channel1_IRQHandler
+BDMA_Channel2_IRQHandler
+BDMA_Channel3_IRQHandler
+BDMA_Channel4_IRQHandler
+BDMA_Channel5_IRQHandler
+BDMA_Channel6_IRQHandler
+BDMA_Channel7_IRQHandler
+COMP1_IRQHandler
+LPTIM2_IRQHandler
+LPTIM3_IRQHandler
+LPTIM4_IRQHandler
+LPTIM5_IRQHandler
+LPUART1_IRQHandler
+WWDG_RST_IRQHandler
+CRS_IRQHandler
+ECC_IRQHandler
+SAI4_IRQHandler
+HOLD_CORE_IRQHandler
+WAKEUP_PIN_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h747xg.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h747xg.s new file mode 100644 index 0000000..9dba686 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h747xg.s @@ -0,0 +1,621 @@ +;********************************************************************************
+;* File Name : startup_stm32h747xg.s
+;* @author MCD Application Team
+;* Description : STM32H7xg devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it, wwdg2_it)
+ DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4
+ DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_IRQHandler ; DCMI
+ DCD 0 ; Reserved
+ DCD RNG_IRQHandler ; Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD QUADSPI_IRQHandler ; QUADSPI
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
+ DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
+ DCD OTG_FS_IRQHandler ; USB OTG FS
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
+ DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
+ DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
+ DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
+ DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
+ DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
+ DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD SAI3_IRQHandler ; SAI3 global Interrupt
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD JPEG_IRQHandler ; JPEG global Interrupt
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD DSI_IRQHandler ; DSI global Interrupt
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD HSEM2_IRQHandler ; HSEM2 global Interrupt
+ DCD ADC3_IRQHandler ; ADC3 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP1_IRQHandler ; COMP1 global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
+ DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it)
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
+ DCD SAI4_IRQHandler ; SAI4 global interrupt
+ DCD 0 ; Reserved
+ DCD HOLD_CORE_IRQHandler ; Hold core interrupt
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_AVD_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream0_IRQHandler [WEAK]
+ EXPORT DMA1_Stream1_IRQHandler [WEAK]
+ EXPORT DMA1_Stream2_IRQHandler [WEAK]
+ EXPORT DMA1_Stream3_IRQHandler [WEAK]
+ EXPORT DMA1_Stream4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream5_IRQHandler [WEAK]
+ EXPORT DMA1_Stream6_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT1_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT1_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
+ EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT SDMMC1_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Stream0_IRQHandler [WEAK]
+ EXPORT DMA2_Stream1_IRQHandler [WEAK]
+ EXPORT DMA2_Stream2_IRQHandler [WEAK]
+ EXPORT DMA2_Stream3_IRQHandler [WEAK]
+ EXPORT DMA2_Stream4_IRQHandler [WEAK]
+ EXPORT ETH_IRQHandler [WEAK]
+ EXPORT ETH_WKUP_IRQHandler [WEAK]
+ EXPORT FDCAN_CAL_IRQHandler [WEAK]
+ EXPORT CM7_SEV_IRQHandler [WEAK]
+ EXPORT CM4_SEV_IRQHandler [WEAK]
+ EXPORT DMA2_Stream5_IRQHandler [WEAK]
+ EXPORT DMA2_Stream6_IRQHandler [WEAK]
+ EXPORT DMA2_Stream7_IRQHandler [WEAK]
+ EXPORT USART6_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_HS_IRQHandler [WEAK]
+ EXPORT DCMI_IRQHandler [WEAK]
+ EXPORT RNG_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT UART7_IRQHandler [WEAK]
+ EXPORT UART8_IRQHandler [WEAK]
+ EXPORT SPI4_IRQHandler [WEAK]
+ EXPORT SPI5_IRQHandler [WEAK]
+ EXPORT SPI6_IRQHandler [WEAK]
+ EXPORT SAI1_IRQHandler [WEAK]
+ EXPORT LTDC_IRQHandler [WEAK]
+ EXPORT LTDC_ER_IRQHandler [WEAK]
+ EXPORT DMA2D_IRQHandler [WEAK]
+ EXPORT SAI2_IRQHandler [WEAK]
+ EXPORT QUADSPI_IRQHandler [WEAK]
+ EXPORT LPTIM1_IRQHandler [WEAK]
+ EXPORT CEC_IRQHandler [WEAK]
+ EXPORT I2C4_EV_IRQHandler [WEAK]
+ EXPORT I2C4_ER_IRQHandler [WEAK]
+ EXPORT SPDIF_RX_IRQHandler [WEAK]
+ EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_FS_IRQHandler [WEAK]
+ EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
+ EXPORT HRTIM1_Master_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIME_IRQHandler [WEAK]
+ EXPORT HRTIM1_FLT_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
+ EXPORT SAI3_IRQHandler [WEAK]
+ EXPORT SWPMI1_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT MDIOS_WKUP_IRQHandler [WEAK]
+ EXPORT MDIOS_IRQHandler [WEAK]
+ EXPORT JPEG_IRQHandler [WEAK]
+ EXPORT MDMA_IRQHandler [WEAK]
+ EXPORT DSI_IRQHandler [WEAK]
+ EXPORT SDMMC2_IRQHandler [WEAK]
+ EXPORT HSEM1_IRQHandler [WEAK]
+ EXPORT HSEM2_IRQHandler [WEAK]
+ EXPORT ADC3_IRQHandler [WEAK]
+ EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
+ EXPORT BDMA_Channel0_IRQHandler [WEAK]
+ EXPORT BDMA_Channel1_IRQHandler [WEAK]
+ EXPORT BDMA_Channel2_IRQHandler [WEAK]
+ EXPORT BDMA_Channel3_IRQHandler [WEAK]
+ EXPORT BDMA_Channel4_IRQHandler [WEAK]
+ EXPORT BDMA_Channel5_IRQHandler [WEAK]
+ EXPORT BDMA_Channel6_IRQHandler [WEAK]
+ EXPORT BDMA_Channel7_IRQHandler [WEAK]
+ EXPORT COMP1_IRQHandler [WEAK]
+ EXPORT LPTIM2_IRQHandler [WEAK]
+ EXPORT LPTIM3_IRQHandler [WEAK]
+ EXPORT LPTIM4_IRQHandler [WEAK]
+ EXPORT LPTIM5_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT WWDG_RST_IRQHandler [WEAK]
+ EXPORT CRS_IRQHandler [WEAK]
+ EXPORT ECC_IRQHandler [WEAK]
+ EXPORT SAI4_IRQHandler [WEAK]
+ EXPORT HOLD_CORE_IRQHandler [WEAK]
+ EXPORT WAKEUP_PIN_IRQHandler [WEAK]
+
+
+WWDG_IRQHandler
+PVD_AVD_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler
+DMA1_Stream2_IRQHandler
+DMA1_Stream3_IRQHandler
+DMA1_Stream4_IRQHandler
+DMA1_Stream5_IRQHandler
+DMA1_Stream6_IRQHandler
+ADC_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+FDCAN2_IT1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+TIM8_BRK_TIM12_IRQHandler
+TIM8_UP_TIM13_IRQHandler
+TIM8_TRG_COM_TIM14_IRQHandler
+TIM8_CC_IRQHandler
+DMA1_Stream7_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Stream0_IRQHandler
+DMA2_Stream1_IRQHandler
+DMA2_Stream2_IRQHandler
+DMA2_Stream3_IRQHandler
+DMA2_Stream4_IRQHandler
+ETH_IRQHandler
+ETH_WKUP_IRQHandler
+FDCAN_CAL_IRQHandler
+CM7_SEV_IRQHandler
+CM4_SEV_IRQHandler
+DMA2_Stream5_IRQHandler
+DMA2_Stream6_IRQHandler
+DMA2_Stream7_IRQHandler
+USART6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+OTG_HS_EP1_OUT_IRQHandler
+OTG_HS_EP1_IN_IRQHandler
+OTG_HS_WKUP_IRQHandler
+OTG_HS_IRQHandler
+DCMI_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+SAI1_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+DMA2D_IRQHandler
+SAI2_IRQHandler
+QUADSPI_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+OTG_FS_EP1_OUT_IRQHandler
+OTG_FS_EP1_IN_IRQHandler
+OTG_FS_WKUP_IRQHandler
+OTG_FS_IRQHandler
+DMAMUX1_OVR_IRQHandler
+HRTIM1_Master_IRQHandler
+HRTIM1_TIMA_IRQHandler
+HRTIM1_TIMB_IRQHandler
+HRTIM1_TIMC_IRQHandler
+HRTIM1_TIMD_IRQHandler
+HRTIM1_TIME_IRQHandler
+HRTIM1_FLT_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+DFSDM1_FLT3_IRQHandler
+SAI3_IRQHandler
+SWPMI1_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+MDIOS_WKUP_IRQHandler
+MDIOS_IRQHandler
+JPEG_IRQHandler
+MDMA_IRQHandler
+DSI_IRQHandler
+SDMMC2_IRQHandler
+HSEM1_IRQHandler
+HSEM2_IRQHandler
+ADC3_IRQHandler
+DMAMUX2_OVR_IRQHandler
+BDMA_Channel0_IRQHandler
+BDMA_Channel1_IRQHandler
+BDMA_Channel2_IRQHandler
+BDMA_Channel3_IRQHandler
+BDMA_Channel4_IRQHandler
+BDMA_Channel5_IRQHandler
+BDMA_Channel6_IRQHandler
+BDMA_Channel7_IRQHandler
+COMP1_IRQHandler
+LPTIM2_IRQHandler
+LPTIM3_IRQHandler
+LPTIM4_IRQHandler
+LPTIM5_IRQHandler
+LPUART1_IRQHandler
+WWDG_RST_IRQHandler
+CRS_IRQHandler
+ECC_IRQHandler
+SAI4_IRQHandler
+HOLD_CORE_IRQHandler
+WAKEUP_PIN_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h747xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h747xx.s new file mode 100644 index 0000000..5ace82f --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h747xx.s @@ -0,0 +1,621 @@ +;********************************************************************************
+;* File Name : startup_stm32h747xx.s
+;* @author MCD Application Team
+;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it, wwdg2_it)
+ DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4
+ DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_IRQHandler ; DCMI
+ DCD 0 ; Reserved
+ DCD RNG_IRQHandler ; Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD QUADSPI_IRQHandler ; QUADSPI
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
+ DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
+ DCD OTG_FS_IRQHandler ; USB OTG FS
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
+ DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
+ DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
+ DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
+ DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
+ DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
+ DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD SAI3_IRQHandler ; SAI3 global Interrupt
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD JPEG_IRQHandler ; JPEG global Interrupt
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD DSI_IRQHandler ; DSI global Interrupt
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD HSEM2_IRQHandler ; HSEM2 global Interrupt
+ DCD ADC3_IRQHandler ; ADC3 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP1_IRQHandler ; COMP1 global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
+ DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it)
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
+ DCD SAI4_IRQHandler ; SAI4 global interrupt
+ DCD 0 ; Reserved
+ DCD HOLD_CORE_IRQHandler ; Hold core interrupt
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_AVD_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream0_IRQHandler [WEAK]
+ EXPORT DMA1_Stream1_IRQHandler [WEAK]
+ EXPORT DMA1_Stream2_IRQHandler [WEAK]
+ EXPORT DMA1_Stream3_IRQHandler [WEAK]
+ EXPORT DMA1_Stream4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream5_IRQHandler [WEAK]
+ EXPORT DMA1_Stream6_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT1_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT1_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
+ EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT SDMMC1_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Stream0_IRQHandler [WEAK]
+ EXPORT DMA2_Stream1_IRQHandler [WEAK]
+ EXPORT DMA2_Stream2_IRQHandler [WEAK]
+ EXPORT DMA2_Stream3_IRQHandler [WEAK]
+ EXPORT DMA2_Stream4_IRQHandler [WEAK]
+ EXPORT ETH_IRQHandler [WEAK]
+ EXPORT ETH_WKUP_IRQHandler [WEAK]
+ EXPORT FDCAN_CAL_IRQHandler [WEAK]
+ EXPORT CM7_SEV_IRQHandler [WEAK]
+ EXPORT CM4_SEV_IRQHandler [WEAK]
+ EXPORT DMA2_Stream5_IRQHandler [WEAK]
+ EXPORT DMA2_Stream6_IRQHandler [WEAK]
+ EXPORT DMA2_Stream7_IRQHandler [WEAK]
+ EXPORT USART6_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_HS_IRQHandler [WEAK]
+ EXPORT DCMI_IRQHandler [WEAK]
+ EXPORT RNG_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT UART7_IRQHandler [WEAK]
+ EXPORT UART8_IRQHandler [WEAK]
+ EXPORT SPI4_IRQHandler [WEAK]
+ EXPORT SPI5_IRQHandler [WEAK]
+ EXPORT SPI6_IRQHandler [WEAK]
+ EXPORT SAI1_IRQHandler [WEAK]
+ EXPORT LTDC_IRQHandler [WEAK]
+ EXPORT LTDC_ER_IRQHandler [WEAK]
+ EXPORT DMA2D_IRQHandler [WEAK]
+ EXPORT SAI2_IRQHandler [WEAK]
+ EXPORT QUADSPI_IRQHandler [WEAK]
+ EXPORT LPTIM1_IRQHandler [WEAK]
+ EXPORT CEC_IRQHandler [WEAK]
+ EXPORT I2C4_EV_IRQHandler [WEAK]
+ EXPORT I2C4_ER_IRQHandler [WEAK]
+ EXPORT SPDIF_RX_IRQHandler [WEAK]
+ EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_FS_IRQHandler [WEAK]
+ EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
+ EXPORT HRTIM1_Master_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIME_IRQHandler [WEAK]
+ EXPORT HRTIM1_FLT_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
+ EXPORT SAI3_IRQHandler [WEAK]
+ EXPORT SWPMI1_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT MDIOS_WKUP_IRQHandler [WEAK]
+ EXPORT MDIOS_IRQHandler [WEAK]
+ EXPORT JPEG_IRQHandler [WEAK]
+ EXPORT MDMA_IRQHandler [WEAK]
+ EXPORT DSI_IRQHandler [WEAK]
+ EXPORT SDMMC2_IRQHandler [WEAK]
+ EXPORT HSEM1_IRQHandler [WEAK]
+ EXPORT HSEM2_IRQHandler [WEAK]
+ EXPORT ADC3_IRQHandler [WEAK]
+ EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
+ EXPORT BDMA_Channel0_IRQHandler [WEAK]
+ EXPORT BDMA_Channel1_IRQHandler [WEAK]
+ EXPORT BDMA_Channel2_IRQHandler [WEAK]
+ EXPORT BDMA_Channel3_IRQHandler [WEAK]
+ EXPORT BDMA_Channel4_IRQHandler [WEAK]
+ EXPORT BDMA_Channel5_IRQHandler [WEAK]
+ EXPORT BDMA_Channel6_IRQHandler [WEAK]
+ EXPORT BDMA_Channel7_IRQHandler [WEAK]
+ EXPORT COMP1_IRQHandler [WEAK]
+ EXPORT LPTIM2_IRQHandler [WEAK]
+ EXPORT LPTIM3_IRQHandler [WEAK]
+ EXPORT LPTIM4_IRQHandler [WEAK]
+ EXPORT LPTIM5_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT WWDG_RST_IRQHandler [WEAK]
+ EXPORT CRS_IRQHandler [WEAK]
+ EXPORT ECC_IRQHandler [WEAK]
+ EXPORT SAI4_IRQHandler [WEAK]
+ EXPORT HOLD_CORE_IRQHandler [WEAK]
+ EXPORT WAKEUP_PIN_IRQHandler [WEAK]
+
+
+WWDG_IRQHandler
+PVD_AVD_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler
+DMA1_Stream2_IRQHandler
+DMA1_Stream3_IRQHandler
+DMA1_Stream4_IRQHandler
+DMA1_Stream5_IRQHandler
+DMA1_Stream6_IRQHandler
+ADC_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+FDCAN2_IT1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+TIM8_BRK_TIM12_IRQHandler
+TIM8_UP_TIM13_IRQHandler
+TIM8_TRG_COM_TIM14_IRQHandler
+TIM8_CC_IRQHandler
+DMA1_Stream7_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Stream0_IRQHandler
+DMA2_Stream1_IRQHandler
+DMA2_Stream2_IRQHandler
+DMA2_Stream3_IRQHandler
+DMA2_Stream4_IRQHandler
+ETH_IRQHandler
+ETH_WKUP_IRQHandler
+FDCAN_CAL_IRQHandler
+CM7_SEV_IRQHandler
+CM4_SEV_IRQHandler
+DMA2_Stream5_IRQHandler
+DMA2_Stream6_IRQHandler
+DMA2_Stream7_IRQHandler
+USART6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+OTG_HS_EP1_OUT_IRQHandler
+OTG_HS_EP1_IN_IRQHandler
+OTG_HS_WKUP_IRQHandler
+OTG_HS_IRQHandler
+DCMI_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+SAI1_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+DMA2D_IRQHandler
+SAI2_IRQHandler
+QUADSPI_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+OTG_FS_EP1_OUT_IRQHandler
+OTG_FS_EP1_IN_IRQHandler
+OTG_FS_WKUP_IRQHandler
+OTG_FS_IRQHandler
+DMAMUX1_OVR_IRQHandler
+HRTIM1_Master_IRQHandler
+HRTIM1_TIMA_IRQHandler
+HRTIM1_TIMB_IRQHandler
+HRTIM1_TIMC_IRQHandler
+HRTIM1_TIMD_IRQHandler
+HRTIM1_TIME_IRQHandler
+HRTIM1_FLT_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+DFSDM1_FLT3_IRQHandler
+SAI3_IRQHandler
+SWPMI1_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+MDIOS_WKUP_IRQHandler
+MDIOS_IRQHandler
+JPEG_IRQHandler
+MDMA_IRQHandler
+DSI_IRQHandler
+SDMMC2_IRQHandler
+HSEM1_IRQHandler
+HSEM2_IRQHandler
+ADC3_IRQHandler
+DMAMUX2_OVR_IRQHandler
+BDMA_Channel0_IRQHandler
+BDMA_Channel1_IRQHandler
+BDMA_Channel2_IRQHandler
+BDMA_Channel3_IRQHandler
+BDMA_Channel4_IRQHandler
+BDMA_Channel5_IRQHandler
+BDMA_Channel6_IRQHandler
+BDMA_Channel7_IRQHandler
+COMP1_IRQHandler
+LPTIM2_IRQHandler
+LPTIM3_IRQHandler
+LPTIM4_IRQHandler
+LPTIM5_IRQHandler
+LPUART1_IRQHandler
+WWDG_RST_IRQHandler
+CRS_IRQHandler
+ECC_IRQHandler
+SAI4_IRQHandler
+HOLD_CORE_IRQHandler
+WAKEUP_PIN_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h750xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h750xx.s new file mode 100644 index 0000000..6586e3d --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h750xx.s @@ -0,0 +1,611 @@ +;********************************************************************************
+;* File Name : startup_stm32h750xx.s
+;* @author MCD Application Team
+;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2018 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it)
+ DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_IRQHandler ; DCMI
+ DCD CRYP_IRQHandler ; CRYP crypto
+ DCD HASH_RNG_IRQHandler ; Hash and Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD QUADSPI_IRQHandler ; QUADSPI
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
+ DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
+ DCD OTG_FS_IRQHandler ; USB OTG FS
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
+ DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
+ DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
+ DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
+ DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
+ DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
+ DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD SAI3_IRQHandler ; SAI3 global Interrupt
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD JPEG_IRQHandler ; JPEG global Interrupt
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD 0 ; Reserved
+ DCD ADC3_IRQHandler ; ADC3 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP1_IRQHandler ; COMP1 global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
+ DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD 0 ; Reserved
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
+ DCD SAI4_IRQHandler ; SAI4 global interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_AVD_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream0_IRQHandler [WEAK]
+ EXPORT DMA1_Stream1_IRQHandler [WEAK]
+ EXPORT DMA1_Stream2_IRQHandler [WEAK]
+ EXPORT DMA1_Stream3_IRQHandler [WEAK]
+ EXPORT DMA1_Stream4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream5_IRQHandler [WEAK]
+ EXPORT DMA1_Stream6_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT1_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT1_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
+ EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT SDMMC1_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Stream0_IRQHandler [WEAK]
+ EXPORT DMA2_Stream1_IRQHandler [WEAK]
+ EXPORT DMA2_Stream2_IRQHandler [WEAK]
+ EXPORT DMA2_Stream3_IRQHandler [WEAK]
+ EXPORT DMA2_Stream4_IRQHandler [WEAK]
+ EXPORT ETH_IRQHandler [WEAK]
+ EXPORT ETH_WKUP_IRQHandler [WEAK]
+ EXPORT FDCAN_CAL_IRQHandler [WEAK]
+ EXPORT DMA2_Stream5_IRQHandler [WEAK]
+ EXPORT DMA2_Stream6_IRQHandler [WEAK]
+ EXPORT DMA2_Stream7_IRQHandler [WEAK]
+ EXPORT USART6_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_HS_IRQHandler [WEAK]
+ EXPORT DCMI_IRQHandler [WEAK]
+ EXPORT CRYP_IRQHandler [WEAK]
+ EXPORT HASH_RNG_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT UART7_IRQHandler [WEAK]
+ EXPORT UART8_IRQHandler [WEAK]
+ EXPORT SPI4_IRQHandler [WEAK]
+ EXPORT SPI5_IRQHandler [WEAK]
+ EXPORT SPI6_IRQHandler [WEAK]
+ EXPORT SAI1_IRQHandler [WEAK]
+ EXPORT LTDC_IRQHandler [WEAK]
+ EXPORT LTDC_ER_IRQHandler [WEAK]
+ EXPORT DMA2D_IRQHandler [WEAK]
+ EXPORT SAI2_IRQHandler [WEAK]
+ EXPORT QUADSPI_IRQHandler [WEAK]
+ EXPORT LPTIM1_IRQHandler [WEAK]
+ EXPORT CEC_IRQHandler [WEAK]
+ EXPORT I2C4_EV_IRQHandler [WEAK]
+ EXPORT I2C4_ER_IRQHandler [WEAK]
+ EXPORT SPDIF_RX_IRQHandler [WEAK]
+ EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_FS_IRQHandler [WEAK]
+ EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
+ EXPORT HRTIM1_Master_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIME_IRQHandler [WEAK]
+ EXPORT HRTIM1_FLT_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
+ EXPORT SAI3_IRQHandler [WEAK]
+ EXPORT SWPMI1_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT MDIOS_WKUP_IRQHandler [WEAK]
+ EXPORT MDIOS_IRQHandler [WEAK]
+ EXPORT JPEG_IRQHandler [WEAK]
+ EXPORT MDMA_IRQHandler [WEAK]
+ EXPORT SDMMC2_IRQHandler [WEAK]
+ EXPORT HSEM1_IRQHandler [WEAK]
+ EXPORT ADC3_IRQHandler [WEAK]
+ EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
+ EXPORT BDMA_Channel0_IRQHandler [WEAK]
+ EXPORT BDMA_Channel1_IRQHandler [WEAK]
+ EXPORT BDMA_Channel2_IRQHandler [WEAK]
+ EXPORT BDMA_Channel3_IRQHandler [WEAK]
+ EXPORT BDMA_Channel4_IRQHandler [WEAK]
+ EXPORT BDMA_Channel5_IRQHandler [WEAK]
+ EXPORT BDMA_Channel6_IRQHandler [WEAK]
+ EXPORT BDMA_Channel7_IRQHandler [WEAK]
+ EXPORT COMP1_IRQHandler [WEAK]
+ EXPORT LPTIM2_IRQHandler [WEAK]
+ EXPORT LPTIM3_IRQHandler [WEAK]
+ EXPORT LPTIM4_IRQHandler [WEAK]
+ EXPORT LPTIM5_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT CRS_IRQHandler [WEAK]
+ EXPORT ECC_IRQHandler [WEAK]
+ EXPORT SAI4_IRQHandler [WEAK]
+ EXPORT WAKEUP_PIN_IRQHandler [WEAK]
+
+
+WWDG_IRQHandler
+PVD_AVD_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler
+DMA1_Stream2_IRQHandler
+DMA1_Stream3_IRQHandler
+DMA1_Stream4_IRQHandler
+DMA1_Stream5_IRQHandler
+DMA1_Stream6_IRQHandler
+ADC_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+FDCAN2_IT1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+TIM8_BRK_TIM12_IRQHandler
+TIM8_UP_TIM13_IRQHandler
+TIM8_TRG_COM_TIM14_IRQHandler
+TIM8_CC_IRQHandler
+DMA1_Stream7_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Stream0_IRQHandler
+DMA2_Stream1_IRQHandler
+DMA2_Stream2_IRQHandler
+DMA2_Stream3_IRQHandler
+DMA2_Stream4_IRQHandler
+ETH_IRQHandler
+ETH_WKUP_IRQHandler
+FDCAN_CAL_IRQHandler
+DMA2_Stream5_IRQHandler
+DMA2_Stream6_IRQHandler
+DMA2_Stream7_IRQHandler
+USART6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+OTG_HS_EP1_OUT_IRQHandler
+OTG_HS_EP1_IN_IRQHandler
+OTG_HS_WKUP_IRQHandler
+OTG_HS_IRQHandler
+DCMI_IRQHandler
+CRYP_IRQHandler
+HASH_RNG_IRQHandler
+FPU_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+SAI1_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+DMA2D_IRQHandler
+SAI2_IRQHandler
+QUADSPI_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+OTG_FS_EP1_OUT_IRQHandler
+OTG_FS_EP1_IN_IRQHandler
+OTG_FS_WKUP_IRQHandler
+OTG_FS_IRQHandler
+DMAMUX1_OVR_IRQHandler
+HRTIM1_Master_IRQHandler
+HRTIM1_TIMA_IRQHandler
+HRTIM1_TIMB_IRQHandler
+HRTIM1_TIMC_IRQHandler
+HRTIM1_TIMD_IRQHandler
+HRTIM1_TIME_IRQHandler
+HRTIM1_FLT_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+DFSDM1_FLT3_IRQHandler
+SAI3_IRQHandler
+SWPMI1_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+MDIOS_WKUP_IRQHandler
+MDIOS_IRQHandler
+JPEG_IRQHandler
+MDMA_IRQHandler
+SDMMC2_IRQHandler
+HSEM1_IRQHandler
+ADC3_IRQHandler
+DMAMUX2_OVR_IRQHandler
+BDMA_Channel0_IRQHandler
+BDMA_Channel1_IRQHandler
+BDMA_Channel2_IRQHandler
+BDMA_Channel3_IRQHandler
+BDMA_Channel4_IRQHandler
+BDMA_Channel5_IRQHandler
+BDMA_Channel6_IRQHandler
+BDMA_Channel7_IRQHandler
+COMP1_IRQHandler
+LPTIM2_IRQHandler
+LPTIM3_IRQHandler
+LPTIM4_IRQHandler
+LPTIM5_IRQHandler
+LPUART1_IRQHandler
+CRS_IRQHandler
+ECC_IRQHandler
+SAI4_IRQHandler
+WAKEUP_PIN_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h753xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h753xx.s new file mode 100644 index 0000000..3e385e3 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h753xx.s @@ -0,0 +1,611 @@ +;********************************************************************************
+;* File Name : startup_stm32h753xx.s
+;* @author MCD Application Team
+;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it)
+ DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_IRQHandler ; DCMI
+ DCD CRYP_IRQHandler ; CRYP crypto
+ DCD HASH_RNG_IRQHandler ; Hash and Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD QUADSPI_IRQHandler ; QUADSPI
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
+ DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
+ DCD OTG_FS_IRQHandler ; USB OTG FS
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
+ DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
+ DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
+ DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
+ DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
+ DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
+ DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD SAI3_IRQHandler ; SAI3 global Interrupt
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD JPEG_IRQHandler ; JPEG global Interrupt
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD 0 ; Reserved
+ DCD ADC3_IRQHandler ; ADC3 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP1_IRQHandler ; COMP1 global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
+ DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD 0 ; Reserved
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
+ DCD SAI4_IRQHandler ; SAI4 global interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_AVD_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream0_IRQHandler [WEAK]
+ EXPORT DMA1_Stream1_IRQHandler [WEAK]
+ EXPORT DMA1_Stream2_IRQHandler [WEAK]
+ EXPORT DMA1_Stream3_IRQHandler [WEAK]
+ EXPORT DMA1_Stream4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream5_IRQHandler [WEAK]
+ EXPORT DMA1_Stream6_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT1_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT1_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
+ EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT SDMMC1_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Stream0_IRQHandler [WEAK]
+ EXPORT DMA2_Stream1_IRQHandler [WEAK]
+ EXPORT DMA2_Stream2_IRQHandler [WEAK]
+ EXPORT DMA2_Stream3_IRQHandler [WEAK]
+ EXPORT DMA2_Stream4_IRQHandler [WEAK]
+ EXPORT ETH_IRQHandler [WEAK]
+ EXPORT ETH_WKUP_IRQHandler [WEAK]
+ EXPORT FDCAN_CAL_IRQHandler [WEAK]
+ EXPORT DMA2_Stream5_IRQHandler [WEAK]
+ EXPORT DMA2_Stream6_IRQHandler [WEAK]
+ EXPORT DMA2_Stream7_IRQHandler [WEAK]
+ EXPORT USART6_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_HS_IRQHandler [WEAK]
+ EXPORT DCMI_IRQHandler [WEAK]
+ EXPORT CRYP_IRQHandler [WEAK]
+ EXPORT HASH_RNG_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT UART7_IRQHandler [WEAK]
+ EXPORT UART8_IRQHandler [WEAK]
+ EXPORT SPI4_IRQHandler [WEAK]
+ EXPORT SPI5_IRQHandler [WEAK]
+ EXPORT SPI6_IRQHandler [WEAK]
+ EXPORT SAI1_IRQHandler [WEAK]
+ EXPORT LTDC_IRQHandler [WEAK]
+ EXPORT LTDC_ER_IRQHandler [WEAK]
+ EXPORT DMA2D_IRQHandler [WEAK]
+ EXPORT SAI2_IRQHandler [WEAK]
+ EXPORT QUADSPI_IRQHandler [WEAK]
+ EXPORT LPTIM1_IRQHandler [WEAK]
+ EXPORT CEC_IRQHandler [WEAK]
+ EXPORT I2C4_EV_IRQHandler [WEAK]
+ EXPORT I2C4_ER_IRQHandler [WEAK]
+ EXPORT SPDIF_RX_IRQHandler [WEAK]
+ EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_FS_IRQHandler [WEAK]
+ EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
+ EXPORT HRTIM1_Master_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIME_IRQHandler [WEAK]
+ EXPORT HRTIM1_FLT_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
+ EXPORT SAI3_IRQHandler [WEAK]
+ EXPORT SWPMI1_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT MDIOS_WKUP_IRQHandler [WEAK]
+ EXPORT MDIOS_IRQHandler [WEAK]
+ EXPORT JPEG_IRQHandler [WEAK]
+ EXPORT MDMA_IRQHandler [WEAK]
+ EXPORT SDMMC2_IRQHandler [WEAK]
+ EXPORT HSEM1_IRQHandler [WEAK]
+ EXPORT ADC3_IRQHandler [WEAK]
+ EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
+ EXPORT BDMA_Channel0_IRQHandler [WEAK]
+ EXPORT BDMA_Channel1_IRQHandler [WEAK]
+ EXPORT BDMA_Channel2_IRQHandler [WEAK]
+ EXPORT BDMA_Channel3_IRQHandler [WEAK]
+ EXPORT BDMA_Channel4_IRQHandler [WEAK]
+ EXPORT BDMA_Channel5_IRQHandler [WEAK]
+ EXPORT BDMA_Channel6_IRQHandler [WEAK]
+ EXPORT BDMA_Channel7_IRQHandler [WEAK]
+ EXPORT COMP1_IRQHandler [WEAK]
+ EXPORT LPTIM2_IRQHandler [WEAK]
+ EXPORT LPTIM3_IRQHandler [WEAK]
+ EXPORT LPTIM4_IRQHandler [WEAK]
+ EXPORT LPTIM5_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT CRS_IRQHandler [WEAK]
+ EXPORT ECC_IRQHandler [WEAK]
+ EXPORT SAI4_IRQHandler [WEAK]
+ EXPORT WAKEUP_PIN_IRQHandler [WEAK]
+
+
+WWDG_IRQHandler
+PVD_AVD_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler
+DMA1_Stream2_IRQHandler
+DMA1_Stream3_IRQHandler
+DMA1_Stream4_IRQHandler
+DMA1_Stream5_IRQHandler
+DMA1_Stream6_IRQHandler
+ADC_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+FDCAN2_IT1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+TIM8_BRK_TIM12_IRQHandler
+TIM8_UP_TIM13_IRQHandler
+TIM8_TRG_COM_TIM14_IRQHandler
+TIM8_CC_IRQHandler
+DMA1_Stream7_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Stream0_IRQHandler
+DMA2_Stream1_IRQHandler
+DMA2_Stream2_IRQHandler
+DMA2_Stream3_IRQHandler
+DMA2_Stream4_IRQHandler
+ETH_IRQHandler
+ETH_WKUP_IRQHandler
+FDCAN_CAL_IRQHandler
+DMA2_Stream5_IRQHandler
+DMA2_Stream6_IRQHandler
+DMA2_Stream7_IRQHandler
+USART6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+OTG_HS_EP1_OUT_IRQHandler
+OTG_HS_EP1_IN_IRQHandler
+OTG_HS_WKUP_IRQHandler
+OTG_HS_IRQHandler
+DCMI_IRQHandler
+CRYP_IRQHandler
+HASH_RNG_IRQHandler
+FPU_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+SAI1_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+DMA2D_IRQHandler
+SAI2_IRQHandler
+QUADSPI_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+OTG_FS_EP1_OUT_IRQHandler
+OTG_FS_EP1_IN_IRQHandler
+OTG_FS_WKUP_IRQHandler
+OTG_FS_IRQHandler
+DMAMUX1_OVR_IRQHandler
+HRTIM1_Master_IRQHandler
+HRTIM1_TIMA_IRQHandler
+HRTIM1_TIMB_IRQHandler
+HRTIM1_TIMC_IRQHandler
+HRTIM1_TIMD_IRQHandler
+HRTIM1_TIME_IRQHandler
+HRTIM1_FLT_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+DFSDM1_FLT3_IRQHandler
+SAI3_IRQHandler
+SWPMI1_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+MDIOS_WKUP_IRQHandler
+MDIOS_IRQHandler
+JPEG_IRQHandler
+MDMA_IRQHandler
+SDMMC2_IRQHandler
+HSEM1_IRQHandler
+ADC3_IRQHandler
+DMAMUX2_OVR_IRQHandler
+BDMA_Channel0_IRQHandler
+BDMA_Channel1_IRQHandler
+BDMA_Channel2_IRQHandler
+BDMA_Channel3_IRQHandler
+BDMA_Channel4_IRQHandler
+BDMA_Channel5_IRQHandler
+BDMA_Channel6_IRQHandler
+BDMA_Channel7_IRQHandler
+COMP1_IRQHandler
+LPTIM2_IRQHandler
+LPTIM3_IRQHandler
+LPTIM4_IRQHandler
+LPTIM5_IRQHandler
+LPUART1_IRQHandler
+CRS_IRQHandler
+ECC_IRQHandler
+SAI4_IRQHandler
+WAKEUP_PIN_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h755xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h755xx.s new file mode 100644 index 0000000..4764a09 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h755xx.s @@ -0,0 +1,621 @@ +;********************************************************************************
+;* File Name : startup_stm32h755xx.s
+;* @author MCD Application Team
+;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it, wwdg2_it)
+ DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4
+ DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_IRQHandler ; DCMI
+ DCD CRYP_IRQHandler ; CRYP crypto
+ DCD HASH_RNG_IRQHandler ; Hash and Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD QUADSPI_IRQHandler ; QUADSPI
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
+ DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
+ DCD OTG_FS_IRQHandler ; USB OTG FS
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
+ DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
+ DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
+ DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
+ DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
+ DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
+ DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD SAI3_IRQHandler ; SAI3 global Interrupt
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD JPEG_IRQHandler ; JPEG global Interrupt
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD HSEM2_IRQHandler ; HSEM2 global Interrupt
+ DCD ADC3_IRQHandler ; ADC3 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP1_IRQHandler ; COMP1 global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
+ DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it)
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
+ DCD SAI4_IRQHandler ; SAI4 global interrupt
+ DCD 0 ; Reserved
+ DCD HOLD_CORE_IRQHandler ; Hold core interrupt
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_AVD_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream0_IRQHandler [WEAK]
+ EXPORT DMA1_Stream1_IRQHandler [WEAK]
+ EXPORT DMA1_Stream2_IRQHandler [WEAK]
+ EXPORT DMA1_Stream3_IRQHandler [WEAK]
+ EXPORT DMA1_Stream4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream5_IRQHandler [WEAK]
+ EXPORT DMA1_Stream6_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT1_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT1_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
+ EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT SDMMC1_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Stream0_IRQHandler [WEAK]
+ EXPORT DMA2_Stream1_IRQHandler [WEAK]
+ EXPORT DMA2_Stream2_IRQHandler [WEAK]
+ EXPORT DMA2_Stream3_IRQHandler [WEAK]
+ EXPORT DMA2_Stream4_IRQHandler [WEAK]
+ EXPORT ETH_IRQHandler [WEAK]
+ EXPORT ETH_WKUP_IRQHandler [WEAK]
+ EXPORT FDCAN_CAL_IRQHandler [WEAK]
+ EXPORT CM7_SEV_IRQHandler [WEAK]
+ EXPORT CM4_SEV_IRQHandler [WEAK]
+ EXPORT DMA2_Stream5_IRQHandler [WEAK]
+ EXPORT DMA2_Stream6_IRQHandler [WEAK]
+ EXPORT DMA2_Stream7_IRQHandler [WEAK]
+ EXPORT USART6_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_HS_IRQHandler [WEAK]
+ EXPORT DCMI_IRQHandler [WEAK]
+ EXPORT CRYP_IRQHandler [WEAK]
+ EXPORT HASH_RNG_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT UART7_IRQHandler [WEAK]
+ EXPORT UART8_IRQHandler [WEAK]
+ EXPORT SPI4_IRQHandler [WEAK]
+ EXPORT SPI5_IRQHandler [WEAK]
+ EXPORT SPI6_IRQHandler [WEAK]
+ EXPORT SAI1_IRQHandler [WEAK]
+ EXPORT LTDC_IRQHandler [WEAK]
+ EXPORT LTDC_ER_IRQHandler [WEAK]
+ EXPORT DMA2D_IRQHandler [WEAK]
+ EXPORT SAI2_IRQHandler [WEAK]
+ EXPORT QUADSPI_IRQHandler [WEAK]
+ EXPORT LPTIM1_IRQHandler [WEAK]
+ EXPORT CEC_IRQHandler [WEAK]
+ EXPORT I2C4_EV_IRQHandler [WEAK]
+ EXPORT I2C4_ER_IRQHandler [WEAK]
+ EXPORT SPDIF_RX_IRQHandler [WEAK]
+ EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_FS_IRQHandler [WEAK]
+ EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
+ EXPORT HRTIM1_Master_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIME_IRQHandler [WEAK]
+ EXPORT HRTIM1_FLT_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
+ EXPORT SAI3_IRQHandler [WEAK]
+ EXPORT SWPMI1_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT MDIOS_WKUP_IRQHandler [WEAK]
+ EXPORT MDIOS_IRQHandler [WEAK]
+ EXPORT JPEG_IRQHandler [WEAK]
+ EXPORT MDMA_IRQHandler [WEAK]
+ EXPORT SDMMC2_IRQHandler [WEAK]
+ EXPORT HSEM1_IRQHandler [WEAK]
+ EXPORT HSEM2_IRQHandler [WEAK]
+ EXPORT ADC3_IRQHandler [WEAK]
+ EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
+ EXPORT BDMA_Channel0_IRQHandler [WEAK]
+ EXPORT BDMA_Channel1_IRQHandler [WEAK]
+ EXPORT BDMA_Channel2_IRQHandler [WEAK]
+ EXPORT BDMA_Channel3_IRQHandler [WEAK]
+ EXPORT BDMA_Channel4_IRQHandler [WEAK]
+ EXPORT BDMA_Channel5_IRQHandler [WEAK]
+ EXPORT BDMA_Channel6_IRQHandler [WEAK]
+ EXPORT BDMA_Channel7_IRQHandler [WEAK]
+ EXPORT COMP1_IRQHandler [WEAK]
+ EXPORT LPTIM2_IRQHandler [WEAK]
+ EXPORT LPTIM3_IRQHandler [WEAK]
+ EXPORT LPTIM4_IRQHandler [WEAK]
+ EXPORT LPTIM5_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT WWDG_RST_IRQHandler [WEAK]
+ EXPORT CRS_IRQHandler [WEAK]
+ EXPORT ECC_IRQHandler [WEAK]
+ EXPORT SAI4_IRQHandler [WEAK]
+ EXPORT HOLD_CORE_IRQHandler [WEAK]
+ EXPORT WAKEUP_PIN_IRQHandler [WEAK]
+
+
+WWDG_IRQHandler
+PVD_AVD_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler
+DMA1_Stream2_IRQHandler
+DMA1_Stream3_IRQHandler
+DMA1_Stream4_IRQHandler
+DMA1_Stream5_IRQHandler
+DMA1_Stream6_IRQHandler
+ADC_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+FDCAN2_IT1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+TIM8_BRK_TIM12_IRQHandler
+TIM8_UP_TIM13_IRQHandler
+TIM8_TRG_COM_TIM14_IRQHandler
+TIM8_CC_IRQHandler
+DMA1_Stream7_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Stream0_IRQHandler
+DMA2_Stream1_IRQHandler
+DMA2_Stream2_IRQHandler
+DMA2_Stream3_IRQHandler
+DMA2_Stream4_IRQHandler
+ETH_IRQHandler
+ETH_WKUP_IRQHandler
+FDCAN_CAL_IRQHandler
+CM7_SEV_IRQHandler
+CM4_SEV_IRQHandler
+DMA2_Stream5_IRQHandler
+DMA2_Stream6_IRQHandler
+DMA2_Stream7_IRQHandler
+USART6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+OTG_HS_EP1_OUT_IRQHandler
+OTG_HS_EP1_IN_IRQHandler
+OTG_HS_WKUP_IRQHandler
+OTG_HS_IRQHandler
+DCMI_IRQHandler
+CRYP_IRQHandler
+HASH_RNG_IRQHandler
+FPU_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+SAI1_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+DMA2D_IRQHandler
+SAI2_IRQHandler
+QUADSPI_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+OTG_FS_EP1_OUT_IRQHandler
+OTG_FS_EP1_IN_IRQHandler
+OTG_FS_WKUP_IRQHandler
+OTG_FS_IRQHandler
+DMAMUX1_OVR_IRQHandler
+HRTIM1_Master_IRQHandler
+HRTIM1_TIMA_IRQHandler
+HRTIM1_TIMB_IRQHandler
+HRTIM1_TIMC_IRQHandler
+HRTIM1_TIMD_IRQHandler
+HRTIM1_TIME_IRQHandler
+HRTIM1_FLT_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+DFSDM1_FLT3_IRQHandler
+SAI3_IRQHandler
+SWPMI1_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+MDIOS_WKUP_IRQHandler
+MDIOS_IRQHandler
+JPEG_IRQHandler
+MDMA_IRQHandler
+SDMMC2_IRQHandler
+HSEM1_IRQHandler
+HSEM2_IRQHandler
+ADC3_IRQHandler
+DMAMUX2_OVR_IRQHandler
+BDMA_Channel0_IRQHandler
+BDMA_Channel1_IRQHandler
+BDMA_Channel2_IRQHandler
+BDMA_Channel3_IRQHandler
+BDMA_Channel4_IRQHandler
+BDMA_Channel5_IRQHandler
+BDMA_Channel6_IRQHandler
+BDMA_Channel7_IRQHandler
+COMP1_IRQHandler
+LPTIM2_IRQHandler
+LPTIM3_IRQHandler
+LPTIM4_IRQHandler
+LPTIM5_IRQHandler
+LPUART1_IRQHandler
+WWDG_RST_IRQHandler
+CRS_IRQHandler
+ECC_IRQHandler
+SAI4_IRQHandler
+HOLD_CORE_IRQHandler
+WAKEUP_PIN_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h757xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h757xx.s new file mode 100644 index 0000000..c5414e1 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h757xx.s @@ -0,0 +1,623 @@ +;********************************************************************************
+;* File Name : startup_stm32h757xx.s
+;* @author MCD Application Team
+;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it, wwdg2_it)
+ DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4
+ DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_IRQHandler ; DCMI
+ DCD CRYP_IRQHandler ; CRYP crypto
+ DCD HASH_RNG_IRQHandler ; Hash and Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD QUADSPI_IRQHandler ; QUADSPI
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
+ DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
+ DCD OTG_FS_IRQHandler ; USB OTG FS
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
+ DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
+ DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
+ DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
+ DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
+ DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
+ DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD SAI3_IRQHandler ; SAI3 global Interrupt
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD JPEG_IRQHandler ; JPEG global Interrupt
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD DSI_IRQHandler ; DSI global Interrupt
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD HSEM2_IRQHandler ; HSEM2 global Interrupt
+ DCD ADC3_IRQHandler ; ADC3 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP1_IRQHandler ; COMP1 global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
+ DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it)
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
+ DCD SAI4_IRQHandler ; SAI4 global interrupt
+ DCD 0 ; Reserved
+ DCD HOLD_CORE_IRQHandler ; Hold core interrupt
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_AVD_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream0_IRQHandler [WEAK]
+ EXPORT DMA1_Stream1_IRQHandler [WEAK]
+ EXPORT DMA1_Stream2_IRQHandler [WEAK]
+ EXPORT DMA1_Stream3_IRQHandler [WEAK]
+ EXPORT DMA1_Stream4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream5_IRQHandler [WEAK]
+ EXPORT DMA1_Stream6_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT1_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT1_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
+ EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT SDMMC1_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Stream0_IRQHandler [WEAK]
+ EXPORT DMA2_Stream1_IRQHandler [WEAK]
+ EXPORT DMA2_Stream2_IRQHandler [WEAK]
+ EXPORT DMA2_Stream3_IRQHandler [WEAK]
+ EXPORT DMA2_Stream4_IRQHandler [WEAK]
+ EXPORT ETH_IRQHandler [WEAK]
+ EXPORT ETH_WKUP_IRQHandler [WEAK]
+ EXPORT FDCAN_CAL_IRQHandler [WEAK]
+ EXPORT CM7_SEV_IRQHandler [WEAK]
+ EXPORT CM4_SEV_IRQHandler [WEAK]
+ EXPORT DMA2_Stream5_IRQHandler [WEAK]
+ EXPORT DMA2_Stream6_IRQHandler [WEAK]
+ EXPORT DMA2_Stream7_IRQHandler [WEAK]
+ EXPORT USART6_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_HS_IRQHandler [WEAK]
+ EXPORT DCMI_IRQHandler [WEAK]
+ EXPORT CRYP_IRQHandler [WEAK]
+ EXPORT HASH_RNG_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT UART7_IRQHandler [WEAK]
+ EXPORT UART8_IRQHandler [WEAK]
+ EXPORT SPI4_IRQHandler [WEAK]
+ EXPORT SPI5_IRQHandler [WEAK]
+ EXPORT SPI6_IRQHandler [WEAK]
+ EXPORT SAI1_IRQHandler [WEAK]
+ EXPORT LTDC_IRQHandler [WEAK]
+ EXPORT LTDC_ER_IRQHandler [WEAK]
+ EXPORT DMA2D_IRQHandler [WEAK]
+ EXPORT SAI2_IRQHandler [WEAK]
+ EXPORT QUADSPI_IRQHandler [WEAK]
+ EXPORT LPTIM1_IRQHandler [WEAK]
+ EXPORT CEC_IRQHandler [WEAK]
+ EXPORT I2C4_EV_IRQHandler [WEAK]
+ EXPORT I2C4_ER_IRQHandler [WEAK]
+ EXPORT SPDIF_RX_IRQHandler [WEAK]
+ EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_FS_IRQHandler [WEAK]
+ EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
+ EXPORT HRTIM1_Master_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMA_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMB_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMC_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIMD_IRQHandler [WEAK]
+ EXPORT HRTIM1_TIME_IRQHandler [WEAK]
+ EXPORT HRTIM1_FLT_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
+ EXPORT SAI3_IRQHandler [WEAK]
+ EXPORT SWPMI1_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT MDIOS_WKUP_IRQHandler [WEAK]
+ EXPORT MDIOS_IRQHandler [WEAK]
+ EXPORT JPEG_IRQHandler [WEAK]
+ EXPORT MDMA_IRQHandler [WEAK]
+ EXPORT DSI_IRQHandler [WEAK]
+ EXPORT SDMMC2_IRQHandler [WEAK]
+ EXPORT HSEM1_IRQHandler [WEAK]
+ EXPORT HSEM2_IRQHandler [WEAK]
+ EXPORT ADC3_IRQHandler [WEAK]
+ EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
+ EXPORT BDMA_Channel0_IRQHandler [WEAK]
+ EXPORT BDMA_Channel1_IRQHandler [WEAK]
+ EXPORT BDMA_Channel2_IRQHandler [WEAK]
+ EXPORT BDMA_Channel3_IRQHandler [WEAK]
+ EXPORT BDMA_Channel4_IRQHandler [WEAK]
+ EXPORT BDMA_Channel5_IRQHandler [WEAK]
+ EXPORT BDMA_Channel6_IRQHandler [WEAK]
+ EXPORT BDMA_Channel7_IRQHandler [WEAK]
+ EXPORT COMP1_IRQHandler [WEAK]
+ EXPORT LPTIM2_IRQHandler [WEAK]
+ EXPORT LPTIM3_IRQHandler [WEAK]
+ EXPORT LPTIM4_IRQHandler [WEAK]
+ EXPORT LPTIM5_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT WWDG_RST_IRQHandler [WEAK]
+ EXPORT CRS_IRQHandler [WEAK]
+ EXPORT ECC_IRQHandler [WEAK]
+ EXPORT SAI4_IRQHandler [WEAK]
+ EXPORT HOLD_CORE_IRQHandler [WEAK]
+ EXPORT WAKEUP_PIN_IRQHandler [WEAK]
+
+
+WWDG_IRQHandler
+PVD_AVD_IRQHandler
+TAMP_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler
+DMA1_Stream2_IRQHandler
+DMA1_Stream3_IRQHandler
+DMA1_Stream4_IRQHandler
+DMA1_Stream5_IRQHandler
+DMA1_Stream6_IRQHandler
+ADC_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+FDCAN2_IT1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+TIM8_BRK_TIM12_IRQHandler
+TIM8_UP_TIM13_IRQHandler
+TIM8_TRG_COM_TIM14_IRQHandler
+TIM8_CC_IRQHandler
+DMA1_Stream7_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Stream0_IRQHandler
+DMA2_Stream1_IRQHandler
+DMA2_Stream2_IRQHandler
+DMA2_Stream3_IRQHandler
+DMA2_Stream4_IRQHandler
+ETH_IRQHandler
+ETH_WKUP_IRQHandler
+FDCAN_CAL_IRQHandler
+CM7_SEV_IRQHandler
+CM4_SEV_IRQHandler
+DMA2_Stream5_IRQHandler
+DMA2_Stream6_IRQHandler
+DMA2_Stream7_IRQHandler
+USART6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+OTG_HS_EP1_OUT_IRQHandler
+OTG_HS_EP1_IN_IRQHandler
+OTG_HS_WKUP_IRQHandler
+OTG_HS_IRQHandler
+DCMI_IRQHandler
+CRYP_IRQHandler
+HASH_RNG_IRQHandler
+FPU_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+SAI1_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+DMA2D_IRQHandler
+SAI2_IRQHandler
+QUADSPI_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+OTG_FS_EP1_OUT_IRQHandler
+OTG_FS_EP1_IN_IRQHandler
+OTG_FS_WKUP_IRQHandler
+OTG_FS_IRQHandler
+DMAMUX1_OVR_IRQHandler
+HRTIM1_Master_IRQHandler
+HRTIM1_TIMA_IRQHandler
+HRTIM1_TIMB_IRQHandler
+HRTIM1_TIMC_IRQHandler
+HRTIM1_TIMD_IRQHandler
+HRTIM1_TIME_IRQHandler
+HRTIM1_FLT_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+DFSDM1_FLT3_IRQHandler
+SAI3_IRQHandler
+SWPMI1_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+MDIOS_WKUP_IRQHandler
+MDIOS_IRQHandler
+JPEG_IRQHandler
+MDMA_IRQHandler
+DSI_IRQHandler
+SDMMC2_IRQHandler
+HSEM1_IRQHandler
+HSEM2_IRQHandler
+ADC3_IRQHandler
+DMAMUX2_OVR_IRQHandler
+BDMA_Channel0_IRQHandler
+BDMA_Channel1_IRQHandler
+BDMA_Channel2_IRQHandler
+BDMA_Channel3_IRQHandler
+BDMA_Channel4_IRQHandler
+BDMA_Channel5_IRQHandler
+BDMA_Channel6_IRQHandler
+BDMA_Channel7_IRQHandler
+COMP1_IRQHandler
+LPTIM2_IRQHandler
+LPTIM3_IRQHandler
+LPTIM4_IRQHandler
+LPTIM5_IRQHandler
+LPUART1_IRQHandler
+WWDG_RST_IRQHandler
+CRS_IRQHandler
+ECC_IRQHandler
+SAI4_IRQHandler
+HOLD_CORE_IRQHandler
+WAKEUP_PIN_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h7a3xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h7a3xx.s new file mode 100644 index 0000000..6fe6e05 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h7a3xx.s @@ -0,0 +1,602 @@ +;********************************************************************************
+;* File Name : startup_stm32h7a3xx.s
+;* @author MCD Application Team
+;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog interrupt
+ DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection
+ DCD RTC_TAMP_STAMP_CSS_LSE_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD DFSDM2_IRQHandler ; DFSDM2 Interrupt
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD DFSDM1_FLT4_IRQHandler ; DFSDM Filter4 Interrupt
+ DCD DFSDM1_FLT5_IRQHandler ; DFSDM Filter5 Interrupt
+ DCD DFSDM1_FLT6_IRQHandler ; DFSDM Filter6 Interrupt
+ DCD DFSDM1_FLT7_IRQHandler ; DFSDM Filter7 Interrupt
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_PSSI_IRQHandler ; DCMI,PSSI
+ DCD 0 ; Reserved
+ DCD RNG_IRQHandler ; Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD OCTOSPI1_IRQHandler ; OCTOSPI1
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD 0 ; Reserved
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD JPEG_IRQHandler ; JPEG global Interrupt
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD 0 ; Reserved
+ DCD DAC2_IRQHandler ; DAC2 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA2_Channel0_IRQHandler ; BDMA2 Channel 0 global Interrupt
+ DCD BDMA2_Channel1_IRQHandler ; BDMA2 Channel 1 global Interrupt
+ DCD BDMA2_Channel2_IRQHandler ; BDMA2 Channel 2 global Interrupt
+ DCD BDMA2_Channel3_IRQHandler ; BDMA2 Channel 3 global Interrupt
+ DCD BDMA2_Channel4_IRQHandler ; BDMA2 Channel 4 global Interrupt
+ DCD BDMA2_Channel5_IRQHandler ; BDMA2 Channel 5 global Interrupt
+ DCD BDMA2_Channel6_IRQHandler ; BDMA2 Channel 6 global Interrupt
+ DCD BDMA2_Channel7_IRQHandler ; BDMA2 Channel 7 global Interrupt
+ DCD COMP_IRQHandler ; COMP global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD UART9_IRQHandler ; UART9 global interrupt
+ DCD USART10_IRQHandler ; USART10 global interrupt
+ DCD LPUART1_IRQHandler ; LPUART1 interrupt
+ DCD 0 ; Reserved
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC_IRQHandler
+ DCD 0 ; Reserved
+ DCD DTS_IRQHandler ; DTS
+ DCD 0 ; Reserved
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+ DCD OCTOSPI2_IRQHandler ; OCTOSPI2
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD GFXMMU_IRQHandler ; GFXMMU
+ DCD BDMA1_IRQHandler ; BDMA1
+
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_PVM_IRQHandler [WEAK]
+ EXPORT RTC_TAMP_STAMP_CSS_LSE_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream0_IRQHandler [WEAK]
+ EXPORT DMA1_Stream1_IRQHandler [WEAK]
+ EXPORT DMA1_Stream2_IRQHandler [WEAK]
+ EXPORT DMA1_Stream3_IRQHandler [WEAK]
+ EXPORT DMA1_Stream4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream5_IRQHandler [WEAK]
+ EXPORT DMA1_Stream6_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT1_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT1_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT DFSDM2_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
+ EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT SDMMC1_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Stream0_IRQHandler [WEAK]
+ EXPORT DMA2_Stream1_IRQHandler [WEAK]
+ EXPORT DMA2_Stream2_IRQHandler [WEAK]
+ EXPORT DMA2_Stream3_IRQHandler [WEAK]
+ EXPORT DMA2_Stream4_IRQHandler [WEAK]
+ EXPORT FDCAN_CAL_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT4_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT5_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT6_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT7_IRQHandler [WEAK]
+ EXPORT DMA2_Stream5_IRQHandler [WEAK]
+ EXPORT DMA2_Stream6_IRQHandler [WEAK]
+ EXPORT DMA2_Stream7_IRQHandler [WEAK]
+ EXPORT USART6_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_HS_IRQHandler [WEAK]
+ EXPORT DCMI_PSSI_IRQHandler [WEAK]
+ EXPORT RNG_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT UART7_IRQHandler [WEAK]
+ EXPORT UART8_IRQHandler [WEAK]
+ EXPORT SPI4_IRQHandler [WEAK]
+ EXPORT SPI5_IRQHandler [WEAK]
+ EXPORT SPI6_IRQHandler [WEAK]
+ EXPORT SAI1_IRQHandler [WEAK]
+ EXPORT LTDC_IRQHandler [WEAK]
+ EXPORT LTDC_ER_IRQHandler [WEAK]
+ EXPORT DMA2D_IRQHandler [WEAK]
+ EXPORT SAI2_IRQHandler [WEAK]
+ EXPORT OCTOSPI1_IRQHandler [WEAK]
+ EXPORT LPTIM1_IRQHandler [WEAK]
+ EXPORT CEC_IRQHandler [WEAK]
+ EXPORT I2C4_EV_IRQHandler [WEAK]
+ EXPORT I2C4_ER_IRQHandler [WEAK]
+ EXPORT SPDIF_RX_IRQHandler [WEAK]
+ EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
+ EXPORT SWPMI1_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT MDIOS_WKUP_IRQHandler [WEAK]
+ EXPORT MDIOS_IRQHandler [WEAK]
+ EXPORT JPEG_IRQHandler [WEAK]
+ EXPORT MDMA_IRQHandler [WEAK]
+ EXPORT SDMMC2_IRQHandler [WEAK]
+ EXPORT HSEM1_IRQHandler [WEAK]
+ EXPORT DAC2_IRQHandler [WEAK]
+ EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel0_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel1_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel2_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel3_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel4_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel5_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel6_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel7_IRQHandler [WEAK]
+ EXPORT COMP_IRQHandler [WEAK]
+ EXPORT LPTIM2_IRQHandler [WEAK]
+ EXPORT LPTIM3_IRQHandler [WEAK]
+ EXPORT UART9_IRQHandler [WEAK]
+ EXPORT USART10_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT CRS_IRQHandler [WEAK]
+ EXPORT ECC_IRQHandler [WEAK]
+ EXPORT DTS_IRQHandler [WEAK]
+ EXPORT WAKEUP_PIN_IRQHandler [WEAK]
+ EXPORT OCTOSPI2_IRQHandler [WEAK]
+ EXPORT GFXMMU_IRQHandler [WEAK]
+ EXPORT BDMA1_IRQHandler [WEAK]
+
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler
+DMA1_Stream2_IRQHandler
+DMA1_Stream3_IRQHandler
+DMA1_Stream4_IRQHandler
+DMA1_Stream5_IRQHandler
+DMA1_Stream6_IRQHandler
+ADC_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+FDCAN2_IT1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+DFSDM2_IRQHandler
+TIM8_BRK_TIM12_IRQHandler
+TIM8_UP_TIM13_IRQHandler
+TIM8_TRG_COM_TIM14_IRQHandler
+TIM8_CC_IRQHandler
+DMA1_Stream7_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Stream0_IRQHandler
+DMA2_Stream1_IRQHandler
+DMA2_Stream2_IRQHandler
+DMA2_Stream3_IRQHandler
+DMA2_Stream4_IRQHandler
+FDCAN_CAL_IRQHandler
+DFSDM1_FLT4_IRQHandler
+DFSDM1_FLT5_IRQHandler
+DFSDM1_FLT6_IRQHandler
+DFSDM1_FLT7_IRQHandler
+DMA2_Stream5_IRQHandler
+DMA2_Stream6_IRQHandler
+DMA2_Stream7_IRQHandler
+USART6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+OTG_HS_EP1_OUT_IRQHandler
+OTG_HS_EP1_IN_IRQHandler
+OTG_HS_WKUP_IRQHandler
+OTG_HS_IRQHandler
+DCMI_PSSI_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+SAI1_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+DMA2D_IRQHandler
+SAI2_IRQHandler
+OCTOSPI1_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+DMAMUX1_OVR_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+DFSDM1_FLT3_IRQHandler
+SWPMI1_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+MDIOS_WKUP_IRQHandler
+MDIOS_IRQHandler
+JPEG_IRQHandler
+MDMA_IRQHandler
+SDMMC2_IRQHandler
+HSEM1_IRQHandler
+DAC2_IRQHandler
+DMAMUX2_OVR_IRQHandler
+BDMA2_Channel0_IRQHandler
+BDMA2_Channel1_IRQHandler
+BDMA2_Channel2_IRQHandler
+BDMA2_Channel3_IRQHandler
+BDMA2_Channel4_IRQHandler
+BDMA2_Channel5_IRQHandler
+BDMA2_Channel6_IRQHandler
+BDMA2_Channel7_IRQHandler
+COMP_IRQHandler
+LPTIM2_IRQHandler
+LPTIM3_IRQHandler
+UART9_IRQHandler
+USART10_IRQHandler
+LPUART1_IRQHandler
+CRS_IRQHandler
+ECC_IRQHandler
+DTS_IRQHandler
+WAKEUP_PIN_IRQHandler
+OCTOSPI2_IRQHandler
+GFXMMU_IRQHandler
+BDMA1_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h7a3xxq.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h7a3xxq.s new file mode 100644 index 0000000..a626d72 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h7a3xxq.s @@ -0,0 +1,602 @@ +;********************************************************************************
+;* File Name : startup_stm32h7a3xxq.s
+;* @author MCD Application Team
+;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog interrupt
+ DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection
+ DCD RTC_TAMP_STAMP_CSS_LSE_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD DFSDM2_IRQHandler ; DFSDM2 Interrupt
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD DFSDM1_FLT4_IRQHandler ; DFSDM Filter4 Interrupt
+ DCD DFSDM1_FLT5_IRQHandler ; DFSDM Filter5 Interrupt
+ DCD DFSDM1_FLT6_IRQHandler ; DFSDM Filter6 Interrupt
+ DCD DFSDM1_FLT7_IRQHandler ; DFSDM Filter7 Interrupt
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_PSSI_IRQHandler ; DCMI,PSSI
+ DCD 0 ; Reserved
+ DCD RNG_IRQHandler ; Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD OCTOSPI1_IRQHandler ; OCTOSPI1
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD 0 ; Reserved
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD JPEG_IRQHandler ; JPEG global Interrupt
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD 0 ; Reserved
+ DCD DAC2_IRQHandler ; DAC2 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA2_Channel0_IRQHandler ; BDMA2 Channel 0 global Interrupt
+ DCD BDMA2_Channel1_IRQHandler ; BDMA2 Channel 1 global Interrupt
+ DCD BDMA2_Channel2_IRQHandler ; BDMA2 Channel 2 global Interrupt
+ DCD BDMA2_Channel3_IRQHandler ; BDMA2 Channel 3 global Interrupt
+ DCD BDMA2_Channel4_IRQHandler ; BDMA2 Channel 4 global Interrupt
+ DCD BDMA2_Channel5_IRQHandler ; BDMA2 Channel 5 global Interrupt
+ DCD BDMA2_Channel6_IRQHandler ; BDMA2 Channel 6 global Interrupt
+ DCD BDMA2_Channel7_IRQHandler ; BDMA2 Channel 7 global Interrupt
+ DCD COMP_IRQHandler ; COMP global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD UART9_IRQHandler ; UART9 global interrupt
+ DCD USART10_IRQHandler ; USART10 global interrupt
+ DCD LPUART1_IRQHandler ; LPUART1 interrupt
+ DCD 0 ; Reserved
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC_IRQHandler
+ DCD 0 ; Reserved
+ DCD DTS_IRQHandler ; DTS
+ DCD 0 ; Reserved
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+ DCD OCTOSPI2_IRQHandler ; OCTOSPI2
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD GFXMMU_IRQHandler ; GFXMMU
+ DCD BDMA1_IRQHandler ; BDMA1
+
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_PVM_IRQHandler [WEAK]
+ EXPORT RTC_TAMP_STAMP_CSS_LSE_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream0_IRQHandler [WEAK]
+ EXPORT DMA1_Stream1_IRQHandler [WEAK]
+ EXPORT DMA1_Stream2_IRQHandler [WEAK]
+ EXPORT DMA1_Stream3_IRQHandler [WEAK]
+ EXPORT DMA1_Stream4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream5_IRQHandler [WEAK]
+ EXPORT DMA1_Stream6_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT1_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT1_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT DFSDM2_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
+ EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT SDMMC1_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Stream0_IRQHandler [WEAK]
+ EXPORT DMA2_Stream1_IRQHandler [WEAK]
+ EXPORT DMA2_Stream2_IRQHandler [WEAK]
+ EXPORT DMA2_Stream3_IRQHandler [WEAK]
+ EXPORT DMA2_Stream4_IRQHandler [WEAK]
+ EXPORT FDCAN_CAL_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT4_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT5_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT6_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT7_IRQHandler [WEAK]
+ EXPORT DMA2_Stream5_IRQHandler [WEAK]
+ EXPORT DMA2_Stream6_IRQHandler [WEAK]
+ EXPORT DMA2_Stream7_IRQHandler [WEAK]
+ EXPORT USART6_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_HS_IRQHandler [WEAK]
+ EXPORT DCMI_PSSI_IRQHandler [WEAK]
+ EXPORT RNG_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT UART7_IRQHandler [WEAK]
+ EXPORT UART8_IRQHandler [WEAK]
+ EXPORT SPI4_IRQHandler [WEAK]
+ EXPORT SPI5_IRQHandler [WEAK]
+ EXPORT SPI6_IRQHandler [WEAK]
+ EXPORT SAI1_IRQHandler [WEAK]
+ EXPORT LTDC_IRQHandler [WEAK]
+ EXPORT LTDC_ER_IRQHandler [WEAK]
+ EXPORT DMA2D_IRQHandler [WEAK]
+ EXPORT SAI2_IRQHandler [WEAK]
+ EXPORT OCTOSPI1_IRQHandler [WEAK]
+ EXPORT LPTIM1_IRQHandler [WEAK]
+ EXPORT CEC_IRQHandler [WEAK]
+ EXPORT I2C4_EV_IRQHandler [WEAK]
+ EXPORT I2C4_ER_IRQHandler [WEAK]
+ EXPORT SPDIF_RX_IRQHandler [WEAK]
+ EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
+ EXPORT SWPMI1_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT MDIOS_WKUP_IRQHandler [WEAK]
+ EXPORT MDIOS_IRQHandler [WEAK]
+ EXPORT JPEG_IRQHandler [WEAK]
+ EXPORT MDMA_IRQHandler [WEAK]
+ EXPORT SDMMC2_IRQHandler [WEAK]
+ EXPORT HSEM1_IRQHandler [WEAK]
+ EXPORT DAC2_IRQHandler [WEAK]
+ EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel0_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel1_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel2_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel3_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel4_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel5_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel6_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel7_IRQHandler [WEAK]
+ EXPORT COMP_IRQHandler [WEAK]
+ EXPORT LPTIM2_IRQHandler [WEAK]
+ EXPORT LPTIM3_IRQHandler [WEAK]
+ EXPORT UART9_IRQHandler [WEAK]
+ EXPORT USART10_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT CRS_IRQHandler [WEAK]
+ EXPORT ECC_IRQHandler [WEAK]
+ EXPORT DTS_IRQHandler [WEAK]
+ EXPORT WAKEUP_PIN_IRQHandler [WEAK]
+ EXPORT OCTOSPI2_IRQHandler [WEAK]
+ EXPORT GFXMMU_IRQHandler [WEAK]
+ EXPORT BDMA1_IRQHandler [WEAK]
+
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler
+DMA1_Stream2_IRQHandler
+DMA1_Stream3_IRQHandler
+DMA1_Stream4_IRQHandler
+DMA1_Stream5_IRQHandler
+DMA1_Stream6_IRQHandler
+ADC_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+FDCAN2_IT1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+DFSDM2_IRQHandler
+TIM8_BRK_TIM12_IRQHandler
+TIM8_UP_TIM13_IRQHandler
+TIM8_TRG_COM_TIM14_IRQHandler
+TIM8_CC_IRQHandler
+DMA1_Stream7_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Stream0_IRQHandler
+DMA2_Stream1_IRQHandler
+DMA2_Stream2_IRQHandler
+DMA2_Stream3_IRQHandler
+DMA2_Stream4_IRQHandler
+FDCAN_CAL_IRQHandler
+DFSDM1_FLT4_IRQHandler
+DFSDM1_FLT5_IRQHandler
+DFSDM1_FLT6_IRQHandler
+DFSDM1_FLT7_IRQHandler
+DMA2_Stream5_IRQHandler
+DMA2_Stream6_IRQHandler
+DMA2_Stream7_IRQHandler
+USART6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+OTG_HS_EP1_OUT_IRQHandler
+OTG_HS_EP1_IN_IRQHandler
+OTG_HS_WKUP_IRQHandler
+OTG_HS_IRQHandler
+DCMI_PSSI_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+SAI1_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+DMA2D_IRQHandler
+SAI2_IRQHandler
+OCTOSPI1_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+DMAMUX1_OVR_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+DFSDM1_FLT3_IRQHandler
+SWPMI1_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+MDIOS_WKUP_IRQHandler
+MDIOS_IRQHandler
+JPEG_IRQHandler
+MDMA_IRQHandler
+SDMMC2_IRQHandler
+HSEM1_IRQHandler
+DAC2_IRQHandler
+DMAMUX2_OVR_IRQHandler
+BDMA2_Channel0_IRQHandler
+BDMA2_Channel1_IRQHandler
+BDMA2_Channel2_IRQHandler
+BDMA2_Channel3_IRQHandler
+BDMA2_Channel4_IRQHandler
+BDMA2_Channel5_IRQHandler
+BDMA2_Channel6_IRQHandler
+BDMA2_Channel7_IRQHandler
+COMP_IRQHandler
+LPTIM2_IRQHandler
+LPTIM3_IRQHandler
+UART9_IRQHandler
+USART10_IRQHandler
+LPUART1_IRQHandler
+CRS_IRQHandler
+ECC_IRQHandler
+DTS_IRQHandler
+WAKEUP_PIN_IRQHandler
+OCTOSPI2_IRQHandler
+GFXMMU_IRQHandler
+BDMA1_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h7b0xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h7b0xx.s new file mode 100644 index 0000000..45aeb7a --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h7b0xx.s @@ -0,0 +1,608 @@ +;********************************************************************************
+;* File Name : startup_stm32h7b0xx.s
+;* @author MCD Application Team
+;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog interrupt
+ DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection
+ DCD RTC_TAMP_STAMP_CSS_LSE_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD DFSDM2_IRQHandler ; DFSDM2 Interrupt
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD DFSDM1_FLT4_IRQHandler ; DFSDM Filter4 Interrupt
+ DCD DFSDM1_FLT5_IRQHandler ; DFSDM Filter5 Interrupt
+ DCD DFSDM1_FLT6_IRQHandler ; DFSDM Filter6 Interrupt
+ DCD DFSDM1_FLT7_IRQHandler ; DFSDM Filter7 Interrupt
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_PSSI_IRQHandler ; DCMI,PSSI
+ DCD CRYP_IRQHandler ; CRYP crypto
+ DCD HASH_RNG_IRQHandler ; Hash and Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD OCTOSPI1_IRQHandler ; OCTOSPI1
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD 0 ; Reserved
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD JPEG_IRQHandler ; JPEG global Interrupt
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD 0 ; Reserved
+ DCD DAC2_IRQHandler ; DAC2 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA2_Channel0_IRQHandler ; BDMA2 Channel 0 global Interrupt
+ DCD BDMA2_Channel1_IRQHandler ; BDMA2 Channel 1 global Interrupt
+ DCD BDMA2_Channel2_IRQHandler ; BDMA2 Channel 2 global Interrupt
+ DCD BDMA2_Channel3_IRQHandler ; BDMA2 Channel 3 global Interrupt
+ DCD BDMA2_Channel4_IRQHandler ; BDMA2 Channel 4 global Interrupt
+ DCD BDMA2_Channel5_IRQHandler ; BDMA2 Channel 5 global Interrupt
+ DCD BDMA2_Channel6_IRQHandler ; BDMA2 Channel 6 global Interrupt
+ DCD BDMA2_Channel7_IRQHandler ; BDMA2 Channel 7 global Interrupt
+ DCD COMP_IRQHandler ; COMP global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD UART9_IRQHandler ; UART9 global interrupt
+ DCD USART10_IRQHandler ; USART10 global interrupt
+ DCD LPUART1_IRQHandler ; LPUART1 interrupt
+ DCD 0 ; Reserved
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC_IRQHandler
+ DCD 0 ; Reserved
+ DCD DTS_IRQHandler ; DTS
+ DCD 0 ; Reserved
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+ DCD OCTOSPI2_IRQHandler ; OCTOSPI2
+ DCD OTFDEC1_IRQHandler ; OTFDEC1
+ DCD OTFDEC2_IRQHandler ; OTFDEC2
+ DCD GFXMMU_IRQHandler ; GFXMMU
+ DCD BDMA1_IRQHandler ; BDMA1
+
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_PVM_IRQHandler [WEAK]
+ EXPORT RTC_TAMP_STAMP_CSS_LSE_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream0_IRQHandler [WEAK]
+ EXPORT DMA1_Stream1_IRQHandler [WEAK]
+ EXPORT DMA1_Stream2_IRQHandler [WEAK]
+ EXPORT DMA1_Stream3_IRQHandler [WEAK]
+ EXPORT DMA1_Stream4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream5_IRQHandler [WEAK]
+ EXPORT DMA1_Stream6_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT1_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT1_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT DFSDM2_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
+ EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT SDMMC1_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Stream0_IRQHandler [WEAK]
+ EXPORT DMA2_Stream1_IRQHandler [WEAK]
+ EXPORT DMA2_Stream2_IRQHandler [WEAK]
+ EXPORT DMA2_Stream3_IRQHandler [WEAK]
+ EXPORT DMA2_Stream4_IRQHandler [WEAK]
+ EXPORT FDCAN_CAL_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT4_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT5_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT6_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT7_IRQHandler [WEAK]
+ EXPORT DMA2_Stream5_IRQHandler [WEAK]
+ EXPORT DMA2_Stream6_IRQHandler [WEAK]
+ EXPORT DMA2_Stream7_IRQHandler [WEAK]
+ EXPORT USART6_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_HS_IRQHandler [WEAK]
+ EXPORT DCMI_PSSI_IRQHandler [WEAK]
+ EXPORT CRYP_IRQHandler [WEAK]
+ EXPORT HASH_RNG_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT UART7_IRQHandler [WEAK]
+ EXPORT UART8_IRQHandler [WEAK]
+ EXPORT SPI4_IRQHandler [WEAK]
+ EXPORT SPI5_IRQHandler [WEAK]
+ EXPORT SPI6_IRQHandler [WEAK]
+ EXPORT SAI1_IRQHandler [WEAK]
+ EXPORT LTDC_IRQHandler [WEAK]
+ EXPORT LTDC_ER_IRQHandler [WEAK]
+ EXPORT DMA2D_IRQHandler [WEAK]
+ EXPORT SAI2_IRQHandler [WEAK]
+ EXPORT OCTOSPI1_IRQHandler [WEAK]
+ EXPORT LPTIM1_IRQHandler [WEAK]
+ EXPORT CEC_IRQHandler [WEAK]
+ EXPORT I2C4_EV_IRQHandler [WEAK]
+ EXPORT I2C4_ER_IRQHandler [WEAK]
+ EXPORT SPDIF_RX_IRQHandler [WEAK]
+ EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
+ EXPORT SWPMI1_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT MDIOS_WKUP_IRQHandler [WEAK]
+ EXPORT MDIOS_IRQHandler [WEAK]
+ EXPORT JPEG_IRQHandler [WEAK]
+ EXPORT MDMA_IRQHandler [WEAK]
+ EXPORT SDMMC2_IRQHandler [WEAK]
+ EXPORT HSEM1_IRQHandler [WEAK]
+ EXPORT DAC2_IRQHandler [WEAK]
+ EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel0_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel1_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel2_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel3_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel4_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel5_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel6_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel7_IRQHandler [WEAK]
+ EXPORT COMP_IRQHandler [WEAK]
+ EXPORT LPTIM2_IRQHandler [WEAK]
+ EXPORT LPTIM3_IRQHandler [WEAK]
+ EXPORT UART9_IRQHandler [WEAK]
+ EXPORT USART10_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT CRS_IRQHandler [WEAK]
+ EXPORT ECC_IRQHandler [WEAK]
+ EXPORT DTS_IRQHandler [WEAK]
+ EXPORT WAKEUP_PIN_IRQHandler [WEAK]
+ EXPORT OCTOSPI2_IRQHandler [WEAK]
+ EXPORT OTFDEC1_IRQHandler [WEAK]
+ EXPORT OTFDEC2_IRQHandler [WEAK]
+ EXPORT GFXMMU_IRQHandler [WEAK]
+ EXPORT BDMA1_IRQHandler [WEAK]
+
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler
+DMA1_Stream2_IRQHandler
+DMA1_Stream3_IRQHandler
+DMA1_Stream4_IRQHandler
+DMA1_Stream5_IRQHandler
+DMA1_Stream6_IRQHandler
+ADC_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+FDCAN2_IT1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+DFSDM2_IRQHandler
+TIM8_BRK_TIM12_IRQHandler
+TIM8_UP_TIM13_IRQHandler
+TIM8_TRG_COM_TIM14_IRQHandler
+TIM8_CC_IRQHandler
+DMA1_Stream7_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Stream0_IRQHandler
+DMA2_Stream1_IRQHandler
+DMA2_Stream2_IRQHandler
+DMA2_Stream3_IRQHandler
+DMA2_Stream4_IRQHandler
+FDCAN_CAL_IRQHandler
+DFSDM1_FLT4_IRQHandler
+DFSDM1_FLT5_IRQHandler
+DFSDM1_FLT6_IRQHandler
+DFSDM1_FLT7_IRQHandler
+DMA2_Stream5_IRQHandler
+DMA2_Stream6_IRQHandler
+DMA2_Stream7_IRQHandler
+USART6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+OTG_HS_EP1_OUT_IRQHandler
+OTG_HS_EP1_IN_IRQHandler
+OTG_HS_WKUP_IRQHandler
+OTG_HS_IRQHandler
+DCMI_PSSI_IRQHandler
+CRYP_IRQHandler
+HASH_RNG_IRQHandler
+FPU_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+SAI1_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+DMA2D_IRQHandler
+SAI2_IRQHandler
+OCTOSPI1_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+DMAMUX1_OVR_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+DFSDM1_FLT3_IRQHandler
+SWPMI1_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+MDIOS_WKUP_IRQHandler
+MDIOS_IRQHandler
+JPEG_IRQHandler
+MDMA_IRQHandler
+SDMMC2_IRQHandler
+HSEM1_IRQHandler
+DAC2_IRQHandler
+DMAMUX2_OVR_IRQHandler
+BDMA2_Channel0_IRQHandler
+BDMA2_Channel1_IRQHandler
+BDMA2_Channel2_IRQHandler
+BDMA2_Channel3_IRQHandler
+BDMA2_Channel4_IRQHandler
+BDMA2_Channel5_IRQHandler
+BDMA2_Channel6_IRQHandler
+BDMA2_Channel7_IRQHandler
+COMP_IRQHandler
+LPTIM2_IRQHandler
+LPTIM3_IRQHandler
+UART9_IRQHandler
+USART10_IRQHandler
+LPUART1_IRQHandler
+CRS_IRQHandler
+ECC_IRQHandler
+DTS_IRQHandler
+WAKEUP_PIN_IRQHandler
+OCTOSPI2_IRQHandler
+OTFDEC1_IRQHandler
+OTFDEC2_IRQHandler
+GFXMMU_IRQHandler
+BDMA1_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h7b0xxq.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h7b0xxq.s new file mode 100644 index 0000000..9ed3702 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h7b0xxq.s @@ -0,0 +1,608 @@ +;********************************************************************************
+;* File Name : startup_stm32h7b0xxq.s
+;* @author MCD Application Team
+;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog interrupt
+ DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection
+ DCD RTC_TAMP_STAMP_CSS_LSE_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD DFSDM2_IRQHandler ; DFSDM2 Interrupt
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD DFSDM1_FLT4_IRQHandler ; DFSDM Filter4 Interrupt
+ DCD DFSDM1_FLT5_IRQHandler ; DFSDM Filter5 Interrupt
+ DCD DFSDM1_FLT6_IRQHandler ; DFSDM Filter6 Interrupt
+ DCD DFSDM1_FLT7_IRQHandler ; DFSDM Filter7 Interrupt
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_PSSI_IRQHandler ; DCMI,PSSI
+ DCD CRYP_IRQHandler ; CRYP crypto
+ DCD HASH_RNG_IRQHandler ; Hash and Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD OCTOSPI1_IRQHandler ; OCTOSPI1
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD 0 ; Reserved
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD JPEG_IRQHandler ; JPEG global Interrupt
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD 0 ; Reserved
+ DCD DAC2_IRQHandler ; DAC2 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA2_Channel0_IRQHandler ; BDMA2 Channel 0 global Interrupt
+ DCD BDMA2_Channel1_IRQHandler ; BDMA2 Channel 1 global Interrupt
+ DCD BDMA2_Channel2_IRQHandler ; BDMA2 Channel 2 global Interrupt
+ DCD BDMA2_Channel3_IRQHandler ; BDMA2 Channel 3 global Interrupt
+ DCD BDMA2_Channel4_IRQHandler ; BDMA2 Channel 4 global Interrupt
+ DCD BDMA2_Channel5_IRQHandler ; BDMA2 Channel 5 global Interrupt
+ DCD BDMA2_Channel6_IRQHandler ; BDMA2 Channel 6 global Interrupt
+ DCD BDMA2_Channel7_IRQHandler ; BDMA2 Channel 7 global Interrupt
+ DCD COMP_IRQHandler ; COMP global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD UART9_IRQHandler ; UART9 global interrupt
+ DCD USART10_IRQHandler ; USART10 global interrupt
+ DCD LPUART1_IRQHandler ; LPUART1 interrupt
+ DCD 0 ; Reserved
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC_IRQHandler
+ DCD 0 ; Reserved
+ DCD DTS_IRQHandler ; DTS
+ DCD 0 ; Reserved
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+ DCD OCTOSPI2_IRQHandler ; OCTOSPI2
+ DCD OTFDEC1_IRQHandler ; OTFDEC1
+ DCD OTFDEC2_IRQHandler ; OTFDEC2
+ DCD GFXMMU_IRQHandler ; GFXMMU
+ DCD BDMA1_IRQHandler ; BDMA1
+
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_PVM_IRQHandler [WEAK]
+ EXPORT RTC_TAMP_STAMP_CSS_LSE_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream0_IRQHandler [WEAK]
+ EXPORT DMA1_Stream1_IRQHandler [WEAK]
+ EXPORT DMA1_Stream2_IRQHandler [WEAK]
+ EXPORT DMA1_Stream3_IRQHandler [WEAK]
+ EXPORT DMA1_Stream4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream5_IRQHandler [WEAK]
+ EXPORT DMA1_Stream6_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT1_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT1_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT DFSDM2_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
+ EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT SDMMC1_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Stream0_IRQHandler [WEAK]
+ EXPORT DMA2_Stream1_IRQHandler [WEAK]
+ EXPORT DMA2_Stream2_IRQHandler [WEAK]
+ EXPORT DMA2_Stream3_IRQHandler [WEAK]
+ EXPORT DMA2_Stream4_IRQHandler [WEAK]
+ EXPORT FDCAN_CAL_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT4_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT5_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT6_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT7_IRQHandler [WEAK]
+ EXPORT DMA2_Stream5_IRQHandler [WEAK]
+ EXPORT DMA2_Stream6_IRQHandler [WEAK]
+ EXPORT DMA2_Stream7_IRQHandler [WEAK]
+ EXPORT USART6_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_HS_IRQHandler [WEAK]
+ EXPORT DCMI_PSSI_IRQHandler [WEAK]
+ EXPORT CRYP_IRQHandler [WEAK]
+ EXPORT HASH_RNG_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT UART7_IRQHandler [WEAK]
+ EXPORT UART8_IRQHandler [WEAK]
+ EXPORT SPI4_IRQHandler [WEAK]
+ EXPORT SPI5_IRQHandler [WEAK]
+ EXPORT SPI6_IRQHandler [WEAK]
+ EXPORT SAI1_IRQHandler [WEAK]
+ EXPORT LTDC_IRQHandler [WEAK]
+ EXPORT LTDC_ER_IRQHandler [WEAK]
+ EXPORT DMA2D_IRQHandler [WEAK]
+ EXPORT SAI2_IRQHandler [WEAK]
+ EXPORT OCTOSPI1_IRQHandler [WEAK]
+ EXPORT LPTIM1_IRQHandler [WEAK]
+ EXPORT CEC_IRQHandler [WEAK]
+ EXPORT I2C4_EV_IRQHandler [WEAK]
+ EXPORT I2C4_ER_IRQHandler [WEAK]
+ EXPORT SPDIF_RX_IRQHandler [WEAK]
+ EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
+ EXPORT SWPMI1_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT MDIOS_WKUP_IRQHandler [WEAK]
+ EXPORT MDIOS_IRQHandler [WEAK]
+ EXPORT JPEG_IRQHandler [WEAK]
+ EXPORT MDMA_IRQHandler [WEAK]
+ EXPORT SDMMC2_IRQHandler [WEAK]
+ EXPORT HSEM1_IRQHandler [WEAK]
+ EXPORT DAC2_IRQHandler [WEAK]
+ EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel0_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel1_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel2_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel3_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel4_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel5_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel6_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel7_IRQHandler [WEAK]
+ EXPORT COMP_IRQHandler [WEAK]
+ EXPORT LPTIM2_IRQHandler [WEAK]
+ EXPORT LPTIM3_IRQHandler [WEAK]
+ EXPORT UART9_IRQHandler [WEAK]
+ EXPORT USART10_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT CRS_IRQHandler [WEAK]
+ EXPORT ECC_IRQHandler [WEAK]
+ EXPORT DTS_IRQHandler [WEAK]
+ EXPORT WAKEUP_PIN_IRQHandler [WEAK]
+ EXPORT OCTOSPI2_IRQHandler [WEAK]
+ EXPORT OTFDEC1_IRQHandler [WEAK]
+ EXPORT OTFDEC2_IRQHandler [WEAK]
+ EXPORT GFXMMU_IRQHandler [WEAK]
+ EXPORT BDMA1_IRQHandler [WEAK]
+
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler
+DMA1_Stream2_IRQHandler
+DMA1_Stream3_IRQHandler
+DMA1_Stream4_IRQHandler
+DMA1_Stream5_IRQHandler
+DMA1_Stream6_IRQHandler
+ADC_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+FDCAN2_IT1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+DFSDM2_IRQHandler
+TIM8_BRK_TIM12_IRQHandler
+TIM8_UP_TIM13_IRQHandler
+TIM8_TRG_COM_TIM14_IRQHandler
+TIM8_CC_IRQHandler
+DMA1_Stream7_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Stream0_IRQHandler
+DMA2_Stream1_IRQHandler
+DMA2_Stream2_IRQHandler
+DMA2_Stream3_IRQHandler
+DMA2_Stream4_IRQHandler
+FDCAN_CAL_IRQHandler
+DFSDM1_FLT4_IRQHandler
+DFSDM1_FLT5_IRQHandler
+DFSDM1_FLT6_IRQHandler
+DFSDM1_FLT7_IRQHandler
+DMA2_Stream5_IRQHandler
+DMA2_Stream6_IRQHandler
+DMA2_Stream7_IRQHandler
+USART6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+OTG_HS_EP1_OUT_IRQHandler
+OTG_HS_EP1_IN_IRQHandler
+OTG_HS_WKUP_IRQHandler
+OTG_HS_IRQHandler
+DCMI_PSSI_IRQHandler
+CRYP_IRQHandler
+HASH_RNG_IRQHandler
+FPU_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+SAI1_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+DMA2D_IRQHandler
+SAI2_IRQHandler
+OCTOSPI1_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+DMAMUX1_OVR_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+DFSDM1_FLT3_IRQHandler
+SWPMI1_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+MDIOS_WKUP_IRQHandler
+MDIOS_IRQHandler
+JPEG_IRQHandler
+MDMA_IRQHandler
+SDMMC2_IRQHandler
+HSEM1_IRQHandler
+DAC2_IRQHandler
+DMAMUX2_OVR_IRQHandler
+BDMA2_Channel0_IRQHandler
+BDMA2_Channel1_IRQHandler
+BDMA2_Channel2_IRQHandler
+BDMA2_Channel3_IRQHandler
+BDMA2_Channel4_IRQHandler
+BDMA2_Channel5_IRQHandler
+BDMA2_Channel6_IRQHandler
+BDMA2_Channel7_IRQHandler
+COMP_IRQHandler
+LPTIM2_IRQHandler
+LPTIM3_IRQHandler
+UART9_IRQHandler
+USART10_IRQHandler
+LPUART1_IRQHandler
+CRS_IRQHandler
+ECC_IRQHandler
+DTS_IRQHandler
+WAKEUP_PIN_IRQHandler
+OCTOSPI2_IRQHandler
+OTFDEC1_IRQHandler
+OTFDEC2_IRQHandler
+GFXMMU_IRQHandler
+BDMA1_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h7b3xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h7b3xx.s new file mode 100644 index 0000000..d34c730 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h7b3xx.s @@ -0,0 +1,608 @@ +;********************************************************************************
+;* File Name : startup_stm32h7b3xx.s
+;* @author MCD Application Team
+;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog interrupt
+ DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection
+ DCD RTC_TAMP_STAMP_CSS_LSE_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD DFSDM2_IRQHandler ; DFSDM2 Interrupt
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD DFSDM1_FLT4_IRQHandler ; DFSDM Filter4 Interrupt
+ DCD DFSDM1_FLT5_IRQHandler ; DFSDM Filter5 Interrupt
+ DCD DFSDM1_FLT6_IRQHandler ; DFSDM Filter6 Interrupt
+ DCD DFSDM1_FLT7_IRQHandler ; DFSDM Filter7 Interrupt
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_PSSI_IRQHandler ; DCMI,PSSI
+ DCD CRYP_IRQHandler ; CRYP crypto
+ DCD HASH_RNG_IRQHandler ; Hash and Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD OCTOSPI1_IRQHandler ; OCTOSPI1
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD 0 ; Reserved
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD JPEG_IRQHandler ; JPEG global Interrupt
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD 0 ; Reserved
+ DCD DAC2_IRQHandler ; DAC2 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA2_Channel0_IRQHandler ; BDMA2 Channel 0 global Interrupt
+ DCD BDMA2_Channel1_IRQHandler ; BDMA2 Channel 1 global Interrupt
+ DCD BDMA2_Channel2_IRQHandler ; BDMA2 Channel 2 global Interrupt
+ DCD BDMA2_Channel3_IRQHandler ; BDMA2 Channel 3 global Interrupt
+ DCD BDMA2_Channel4_IRQHandler ; BDMA2 Channel 4 global Interrupt
+ DCD BDMA2_Channel5_IRQHandler ; BDMA2 Channel 5 global Interrupt
+ DCD BDMA2_Channel6_IRQHandler ; BDMA2 Channel 6 global Interrupt
+ DCD BDMA2_Channel7_IRQHandler ; BDMA2 Channel 7 global Interrupt
+ DCD COMP_IRQHandler ; COMP global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD UART9_IRQHandler ; UART9 global interrupt
+ DCD USART10_IRQHandler ; USART10 global interrupt
+ DCD LPUART1_IRQHandler ; LPUART1 interrupt
+ DCD 0 ; Reserved
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC_IRQHandler
+ DCD 0 ; Reserved
+ DCD DTS_IRQHandler ; DTS
+ DCD 0 ; Reserved
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+ DCD OCTOSPI2_IRQHandler ; OCTOSPI2
+ DCD OTFDEC1_IRQHandler ; OTFDEC1
+ DCD OTFDEC2_IRQHandler ; OTFDEC2
+ DCD GFXMMU_IRQHandler ; GFXMMU
+ DCD BDMA1_IRQHandler ; BDMA1
+
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_PVM_IRQHandler [WEAK]
+ EXPORT RTC_TAMP_STAMP_CSS_LSE_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream0_IRQHandler [WEAK]
+ EXPORT DMA1_Stream1_IRQHandler [WEAK]
+ EXPORT DMA1_Stream2_IRQHandler [WEAK]
+ EXPORT DMA1_Stream3_IRQHandler [WEAK]
+ EXPORT DMA1_Stream4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream5_IRQHandler [WEAK]
+ EXPORT DMA1_Stream6_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT1_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT1_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT DFSDM2_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
+ EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT SDMMC1_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Stream0_IRQHandler [WEAK]
+ EXPORT DMA2_Stream1_IRQHandler [WEAK]
+ EXPORT DMA2_Stream2_IRQHandler [WEAK]
+ EXPORT DMA2_Stream3_IRQHandler [WEAK]
+ EXPORT DMA2_Stream4_IRQHandler [WEAK]
+ EXPORT FDCAN_CAL_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT4_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT5_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT6_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT7_IRQHandler [WEAK]
+ EXPORT DMA2_Stream5_IRQHandler [WEAK]
+ EXPORT DMA2_Stream6_IRQHandler [WEAK]
+ EXPORT DMA2_Stream7_IRQHandler [WEAK]
+ EXPORT USART6_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_HS_IRQHandler [WEAK]
+ EXPORT DCMI_PSSI_IRQHandler [WEAK]
+ EXPORT CRYP_IRQHandler [WEAK]
+ EXPORT HASH_RNG_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT UART7_IRQHandler [WEAK]
+ EXPORT UART8_IRQHandler [WEAK]
+ EXPORT SPI4_IRQHandler [WEAK]
+ EXPORT SPI5_IRQHandler [WEAK]
+ EXPORT SPI6_IRQHandler [WEAK]
+ EXPORT SAI1_IRQHandler [WEAK]
+ EXPORT LTDC_IRQHandler [WEAK]
+ EXPORT LTDC_ER_IRQHandler [WEAK]
+ EXPORT DMA2D_IRQHandler [WEAK]
+ EXPORT SAI2_IRQHandler [WEAK]
+ EXPORT OCTOSPI1_IRQHandler [WEAK]
+ EXPORT LPTIM1_IRQHandler [WEAK]
+ EXPORT CEC_IRQHandler [WEAK]
+ EXPORT I2C4_EV_IRQHandler [WEAK]
+ EXPORT I2C4_ER_IRQHandler [WEAK]
+ EXPORT SPDIF_RX_IRQHandler [WEAK]
+ EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
+ EXPORT SWPMI1_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT MDIOS_WKUP_IRQHandler [WEAK]
+ EXPORT MDIOS_IRQHandler [WEAK]
+ EXPORT JPEG_IRQHandler [WEAK]
+ EXPORT MDMA_IRQHandler [WEAK]
+ EXPORT SDMMC2_IRQHandler [WEAK]
+ EXPORT HSEM1_IRQHandler [WEAK]
+ EXPORT DAC2_IRQHandler [WEAK]
+ EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel0_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel1_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel2_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel3_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel4_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel5_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel6_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel7_IRQHandler [WEAK]
+ EXPORT COMP_IRQHandler [WEAK]
+ EXPORT LPTIM2_IRQHandler [WEAK]
+ EXPORT LPTIM3_IRQHandler [WEAK]
+ EXPORT UART9_IRQHandler [WEAK]
+ EXPORT USART10_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT CRS_IRQHandler [WEAK]
+ EXPORT ECC_IRQHandler [WEAK]
+ EXPORT DTS_IRQHandler [WEAK]
+ EXPORT WAKEUP_PIN_IRQHandler [WEAK]
+ EXPORT OCTOSPI2_IRQHandler [WEAK]
+ EXPORT OTFDEC1_IRQHandler [WEAK]
+ EXPORT OTFDEC2_IRQHandler [WEAK]
+ EXPORT GFXMMU_IRQHandler [WEAK]
+ EXPORT BDMA1_IRQHandler [WEAK]
+
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler
+DMA1_Stream2_IRQHandler
+DMA1_Stream3_IRQHandler
+DMA1_Stream4_IRQHandler
+DMA1_Stream5_IRQHandler
+DMA1_Stream6_IRQHandler
+ADC_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+FDCAN2_IT1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+DFSDM2_IRQHandler
+TIM8_BRK_TIM12_IRQHandler
+TIM8_UP_TIM13_IRQHandler
+TIM8_TRG_COM_TIM14_IRQHandler
+TIM8_CC_IRQHandler
+DMA1_Stream7_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Stream0_IRQHandler
+DMA2_Stream1_IRQHandler
+DMA2_Stream2_IRQHandler
+DMA2_Stream3_IRQHandler
+DMA2_Stream4_IRQHandler
+FDCAN_CAL_IRQHandler
+DFSDM1_FLT4_IRQHandler
+DFSDM1_FLT5_IRQHandler
+DFSDM1_FLT6_IRQHandler
+DFSDM1_FLT7_IRQHandler
+DMA2_Stream5_IRQHandler
+DMA2_Stream6_IRQHandler
+DMA2_Stream7_IRQHandler
+USART6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+OTG_HS_EP1_OUT_IRQHandler
+OTG_HS_EP1_IN_IRQHandler
+OTG_HS_WKUP_IRQHandler
+OTG_HS_IRQHandler
+DCMI_PSSI_IRQHandler
+CRYP_IRQHandler
+HASH_RNG_IRQHandler
+FPU_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+SAI1_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+DMA2D_IRQHandler
+SAI2_IRQHandler
+OCTOSPI1_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+DMAMUX1_OVR_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+DFSDM1_FLT3_IRQHandler
+SWPMI1_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+MDIOS_WKUP_IRQHandler
+MDIOS_IRQHandler
+JPEG_IRQHandler
+MDMA_IRQHandler
+SDMMC2_IRQHandler
+HSEM1_IRQHandler
+DAC2_IRQHandler
+DMAMUX2_OVR_IRQHandler
+BDMA2_Channel0_IRQHandler
+BDMA2_Channel1_IRQHandler
+BDMA2_Channel2_IRQHandler
+BDMA2_Channel3_IRQHandler
+BDMA2_Channel4_IRQHandler
+BDMA2_Channel5_IRQHandler
+BDMA2_Channel6_IRQHandler
+BDMA2_Channel7_IRQHandler
+COMP_IRQHandler
+LPTIM2_IRQHandler
+LPTIM3_IRQHandler
+UART9_IRQHandler
+USART10_IRQHandler
+LPUART1_IRQHandler
+CRS_IRQHandler
+ECC_IRQHandler
+DTS_IRQHandler
+WAKEUP_PIN_IRQHandler
+OCTOSPI2_IRQHandler
+OTFDEC1_IRQHandler
+OTFDEC2_IRQHandler
+GFXMMU_IRQHandler
+BDMA1_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h7b3xxq.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h7b3xxq.s new file mode 100644 index 0000000..a9b13d4 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h7b3xxq.s @@ -0,0 +1,608 @@ +;********************************************************************************
+;* File Name : startup_stm32h7b3xxq.s
+;* @author MCD Application Team
+;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog interrupt
+ DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection
+ DCD RTC_TAMP_STAMP_CSS_LSE_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD DFSDM2_IRQHandler ; DFSDM2 Interrupt
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD DFSDM1_FLT4_IRQHandler ; DFSDM Filter4 Interrupt
+ DCD DFSDM1_FLT5_IRQHandler ; DFSDM Filter5 Interrupt
+ DCD DFSDM1_FLT6_IRQHandler ; DFSDM Filter6 Interrupt
+ DCD DFSDM1_FLT7_IRQHandler ; DFSDM Filter7 Interrupt
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_PSSI_IRQHandler ; DCMI,PSSI
+ DCD CRYP_IRQHandler ; CRYP crypto
+ DCD HASH_RNG_IRQHandler ; Hash and Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD OCTOSPI1_IRQHandler ; OCTOSPI1
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD 0 ; Reserved
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD JPEG_IRQHandler ; JPEG global Interrupt
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD 0 ; Reserved
+ DCD DAC2_IRQHandler ; DAC2 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA2_Channel0_IRQHandler ; BDMA2 Channel 0 global Interrupt
+ DCD BDMA2_Channel1_IRQHandler ; BDMA2 Channel 1 global Interrupt
+ DCD BDMA2_Channel2_IRQHandler ; BDMA2 Channel 2 global Interrupt
+ DCD BDMA2_Channel3_IRQHandler ; BDMA2 Channel 3 global Interrupt
+ DCD BDMA2_Channel4_IRQHandler ; BDMA2 Channel 4 global Interrupt
+ DCD BDMA2_Channel5_IRQHandler ; BDMA2 Channel 5 global Interrupt
+ DCD BDMA2_Channel6_IRQHandler ; BDMA2 Channel 6 global Interrupt
+ DCD BDMA2_Channel7_IRQHandler ; BDMA2 Channel 7 global Interrupt
+ DCD COMP_IRQHandler ; COMP global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD UART9_IRQHandler ; UART9 global interrupt
+ DCD USART10_IRQHandler ; USART10 global interrupt
+ DCD LPUART1_IRQHandler ; LPUART1 interrupt
+ DCD 0 ; Reserved
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC_IRQHandler
+ DCD 0 ; Reserved
+ DCD DTS_IRQHandler ; DTS
+ DCD 0 ; Reserved
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+ DCD OCTOSPI2_IRQHandler ; OCTOSPI2
+ DCD OTFDEC1_IRQHandler ; OTFDEC1
+ DCD OTFDEC2_IRQHandler ; OTFDEC2
+ DCD GFXMMU_IRQHandler ; GFXMMU
+ DCD BDMA1_IRQHandler ; BDMA1
+
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_PVM_IRQHandler [WEAK]
+ EXPORT RTC_TAMP_STAMP_CSS_LSE_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream0_IRQHandler [WEAK]
+ EXPORT DMA1_Stream1_IRQHandler [WEAK]
+ EXPORT DMA1_Stream2_IRQHandler [WEAK]
+ EXPORT DMA1_Stream3_IRQHandler [WEAK]
+ EXPORT DMA1_Stream4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream5_IRQHandler [WEAK]
+ EXPORT DMA1_Stream6_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT1_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT1_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT DFSDM2_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
+ EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT SDMMC1_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Stream0_IRQHandler [WEAK]
+ EXPORT DMA2_Stream1_IRQHandler [WEAK]
+ EXPORT DMA2_Stream2_IRQHandler [WEAK]
+ EXPORT DMA2_Stream3_IRQHandler [WEAK]
+ EXPORT DMA2_Stream4_IRQHandler [WEAK]
+ EXPORT FDCAN_CAL_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT4_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT5_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT6_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT7_IRQHandler [WEAK]
+ EXPORT DMA2_Stream5_IRQHandler [WEAK]
+ EXPORT DMA2_Stream6_IRQHandler [WEAK]
+ EXPORT DMA2_Stream7_IRQHandler [WEAK]
+ EXPORT USART6_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_HS_IRQHandler [WEAK]
+ EXPORT DCMI_PSSI_IRQHandler [WEAK]
+ EXPORT CRYP_IRQHandler [WEAK]
+ EXPORT HASH_RNG_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT UART7_IRQHandler [WEAK]
+ EXPORT UART8_IRQHandler [WEAK]
+ EXPORT SPI4_IRQHandler [WEAK]
+ EXPORT SPI5_IRQHandler [WEAK]
+ EXPORT SPI6_IRQHandler [WEAK]
+ EXPORT SAI1_IRQHandler [WEAK]
+ EXPORT LTDC_IRQHandler [WEAK]
+ EXPORT LTDC_ER_IRQHandler [WEAK]
+ EXPORT DMA2D_IRQHandler [WEAK]
+ EXPORT SAI2_IRQHandler [WEAK]
+ EXPORT OCTOSPI1_IRQHandler [WEAK]
+ EXPORT LPTIM1_IRQHandler [WEAK]
+ EXPORT CEC_IRQHandler [WEAK]
+ EXPORT I2C4_EV_IRQHandler [WEAK]
+ EXPORT I2C4_ER_IRQHandler [WEAK]
+ EXPORT SPDIF_RX_IRQHandler [WEAK]
+ EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
+ EXPORT SWPMI1_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT MDIOS_WKUP_IRQHandler [WEAK]
+ EXPORT MDIOS_IRQHandler [WEAK]
+ EXPORT JPEG_IRQHandler [WEAK]
+ EXPORT MDMA_IRQHandler [WEAK]
+ EXPORT SDMMC2_IRQHandler [WEAK]
+ EXPORT HSEM1_IRQHandler [WEAK]
+ EXPORT DAC2_IRQHandler [WEAK]
+ EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel0_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel1_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel2_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel3_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel4_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel5_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel6_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel7_IRQHandler [WEAK]
+ EXPORT COMP_IRQHandler [WEAK]
+ EXPORT LPTIM2_IRQHandler [WEAK]
+ EXPORT LPTIM3_IRQHandler [WEAK]
+ EXPORT UART9_IRQHandler [WEAK]
+ EXPORT USART10_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT CRS_IRQHandler [WEAK]
+ EXPORT ECC_IRQHandler [WEAK]
+ EXPORT DTS_IRQHandler [WEAK]
+ EXPORT WAKEUP_PIN_IRQHandler [WEAK]
+ EXPORT OCTOSPI2_IRQHandler [WEAK]
+ EXPORT OTFDEC1_IRQHandler [WEAK]
+ EXPORT OTFDEC2_IRQHandler [WEAK]
+ EXPORT GFXMMU_IRQHandler [WEAK]
+ EXPORT BDMA1_IRQHandler [WEAK]
+
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler
+DMA1_Stream2_IRQHandler
+DMA1_Stream3_IRQHandler
+DMA1_Stream4_IRQHandler
+DMA1_Stream5_IRQHandler
+DMA1_Stream6_IRQHandler
+ADC_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+FDCAN2_IT1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+DFSDM2_IRQHandler
+TIM8_BRK_TIM12_IRQHandler
+TIM8_UP_TIM13_IRQHandler
+TIM8_TRG_COM_TIM14_IRQHandler
+TIM8_CC_IRQHandler
+DMA1_Stream7_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Stream0_IRQHandler
+DMA2_Stream1_IRQHandler
+DMA2_Stream2_IRQHandler
+DMA2_Stream3_IRQHandler
+DMA2_Stream4_IRQHandler
+FDCAN_CAL_IRQHandler
+DFSDM1_FLT4_IRQHandler
+DFSDM1_FLT5_IRQHandler
+DFSDM1_FLT6_IRQHandler
+DFSDM1_FLT7_IRQHandler
+DMA2_Stream5_IRQHandler
+DMA2_Stream6_IRQHandler
+DMA2_Stream7_IRQHandler
+USART6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+OTG_HS_EP1_OUT_IRQHandler
+OTG_HS_EP1_IN_IRQHandler
+OTG_HS_WKUP_IRQHandler
+OTG_HS_IRQHandler
+DCMI_PSSI_IRQHandler
+CRYP_IRQHandler
+HASH_RNG_IRQHandler
+FPU_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+SAI1_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+DMA2D_IRQHandler
+SAI2_IRQHandler
+OCTOSPI1_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+DMAMUX1_OVR_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+DFSDM1_FLT3_IRQHandler
+SWPMI1_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+MDIOS_WKUP_IRQHandler
+MDIOS_IRQHandler
+JPEG_IRQHandler
+MDMA_IRQHandler
+SDMMC2_IRQHandler
+HSEM1_IRQHandler
+DAC2_IRQHandler
+DMAMUX2_OVR_IRQHandler
+BDMA2_Channel0_IRQHandler
+BDMA2_Channel1_IRQHandler
+BDMA2_Channel2_IRQHandler
+BDMA2_Channel3_IRQHandler
+BDMA2_Channel4_IRQHandler
+BDMA2_Channel5_IRQHandler
+BDMA2_Channel6_IRQHandler
+BDMA2_Channel7_IRQHandler
+COMP_IRQHandler
+LPTIM2_IRQHandler
+LPTIM3_IRQHandler
+UART9_IRQHandler
+USART10_IRQHandler
+LPUART1_IRQHandler
+CRS_IRQHandler
+ECC_IRQHandler
+DTS_IRQHandler
+WAKEUP_PIN_IRQHandler
+OCTOSPI2_IRQHandler
+OTFDEC1_IRQHandler
+OTFDEC2_IRQHandler
+GFXMMU_IRQHandler
+BDMA1_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h723xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h723xx.s new file mode 100644 index 0000000..5708560 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h723xx.s @@ -0,0 +1,756 @@ +/**
+ ******************************************************************************
+ * @file startup_stm32h723xx.s
+ * @author MCD Application Team
+ * @brief STM32H723xx Devices vector table for GCC based toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m7
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+ /* External Interrupts */
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
+ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_IRQHandler /* EXTI Line0 */
+ .word EXTI1_IRQHandler /* EXTI Line1 */
+ .word EXTI2_IRQHandler /* EXTI Line2 */
+ .word EXTI3_IRQHandler /* EXTI Line3 */
+ .word EXTI4_IRQHandler /* EXTI Line4 */
+ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
+ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
+ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
+ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
+ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
+ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
+ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
+ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
+ .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
+ .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
+ .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
+ .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
+ .word EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
+ .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
+ .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM4_IRQHandler /* TIM4 */
+ .word I2C1_EV_IRQHandler /* I2C1 Event */
+ .word I2C1_ER_IRQHandler /* I2C1 Error */
+ .word I2C2_EV_IRQHandler /* I2C2 Event */
+ .word I2C2_ER_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
+ .word 0 /* Reserved */
+ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
+ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
+ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
+ .word FMC_IRQHandler /* FMC */
+ .word SDMMC1_IRQHandler /* SDMMC1 */
+ .word TIM5_IRQHandler /* TIM5 */
+ .word SPI3_IRQHandler /* SPI3 */
+ .word UART4_IRQHandler /* UART4 */
+ .word UART5_IRQHandler /* UART5 */
+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
+ .word TIM7_IRQHandler /* TIM7 */
+ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
+ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
+ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
+ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
+ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
+ .word ETH_IRQHandler /* Ethernet */
+ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
+ .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
+ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
+ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
+ .word USART6_IRQHandler /* USART6 */
+ .word I2C3_EV_IRQHandler /* I2C3 event */
+ .word I2C3_ER_IRQHandler /* I2C3 error */
+ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
+ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
+ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
+ .word OTG_HS_IRQHandler /* USB OTG HS */
+ .word DCMI_PSSI_IRQHandler /* DCMI, PSSI */
+ .word 0 /* Reserved */
+ .word RNG_IRQHandler /* Rng */
+ .word FPU_IRQHandler /* FPU */
+ .word UART7_IRQHandler /* UART7 */
+ .word UART8_IRQHandler /* UART8 */
+ .word SPI4_IRQHandler /* SPI4 */
+ .word SPI5_IRQHandler /* SPI5 */
+ .word SPI6_IRQHandler /* SPI6 */
+ .word SAI1_IRQHandler /* SAI1 */
+ .word LTDC_IRQHandler /* LTDC */
+ .word LTDC_ER_IRQHandler /* LTDC error */
+ .word DMA2D_IRQHandler /* DMA2D */
+ .word 0 /* Reserved */
+ .word OCTOSPI1_IRQHandler /* OCTOSPI1 */
+ .word LPTIM1_IRQHandler /* LPTIM1 */
+ .word CEC_IRQHandler /* HDMI_CEC */
+ .word I2C4_EV_IRQHandler /* I2C4 Event */
+ .word I2C4_ER_IRQHandler /* I2C4 Error */
+ .word SPDIF_RX_IRQHandler /* SPDIF_RX */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
+ .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
+ .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
+ .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
+ .word 0 /* Reserved */
+ .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
+ .word TIM15_IRQHandler /* TIM15 global Interrupt */
+ .word TIM16_IRQHandler /* TIM16 global Interrupt */
+ .word TIM17_IRQHandler /* TIM17 global Interrupt */
+ .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
+ .word MDIOS_IRQHandler /* MDIOS global Interrupt */
+ .word 0 /* Reserved */
+ .word MDMA_IRQHandler /* MDMA global Interrupt */
+ .word 0 /* Reserved */
+ .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
+ .word HSEM1_IRQHandler /* HSEM1 global Interrupt */
+ .word 0 /* Reserved */
+ .word ADC3_IRQHandler /* ADC3 global Interrupt */
+ .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
+ .word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
+ .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
+ .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
+ .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
+ .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
+ .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
+ .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
+ .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
+ .word COMP1_IRQHandler /* COMP1 global Interrupt */
+ .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
+ .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
+ .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
+ .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
+ .word LPUART1_IRQHandler /* LP UART1 interrupt */
+ .word 0 /* Reserved */
+ .word CRS_IRQHandler /* Clock Recovery Global Interrupt */
+ .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
+ .word SAI4_IRQHandler /* SAI4 global interrupt */
+ .word DTS_IRQHandler /* Digital Temperature Sensor interrupt */
+ .word 0 /* Reserved */
+ .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
+ .word OCTOSPI2_IRQHandler /* OCTOSPI2 Interrupt */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word FMAC_IRQHandler /* FMAC Interrupt */
+ .word CORDIC_IRQHandler /* CORDIC Interrupt */
+ .word UART9_IRQHandler /* UART9 Interrupt */
+ .word USART10_IRQHandler /* UART10 Interrupt */
+ .word I2C5_EV_IRQHandler /* I2C5 Event Interrupt */
+ .word I2C5_ER_IRQHandler /* I2C5 Error Interrupt */
+ .word FDCAN3_IT0_IRQHandler /* FDCAN3 interrupt line 0 */
+ .word FDCAN3_IT1_IRQHandler /* FDCAN3 interrupt line 1 */
+ .word TIM23_IRQHandler /* TIM23 global interrupt */
+ .word TIM24_IRQHandler /* TIM24 global interrupt */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_AVD_IRQHandler
+ .thumb_set PVD_AVD_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream0_IRQHandler
+ .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream1_IRQHandler
+ .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream2_IRQHandler
+ .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream3_IRQHandler
+ .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream4_IRQHandler
+ .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream5_IRQHandler
+ .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream6_IRQHandler
+ .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT0_IRQHandler
+ .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT0_IRQHandler
+ .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT1_IRQHandler
+ .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT1_IRQHandler
+ .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_TIM12_IRQHandler
+ .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_TIM13_IRQHandler
+ .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_TIM14_IRQHandler
+ .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream7_IRQHandler
+ .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+ .weak FMC_IRQHandler
+ .thumb_set FMC_IRQHandler,Default_Handler
+
+ .weak SDMMC1_IRQHandler
+ .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream0_IRQHandler
+ .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream1_IRQHandler
+ .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream2_IRQHandler
+ .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream3_IRQHandler
+ .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream4_IRQHandler
+ .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+ .weak ETH_IRQHandler
+ .thumb_set ETH_IRQHandler,Default_Handler
+
+ .weak ETH_WKUP_IRQHandler
+ .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+ .weak FDCAN_CAL_IRQHandler
+ .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream5_IRQHandler
+ .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream6_IRQHandler
+ .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream7_IRQHandler
+ .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+ .weak USART6_IRQHandler
+ .thumb_set USART6_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_OUT_IRQHandler
+ .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_IN_IRQHandler
+ .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_HS_WKUP_IRQHandler
+ .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_HS_IRQHandler
+ .thumb_set OTG_HS_IRQHandler,Default_Handler
+
+ .weak DCMI_PSSI_IRQHandler
+ .thumb_set DCMI_PSSI_IRQHandler,Default_Handler
+
+ .weak RNG_IRQHandler
+ .thumb_set RNG_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak UART7_IRQHandler
+ .thumb_set UART7_IRQHandler,Default_Handler
+
+ .weak UART8_IRQHandler
+ .thumb_set UART8_IRQHandler,Default_Handler
+
+ .weak SPI4_IRQHandler
+ .thumb_set SPI4_IRQHandler,Default_Handler
+
+ .weak SPI5_IRQHandler
+ .thumb_set SPI5_IRQHandler,Default_Handler
+
+ .weak SPI6_IRQHandler
+ .thumb_set SPI6_IRQHandler,Default_Handler
+
+ .weak SAI1_IRQHandler
+ .thumb_set SAI1_IRQHandler,Default_Handler
+
+ .weak LTDC_IRQHandler
+ .thumb_set LTDC_IRQHandler,Default_Handler
+
+ .weak LTDC_ER_IRQHandler
+ .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+ .weak DMA2D_IRQHandler
+ .thumb_set DMA2D_IRQHandler,Default_Handler
+
+ .weak OCTOSPI1_IRQHandler
+ .thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak I2C4_EV_IRQHandler
+ .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+ .weak I2C4_ER_IRQHandler
+ .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+ .weak SPDIF_RX_IRQHandler
+ .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+ .weak DMAMUX1_OVR_IRQHandler
+ .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT0_IRQHandler
+ .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT1_IRQHandler
+ .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT2_IRQHandler
+ .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT3_IRQHandler
+ .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+ .weak SWPMI1_IRQHandler
+ .thumb_set SWPMI1_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak MDIOS_WKUP_IRQHandler
+ .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
+
+ .weak MDIOS_IRQHandler
+ .thumb_set MDIOS_IRQHandler,Default_Handler
+
+ .weak MDMA_IRQHandler
+ .thumb_set MDMA_IRQHandler,Default_Handler
+
+ .weak SDMMC2_IRQHandler
+ .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+ .weak HSEM1_IRQHandler
+ .thumb_set HSEM1_IRQHandler,Default_Handler
+
+ .weak ADC3_IRQHandler
+ .thumb_set ADC3_IRQHandler,Default_Handler
+
+ .weak DMAMUX2_OVR_IRQHandler
+ .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel0_IRQHandler
+ .thumb_set BDMA_Channel0_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel1_IRQHandler
+ .thumb_set BDMA_Channel1_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel2_IRQHandler
+ .thumb_set BDMA_Channel2_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel3_IRQHandler
+ .thumb_set BDMA_Channel3_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel4_IRQHandler
+ .thumb_set BDMA_Channel4_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel5_IRQHandler
+ .thumb_set BDMA_Channel5_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel6_IRQHandler
+ .thumb_set BDMA_Channel6_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel7_IRQHandler
+ .thumb_set BDMA_Channel7_IRQHandler,Default_Handler
+
+ .weak COMP1_IRQHandler
+ .thumb_set COMP1_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak LPTIM4_IRQHandler
+ .thumb_set LPTIM4_IRQHandler,Default_Handler
+
+ .weak LPTIM5_IRQHandler
+ .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak CRS_IRQHandler
+ .thumb_set CRS_IRQHandler,Default_Handler
+
+ .weak ECC_IRQHandler
+ .thumb_set ECC_IRQHandler,Default_Handler
+
+ .weak SAI4_IRQHandler
+ .thumb_set SAI4_IRQHandler,Default_Handler
+
+ .weak DTS_IRQHandler
+ .thumb_set DTS_IRQHandler,Default_Handler
+
+ .weak WAKEUP_PIN_IRQHandler
+ .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+ .weak OCTOSPI2_IRQHandler
+ .thumb_set OCTOSPI2_IRQHandler,Default_Handler
+
+ .weak FMAC_IRQHandler
+ .thumb_set FMAC_IRQHandler,Default_Handler
+
+ .weak CORDIC_IRQHandler
+ .thumb_set CORDIC_IRQHandler,Default_Handler
+
+ .weak UART9_IRQHandler
+ .thumb_set UART9_IRQHandler,Default_Handler
+
+ .weak USART10_IRQHandler
+ .thumb_set USART10_IRQHandler,Default_Handler
+
+ .weak I2C5_EV_IRQHandler
+ .thumb_set I2C5_EV_IRQHandler,Default_Handler
+
+ .weak I2C5_ER_IRQHandler
+ .thumb_set I2C5_ER_IRQHandler,Default_Handler
+
+ .weak FDCAN3_IT0_IRQHandler
+ .thumb_set FDCAN3_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN3_IT1_IRQHandler
+ .thumb_set FDCAN3_IT1_IRQHandler,Default_Handler
+
+ .weak TIM23_IRQHandler
+ .thumb_set TIM23_IRQHandler,Default_Handler
+
+ .weak TIM24_IRQHandler
+ .thumb_set TIM24_IRQHandler,Default_Handler
+
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h725xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h725xx.s new file mode 100644 index 0000000..9a37409 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h725xx.s @@ -0,0 +1,756 @@ +/**
+ ******************************************************************************
+ * @file startup_stm32h725xx.s
+ * @author MCD Application Team
+ * @brief STM32H725xx Devices vector table for GCC based toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m7
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+ /* External Interrupts */
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
+ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_IRQHandler /* EXTI Line0 */
+ .word EXTI1_IRQHandler /* EXTI Line1 */
+ .word EXTI2_IRQHandler /* EXTI Line2 */
+ .word EXTI3_IRQHandler /* EXTI Line3 */
+ .word EXTI4_IRQHandler /* EXTI Line4 */
+ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
+ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
+ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
+ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
+ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
+ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
+ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
+ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
+ .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
+ .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
+ .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
+ .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
+ .word EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
+ .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
+ .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM4_IRQHandler /* TIM4 */
+ .word I2C1_EV_IRQHandler /* I2C1 Event */
+ .word I2C1_ER_IRQHandler /* I2C1 Error */
+ .word I2C2_EV_IRQHandler /* I2C2 Event */
+ .word I2C2_ER_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
+ .word 0 /* Reserved */
+ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
+ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
+ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
+ .word FMC_IRQHandler /* FMC */
+ .word SDMMC1_IRQHandler /* SDMMC1 */
+ .word TIM5_IRQHandler /* TIM5 */
+ .word SPI3_IRQHandler /* SPI3 */
+ .word UART4_IRQHandler /* UART4 */
+ .word UART5_IRQHandler /* UART5 */
+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
+ .word TIM7_IRQHandler /* TIM7 */
+ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
+ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
+ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
+ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
+ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
+ .word ETH_IRQHandler /* Ethernet */
+ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
+ .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
+ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
+ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
+ .word USART6_IRQHandler /* USART6 */
+ .word I2C3_EV_IRQHandler /* I2C3 event */
+ .word I2C3_ER_IRQHandler /* I2C3 error */
+ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
+ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
+ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
+ .word OTG_HS_IRQHandler /* USB OTG HS */
+ .word DCMI_PSSI_IRQHandler /* DCMI, PSSI */
+ .word 0 /* Reserved */
+ .word RNG_IRQHandler /* Rng */
+ .word FPU_IRQHandler /* FPU */
+ .word UART7_IRQHandler /* UART7 */
+ .word UART8_IRQHandler /* UART8 */
+ .word SPI4_IRQHandler /* SPI4 */
+ .word SPI5_IRQHandler /* SPI5 */
+ .word SPI6_IRQHandler /* SPI6 */
+ .word SAI1_IRQHandler /* SAI1 */
+ .word LTDC_IRQHandler /* LTDC */
+ .word LTDC_ER_IRQHandler /* LTDC error */
+ .word DMA2D_IRQHandler /* DMA2D */
+ .word 0 /* Reserved */
+ .word OCTOSPI1_IRQHandler /* OCTOSPI1 */
+ .word LPTIM1_IRQHandler /* LPTIM1 */
+ .word CEC_IRQHandler /* HDMI_CEC */
+ .word I2C4_EV_IRQHandler /* I2C4 Event */
+ .word I2C4_ER_IRQHandler /* I2C4 Error */
+ .word SPDIF_RX_IRQHandler /* SPDIF_RX */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
+ .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
+ .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
+ .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
+ .word 0 /* Reserved */
+ .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
+ .word TIM15_IRQHandler /* TIM15 global Interrupt */
+ .word TIM16_IRQHandler /* TIM16 global Interrupt */
+ .word TIM17_IRQHandler /* TIM17 global Interrupt */
+ .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
+ .word MDIOS_IRQHandler /* MDIOS global Interrupt */
+ .word 0 /* Reserved */
+ .word MDMA_IRQHandler /* MDMA global Interrupt */
+ .word 0 /* Reserved */
+ .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
+ .word HSEM1_IRQHandler /* HSEM1 global Interrupt */
+ .word 0 /* Reserved */
+ .word ADC3_IRQHandler /* ADC3 global Interrupt */
+ .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
+ .word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
+ .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
+ .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
+ .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
+ .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
+ .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
+ .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
+ .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
+ .word COMP1_IRQHandler /* COMP1 global Interrupt */
+ .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
+ .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
+ .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
+ .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
+ .word LPUART1_IRQHandler /* LP UART1 interrupt */
+ .word 0 /* Reserved */
+ .word CRS_IRQHandler /* Clock Recovery Global Interrupt */
+ .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
+ .word SAI4_IRQHandler /* SAI4 global interrupt */
+ .word DTS_IRQHandler /* Digital Temperature Sensor interrupt */
+ .word 0 /* Reserved */
+ .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
+ .word OCTOSPI2_IRQHandler /* OCTOSPI2 Interrupt */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word FMAC_IRQHandler /* FMAC Interrupt */
+ .word CORDIC_IRQHandler /* CORDIC Interrupt */
+ .word UART9_IRQHandler /* UART9 Interrupt */
+ .word USART10_IRQHandler /* UART10 Interrupt */
+ .word I2C5_EV_IRQHandler /* I2C5 Event Interrupt */
+ .word I2C5_ER_IRQHandler /* I2C5 Error Interrupt */
+ .word FDCAN3_IT0_IRQHandler /* FDCAN3 interrupt line 0 */
+ .word FDCAN3_IT1_IRQHandler /* FDCAN3 interrupt line 1 */
+ .word TIM23_IRQHandler /* TIM23 global interrupt */
+ .word TIM24_IRQHandler /* TIM24 global interrupt */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_AVD_IRQHandler
+ .thumb_set PVD_AVD_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream0_IRQHandler
+ .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream1_IRQHandler
+ .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream2_IRQHandler
+ .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream3_IRQHandler
+ .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream4_IRQHandler
+ .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream5_IRQHandler
+ .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream6_IRQHandler
+ .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT0_IRQHandler
+ .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT0_IRQHandler
+ .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT1_IRQHandler
+ .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT1_IRQHandler
+ .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_TIM12_IRQHandler
+ .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_TIM13_IRQHandler
+ .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_TIM14_IRQHandler
+ .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream7_IRQHandler
+ .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+ .weak FMC_IRQHandler
+ .thumb_set FMC_IRQHandler,Default_Handler
+
+ .weak SDMMC1_IRQHandler
+ .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream0_IRQHandler
+ .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream1_IRQHandler
+ .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream2_IRQHandler
+ .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream3_IRQHandler
+ .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream4_IRQHandler
+ .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+ .weak ETH_IRQHandler
+ .thumb_set ETH_IRQHandler,Default_Handler
+
+ .weak ETH_WKUP_IRQHandler
+ .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+ .weak FDCAN_CAL_IRQHandler
+ .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream5_IRQHandler
+ .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream6_IRQHandler
+ .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream7_IRQHandler
+ .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+ .weak USART6_IRQHandler
+ .thumb_set USART6_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_OUT_IRQHandler
+ .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_IN_IRQHandler
+ .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_HS_WKUP_IRQHandler
+ .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_HS_IRQHandler
+ .thumb_set OTG_HS_IRQHandler,Default_Handler
+
+ .weak DCMI_PSSI_IRQHandler
+ .thumb_set DCMI_PSSI_IRQHandler,Default_Handler
+
+ .weak RNG_IRQHandler
+ .thumb_set RNG_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak UART7_IRQHandler
+ .thumb_set UART7_IRQHandler,Default_Handler
+
+ .weak UART8_IRQHandler
+ .thumb_set UART8_IRQHandler,Default_Handler
+
+ .weak SPI4_IRQHandler
+ .thumb_set SPI4_IRQHandler,Default_Handler
+
+ .weak SPI5_IRQHandler
+ .thumb_set SPI5_IRQHandler,Default_Handler
+
+ .weak SPI6_IRQHandler
+ .thumb_set SPI6_IRQHandler,Default_Handler
+
+ .weak SAI1_IRQHandler
+ .thumb_set SAI1_IRQHandler,Default_Handler
+
+ .weak LTDC_IRQHandler
+ .thumb_set LTDC_IRQHandler,Default_Handler
+
+ .weak LTDC_ER_IRQHandler
+ .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+ .weak DMA2D_IRQHandler
+ .thumb_set DMA2D_IRQHandler,Default_Handler
+
+ .weak OCTOSPI1_IRQHandler
+ .thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak I2C4_EV_IRQHandler
+ .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+ .weak I2C4_ER_IRQHandler
+ .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+ .weak SPDIF_RX_IRQHandler
+ .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+ .weak DMAMUX1_OVR_IRQHandler
+ .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT0_IRQHandler
+ .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT1_IRQHandler
+ .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT2_IRQHandler
+ .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT3_IRQHandler
+ .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+ .weak SWPMI1_IRQHandler
+ .thumb_set SWPMI1_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak MDIOS_WKUP_IRQHandler
+ .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
+
+ .weak MDIOS_IRQHandler
+ .thumb_set MDIOS_IRQHandler,Default_Handler
+
+ .weak MDMA_IRQHandler
+ .thumb_set MDMA_IRQHandler,Default_Handler
+
+ .weak SDMMC2_IRQHandler
+ .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+ .weak HSEM1_IRQHandler
+ .thumb_set HSEM1_IRQHandler,Default_Handler
+
+ .weak ADC3_IRQHandler
+ .thumb_set ADC3_IRQHandler,Default_Handler
+
+ .weak DMAMUX2_OVR_IRQHandler
+ .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel0_IRQHandler
+ .thumb_set BDMA_Channel0_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel1_IRQHandler
+ .thumb_set BDMA_Channel1_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel2_IRQHandler
+ .thumb_set BDMA_Channel2_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel3_IRQHandler
+ .thumb_set BDMA_Channel3_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel4_IRQHandler
+ .thumb_set BDMA_Channel4_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel5_IRQHandler
+ .thumb_set BDMA_Channel5_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel6_IRQHandler
+ .thumb_set BDMA_Channel6_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel7_IRQHandler
+ .thumb_set BDMA_Channel7_IRQHandler,Default_Handler
+
+ .weak COMP1_IRQHandler
+ .thumb_set COMP1_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak LPTIM4_IRQHandler
+ .thumb_set LPTIM4_IRQHandler,Default_Handler
+
+ .weak LPTIM5_IRQHandler
+ .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak CRS_IRQHandler
+ .thumb_set CRS_IRQHandler,Default_Handler
+
+ .weak ECC_IRQHandler
+ .thumb_set ECC_IRQHandler,Default_Handler
+
+ .weak SAI4_IRQHandler
+ .thumb_set SAI4_IRQHandler,Default_Handler
+
+ .weak DTS_IRQHandler
+ .thumb_set DTS_IRQHandler,Default_Handler
+
+ .weak WAKEUP_PIN_IRQHandler
+ .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+ .weak OCTOSPI2_IRQHandler
+ .thumb_set OCTOSPI2_IRQHandler,Default_Handler
+
+ .weak FMAC_IRQHandler
+ .thumb_set FMAC_IRQHandler,Default_Handler
+
+ .weak CORDIC_IRQHandler
+ .thumb_set CORDIC_IRQHandler,Default_Handler
+
+ .weak UART9_IRQHandler
+ .thumb_set UART9_IRQHandler,Default_Handler
+
+ .weak USART10_IRQHandler
+ .thumb_set USART10_IRQHandler,Default_Handler
+
+ .weak I2C5_EV_IRQHandler
+ .thumb_set I2C5_EV_IRQHandler,Default_Handler
+
+ .weak I2C5_ER_IRQHandler
+ .thumb_set I2C5_ER_IRQHandler,Default_Handler
+
+ .weak FDCAN3_IT0_IRQHandler
+ .thumb_set FDCAN3_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN3_IT1_IRQHandler
+ .thumb_set FDCAN3_IT1_IRQHandler,Default_Handler
+
+ .weak TIM23_IRQHandler
+ .thumb_set TIM23_IRQHandler,Default_Handler
+
+ .weak TIM24_IRQHandler
+ .thumb_set TIM24_IRQHandler,Default_Handler
+
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h730xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h730xx.s new file mode 100644 index 0000000..6547ce3 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h730xx.s @@ -0,0 +1,765 @@ +/**
+ ******************************************************************************
+ * @file startup_stm32h730xx.s
+ * @author MCD Application Team
+ * @brief STM32H730xx Devices vector table for GCC based toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m7
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+ /* External Interrupts */
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
+ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_IRQHandler /* EXTI Line0 */
+ .word EXTI1_IRQHandler /* EXTI Line1 */
+ .word EXTI2_IRQHandler /* EXTI Line2 */
+ .word EXTI3_IRQHandler /* EXTI Line3 */
+ .word EXTI4_IRQHandler /* EXTI Line4 */
+ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
+ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
+ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
+ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
+ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
+ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
+ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
+ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
+ .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
+ .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
+ .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
+ .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
+ .word EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
+ .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
+ .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM4_IRQHandler /* TIM4 */
+ .word I2C1_EV_IRQHandler /* I2C1 Event */
+ .word I2C1_ER_IRQHandler /* I2C1 Error */
+ .word I2C2_EV_IRQHandler /* I2C2 Event */
+ .word I2C2_ER_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
+ .word 0 /* Reserved */
+ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
+ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
+ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
+ .word FMC_IRQHandler /* FMC */
+ .word SDMMC1_IRQHandler /* SDMMC1 */
+ .word TIM5_IRQHandler /* TIM5 */
+ .word SPI3_IRQHandler /* SPI3 */
+ .word UART4_IRQHandler /* UART4 */
+ .word UART5_IRQHandler /* UART5 */
+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
+ .word TIM7_IRQHandler /* TIM7 */
+ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
+ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
+ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
+ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
+ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
+ .word ETH_IRQHandler /* Ethernet */
+ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
+ .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
+ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
+ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
+ .word USART6_IRQHandler /* USART6 */
+ .word I2C3_EV_IRQHandler /* I2C3 event */
+ .word I2C3_ER_IRQHandler /* I2C3 error */
+ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
+ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
+ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
+ .word OTG_HS_IRQHandler /* USB OTG HS */
+ .word DCMI_PSSI_IRQHandler /* DCMI, PSSI */
+ .word CRYP_IRQHandler /* CRYP */
+ .word HASH_RNG_IRQHandler /* Hash and Rng */
+ .word FPU_IRQHandler /* FPU */
+ .word UART7_IRQHandler /* UART7 */
+ .word UART8_IRQHandler /* UART8 */
+ .word SPI4_IRQHandler /* SPI4 */
+ .word SPI5_IRQHandler /* SPI5 */
+ .word SPI6_IRQHandler /* SPI6 */
+ .word SAI1_IRQHandler /* SAI1 */
+ .word LTDC_IRQHandler /* LTDC */
+ .word LTDC_ER_IRQHandler /* LTDC error */
+ .word DMA2D_IRQHandler /* DMA2D */
+ .word 0 /* Reserved */
+ .word OCTOSPI1_IRQHandler /* OCTOSPI1 */
+ .word LPTIM1_IRQHandler /* LPTIM1 */
+ .word CEC_IRQHandler /* HDMI_CEC */
+ .word I2C4_EV_IRQHandler /* I2C4 Event */
+ .word I2C4_ER_IRQHandler /* I2C4 Error */
+ .word SPDIF_RX_IRQHandler /* SPDIF_RX */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
+ .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
+ .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
+ .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
+ .word 0 /* Reserved */
+ .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
+ .word TIM15_IRQHandler /* TIM15 global Interrupt */
+ .word TIM16_IRQHandler /* TIM16 global Interrupt */
+ .word TIM17_IRQHandler /* TIM17 global Interrupt */
+ .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
+ .word MDIOS_IRQHandler /* MDIOS global Interrupt */
+ .word 0 /* Reserved */
+ .word MDMA_IRQHandler /* MDMA global Interrupt */
+ .word 0 /* Reserved */
+ .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
+ .word HSEM1_IRQHandler /* HSEM1 global Interrupt */
+ .word 0 /* Reserved */
+ .word ADC3_IRQHandler /* ADC3 global Interrupt */
+ .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
+ .word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
+ .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
+ .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
+ .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
+ .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
+ .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
+ .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
+ .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
+ .word COMP1_IRQHandler /* COMP1 global Interrupt */
+ .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
+ .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
+ .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
+ .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
+ .word LPUART1_IRQHandler /* LP UART1 interrupt */
+ .word 0 /* Reserved */
+ .word CRS_IRQHandler /* Clock Recovery Global Interrupt */
+ .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
+ .word SAI4_IRQHandler /* SAI4 global interrupt */
+ .word DTS_IRQHandler /* Digital Temperature Sensor interrupt */
+ .word 0 /* Reserved */
+ .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
+ .word OCTOSPI2_IRQHandler /* OCTOSPI2 Interrupt */
+ .word OTFDEC1_IRQHandler /* OTFDEC1 Interrupt */
+ .word OTFDEC2_IRQHandler /* OTFDEC2 Interrupt */
+ .word FMAC_IRQHandler /* FMAC Interrupt */
+ .word CORDIC_IRQHandler /* CORDIC Interrupt */
+ .word UART9_IRQHandler /* UART9 Interrupt */
+ .word USART10_IRQHandler /* UART10 Interrupt */
+ .word I2C5_EV_IRQHandler /* I2C5 Event Interrupt */
+ .word I2C5_ER_IRQHandler /* I2C5 Error Interrupt */
+ .word FDCAN3_IT0_IRQHandler /* FDCAN3 interrupt line 0 */
+ .word FDCAN3_IT1_IRQHandler /* FDCAN3 interrupt line 1 */
+ .word TIM23_IRQHandler /* TIM23 global interrupt */
+ .word TIM24_IRQHandler /* TIM24 global interrupt */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_AVD_IRQHandler
+ .thumb_set PVD_AVD_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream0_IRQHandler
+ .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream1_IRQHandler
+ .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream2_IRQHandler
+ .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream3_IRQHandler
+ .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream4_IRQHandler
+ .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream5_IRQHandler
+ .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream6_IRQHandler
+ .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT0_IRQHandler
+ .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT0_IRQHandler
+ .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT1_IRQHandler
+ .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT1_IRQHandler
+ .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_TIM12_IRQHandler
+ .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_TIM13_IRQHandler
+ .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_TIM14_IRQHandler
+ .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream7_IRQHandler
+ .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+ .weak FMC_IRQHandler
+ .thumb_set FMC_IRQHandler,Default_Handler
+
+ .weak SDMMC1_IRQHandler
+ .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream0_IRQHandler
+ .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream1_IRQHandler
+ .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream2_IRQHandler
+ .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream3_IRQHandler
+ .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream4_IRQHandler
+ .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+ .weak ETH_IRQHandler
+ .thumb_set ETH_IRQHandler,Default_Handler
+
+ .weak ETH_WKUP_IRQHandler
+ .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+ .weak FDCAN_CAL_IRQHandler
+ .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream5_IRQHandler
+ .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream6_IRQHandler
+ .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream7_IRQHandler
+ .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+ .weak USART6_IRQHandler
+ .thumb_set USART6_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_OUT_IRQHandler
+ .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_IN_IRQHandler
+ .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_HS_WKUP_IRQHandler
+ .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_HS_IRQHandler
+ .thumb_set OTG_HS_IRQHandler,Default_Handler
+
+ .weak DCMI_PSSI_IRQHandler
+ .thumb_set DCMI_PSSI_IRQHandler,Default_Handler
+
+ .weak CRYP_IRQHandler
+ .thumb_set CRYP_IRQHandler,Default_Handler
+
+ .weak HASH_RNG_IRQHandler
+ .thumb_set HASH_RNG_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak UART7_IRQHandler
+ .thumb_set UART7_IRQHandler,Default_Handler
+
+ .weak UART8_IRQHandler
+ .thumb_set UART8_IRQHandler,Default_Handler
+
+ .weak SPI4_IRQHandler
+ .thumb_set SPI4_IRQHandler,Default_Handler
+
+ .weak SPI5_IRQHandler
+ .thumb_set SPI5_IRQHandler,Default_Handler
+
+ .weak SPI6_IRQHandler
+ .thumb_set SPI6_IRQHandler,Default_Handler
+
+ .weak SAI1_IRQHandler
+ .thumb_set SAI1_IRQHandler,Default_Handler
+
+ .weak LTDC_IRQHandler
+ .thumb_set LTDC_IRQHandler,Default_Handler
+
+ .weak LTDC_ER_IRQHandler
+ .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+ .weak DMA2D_IRQHandler
+ .thumb_set DMA2D_IRQHandler,Default_Handler
+
+ .weak OCTOSPI1_IRQHandler
+ .thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak I2C4_EV_IRQHandler
+ .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+ .weak I2C4_ER_IRQHandler
+ .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+ .weak SPDIF_RX_IRQHandler
+ .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+ .weak DMAMUX1_OVR_IRQHandler
+ .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT0_IRQHandler
+ .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT1_IRQHandler
+ .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT2_IRQHandler
+ .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT3_IRQHandler
+ .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+ .weak SWPMI1_IRQHandler
+ .thumb_set SWPMI1_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak MDIOS_WKUP_IRQHandler
+ .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
+
+ .weak MDIOS_IRQHandler
+ .thumb_set MDIOS_IRQHandler,Default_Handler
+
+ .weak MDMA_IRQHandler
+ .thumb_set MDMA_IRQHandler,Default_Handler
+
+ .weak SDMMC2_IRQHandler
+ .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+ .weak HSEM1_IRQHandler
+ .thumb_set HSEM1_IRQHandler,Default_Handler
+
+ .weak ADC3_IRQHandler
+ .thumb_set ADC3_IRQHandler,Default_Handler
+
+ .weak DMAMUX2_OVR_IRQHandler
+ .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel0_IRQHandler
+ .thumb_set BDMA_Channel0_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel1_IRQHandler
+ .thumb_set BDMA_Channel1_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel2_IRQHandler
+ .thumb_set BDMA_Channel2_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel3_IRQHandler
+ .thumb_set BDMA_Channel3_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel4_IRQHandler
+ .thumb_set BDMA_Channel4_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel5_IRQHandler
+ .thumb_set BDMA_Channel5_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel6_IRQHandler
+ .thumb_set BDMA_Channel6_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel7_IRQHandler
+ .thumb_set BDMA_Channel7_IRQHandler,Default_Handler
+
+ .weak COMP1_IRQHandler
+ .thumb_set COMP1_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak LPTIM4_IRQHandler
+ .thumb_set LPTIM4_IRQHandler,Default_Handler
+
+ .weak LPTIM5_IRQHandler
+ .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak CRS_IRQHandler
+ .thumb_set CRS_IRQHandler,Default_Handler
+
+ .weak ECC_IRQHandler
+ .thumb_set ECC_IRQHandler,Default_Handler
+
+ .weak SAI4_IRQHandler
+ .thumb_set SAI4_IRQHandler,Default_Handler
+
+ .weak DTS_IRQHandler
+ .thumb_set DTS_IRQHandler,Default_Handler
+
+ .weak WAKEUP_PIN_IRQHandler
+ .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+ .weak OCTOSPI2_IRQHandler
+ .thumb_set OCTOSPI2_IRQHandler,Default_Handler
+
+ .weak OTFDEC1_IRQHandler
+ .thumb_set OTFDEC1_IRQHandler,Default_Handler
+
+ .weak OTFDEC2_IRQHandler
+ .thumb_set OTFDEC2_IRQHandler,Default_Handler
+
+ .weak FMAC_IRQHandler
+ .thumb_set FMAC_IRQHandler,Default_Handler
+
+ .weak CORDIC_IRQHandler
+ .thumb_set CORDIC_IRQHandler,Default_Handler
+
+ .weak UART9_IRQHandler
+ .thumb_set UART9_IRQHandler,Default_Handler
+
+ .weak USART10_IRQHandler
+ .thumb_set USART10_IRQHandler,Default_Handler
+
+ .weak I2C5_EV_IRQHandler
+ .thumb_set I2C5_EV_IRQHandler,Default_Handler
+
+ .weak I2C5_ER_IRQHandler
+ .thumb_set I2C5_ER_IRQHandler,Default_Handler
+
+ .weak FDCAN3_IT0_IRQHandler
+ .thumb_set FDCAN3_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN3_IT1_IRQHandler
+ .thumb_set FDCAN3_IT1_IRQHandler,Default_Handler
+
+ .weak TIM23_IRQHandler
+ .thumb_set TIM23_IRQHandler,Default_Handler
+
+ .weak TIM24_IRQHandler
+ .thumb_set TIM24_IRQHandler,Default_Handler
+
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h730xxq.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h730xxq.s new file mode 100644 index 0000000..693a7b3 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h730xxq.s @@ -0,0 +1,765 @@ +/**
+ ******************************************************************************
+ * @file startup_stm32h730xxq.s
+ * @author MCD Application Team
+ * @brief STM32H730xxQ Devices vector table for GCC based toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m7
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+ /* External Interrupts */
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
+ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_IRQHandler /* EXTI Line0 */
+ .word EXTI1_IRQHandler /* EXTI Line1 */
+ .word EXTI2_IRQHandler /* EXTI Line2 */
+ .word EXTI3_IRQHandler /* EXTI Line3 */
+ .word EXTI4_IRQHandler /* EXTI Line4 */
+ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
+ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
+ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
+ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
+ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
+ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
+ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
+ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
+ .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
+ .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
+ .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
+ .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
+ .word EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
+ .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
+ .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM4_IRQHandler /* TIM4 */
+ .word I2C1_EV_IRQHandler /* I2C1 Event */
+ .word I2C1_ER_IRQHandler /* I2C1 Error */
+ .word I2C2_EV_IRQHandler /* I2C2 Event */
+ .word I2C2_ER_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
+ .word 0 /* Reserved */
+ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
+ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
+ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
+ .word FMC_IRQHandler /* FMC */
+ .word SDMMC1_IRQHandler /* SDMMC1 */
+ .word TIM5_IRQHandler /* TIM5 */
+ .word SPI3_IRQHandler /* SPI3 */
+ .word UART4_IRQHandler /* UART4 */
+ .word UART5_IRQHandler /* UART5 */
+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
+ .word TIM7_IRQHandler /* TIM7 */
+ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
+ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
+ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
+ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
+ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
+ .word ETH_IRQHandler /* Ethernet */
+ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
+ .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
+ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
+ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
+ .word USART6_IRQHandler /* USART6 */
+ .word I2C3_EV_IRQHandler /* I2C3 event */
+ .word I2C3_ER_IRQHandler /* I2C3 error */
+ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
+ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
+ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
+ .word OTG_HS_IRQHandler /* USB OTG HS */
+ .word DCMI_PSSI_IRQHandler /* DCMI, PSSI */
+ .word CRYP_IRQHandler /* CRYP */
+ .word HASH_RNG_IRQHandler /* Hash and Rng */
+ .word FPU_IRQHandler /* FPU */
+ .word UART7_IRQHandler /* UART7 */
+ .word UART8_IRQHandler /* UART8 */
+ .word SPI4_IRQHandler /* SPI4 */
+ .word SPI5_IRQHandler /* SPI5 */
+ .word SPI6_IRQHandler /* SPI6 */
+ .word SAI1_IRQHandler /* SAI1 */
+ .word LTDC_IRQHandler /* LTDC */
+ .word LTDC_ER_IRQHandler /* LTDC error */
+ .word DMA2D_IRQHandler /* DMA2D */
+ .word 0 /* Reserved */
+ .word OCTOSPI1_IRQHandler /* OCTOSPI1 */
+ .word LPTIM1_IRQHandler /* LPTIM1 */
+ .word CEC_IRQHandler /* HDMI_CEC */
+ .word I2C4_EV_IRQHandler /* I2C4 Event */
+ .word I2C4_ER_IRQHandler /* I2C4 Error */
+ .word SPDIF_RX_IRQHandler /* SPDIF_RX */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
+ .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
+ .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
+ .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
+ .word 0 /* Reserved */
+ .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
+ .word TIM15_IRQHandler /* TIM15 global Interrupt */
+ .word TIM16_IRQHandler /* TIM16 global Interrupt */
+ .word TIM17_IRQHandler /* TIM17 global Interrupt */
+ .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
+ .word MDIOS_IRQHandler /* MDIOS global Interrupt */
+ .word 0 /* Reserved */
+ .word MDMA_IRQHandler /* MDMA global Interrupt */
+ .word 0 /* Reserved */
+ .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
+ .word HSEM1_IRQHandler /* HSEM1 global Interrupt */
+ .word 0 /* Reserved */
+ .word ADC3_IRQHandler /* ADC3 global Interrupt */
+ .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
+ .word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
+ .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
+ .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
+ .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
+ .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
+ .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
+ .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
+ .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
+ .word COMP1_IRQHandler /* COMP1 global Interrupt */
+ .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
+ .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
+ .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
+ .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
+ .word LPUART1_IRQHandler /* LP UART1 interrupt */
+ .word 0 /* Reserved */
+ .word CRS_IRQHandler /* Clock Recovery Global Interrupt */
+ .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
+ .word SAI4_IRQHandler /* SAI4 global interrupt */
+ .word DTS_IRQHandler /* Digital Temperature Sensor interrupt */
+ .word 0 /* Reserved */
+ .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
+ .word OCTOSPI2_IRQHandler /* OCTOSPI2 Interrupt */
+ .word OTFDEC1_IRQHandler /* OTFDEC1 Interrupt */
+ .word OTFDEC2_IRQHandler /* OTFDEC2 Interrupt */
+ .word FMAC_IRQHandler /* FMAC Interrupt */
+ .word CORDIC_IRQHandler /* CORDIC Interrupt */
+ .word UART9_IRQHandler /* UART9 Interrupt */
+ .word USART10_IRQHandler /* UART10 Interrupt */
+ .word I2C5_EV_IRQHandler /* I2C5 Event Interrupt */
+ .word I2C5_ER_IRQHandler /* I2C5 Error Interrupt */
+ .word FDCAN3_IT0_IRQHandler /* FDCAN3 interrupt line 0 */
+ .word FDCAN3_IT1_IRQHandler /* FDCAN3 interrupt line 1 */
+ .word TIM23_IRQHandler /* TIM23 global interrupt */
+ .word TIM24_IRQHandler /* TIM24 global interrupt */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_AVD_IRQHandler
+ .thumb_set PVD_AVD_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream0_IRQHandler
+ .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream1_IRQHandler
+ .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream2_IRQHandler
+ .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream3_IRQHandler
+ .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream4_IRQHandler
+ .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream5_IRQHandler
+ .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream6_IRQHandler
+ .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT0_IRQHandler
+ .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT0_IRQHandler
+ .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT1_IRQHandler
+ .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT1_IRQHandler
+ .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_TIM12_IRQHandler
+ .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_TIM13_IRQHandler
+ .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_TIM14_IRQHandler
+ .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream7_IRQHandler
+ .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+ .weak FMC_IRQHandler
+ .thumb_set FMC_IRQHandler,Default_Handler
+
+ .weak SDMMC1_IRQHandler
+ .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream0_IRQHandler
+ .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream1_IRQHandler
+ .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream2_IRQHandler
+ .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream3_IRQHandler
+ .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream4_IRQHandler
+ .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+ .weak ETH_IRQHandler
+ .thumb_set ETH_IRQHandler,Default_Handler
+
+ .weak ETH_WKUP_IRQHandler
+ .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+ .weak FDCAN_CAL_IRQHandler
+ .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream5_IRQHandler
+ .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream6_IRQHandler
+ .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream7_IRQHandler
+ .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+ .weak USART6_IRQHandler
+ .thumb_set USART6_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_OUT_IRQHandler
+ .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_IN_IRQHandler
+ .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_HS_WKUP_IRQHandler
+ .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_HS_IRQHandler
+ .thumb_set OTG_HS_IRQHandler,Default_Handler
+
+ .weak DCMI_PSSI_IRQHandler
+ .thumb_set DCMI_PSSI_IRQHandler,Default_Handler
+
+ .weak CRYP_IRQHandler
+ .thumb_set CRYP_IRQHandler,Default_Handler
+
+ .weak HASH_RNG_IRQHandler
+ .thumb_set HASH_RNG_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak UART7_IRQHandler
+ .thumb_set UART7_IRQHandler,Default_Handler
+
+ .weak UART8_IRQHandler
+ .thumb_set UART8_IRQHandler,Default_Handler
+
+ .weak SPI4_IRQHandler
+ .thumb_set SPI4_IRQHandler,Default_Handler
+
+ .weak SPI5_IRQHandler
+ .thumb_set SPI5_IRQHandler,Default_Handler
+
+ .weak SPI6_IRQHandler
+ .thumb_set SPI6_IRQHandler,Default_Handler
+
+ .weak SAI1_IRQHandler
+ .thumb_set SAI1_IRQHandler,Default_Handler
+
+ .weak LTDC_IRQHandler
+ .thumb_set LTDC_IRQHandler,Default_Handler
+
+ .weak LTDC_ER_IRQHandler
+ .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+ .weak DMA2D_IRQHandler
+ .thumb_set DMA2D_IRQHandler,Default_Handler
+
+ .weak OCTOSPI1_IRQHandler
+ .thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak I2C4_EV_IRQHandler
+ .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+ .weak I2C4_ER_IRQHandler
+ .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+ .weak SPDIF_RX_IRQHandler
+ .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+ .weak DMAMUX1_OVR_IRQHandler
+ .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT0_IRQHandler
+ .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT1_IRQHandler
+ .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT2_IRQHandler
+ .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT3_IRQHandler
+ .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+ .weak SWPMI1_IRQHandler
+ .thumb_set SWPMI1_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak MDIOS_WKUP_IRQHandler
+ .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
+
+ .weak MDIOS_IRQHandler
+ .thumb_set MDIOS_IRQHandler,Default_Handler
+
+ .weak MDMA_IRQHandler
+ .thumb_set MDMA_IRQHandler,Default_Handler
+
+ .weak SDMMC2_IRQHandler
+ .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+ .weak HSEM1_IRQHandler
+ .thumb_set HSEM1_IRQHandler,Default_Handler
+
+ .weak ADC3_IRQHandler
+ .thumb_set ADC3_IRQHandler,Default_Handler
+
+ .weak DMAMUX2_OVR_IRQHandler
+ .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel0_IRQHandler
+ .thumb_set BDMA_Channel0_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel1_IRQHandler
+ .thumb_set BDMA_Channel1_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel2_IRQHandler
+ .thumb_set BDMA_Channel2_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel3_IRQHandler
+ .thumb_set BDMA_Channel3_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel4_IRQHandler
+ .thumb_set BDMA_Channel4_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel5_IRQHandler
+ .thumb_set BDMA_Channel5_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel6_IRQHandler
+ .thumb_set BDMA_Channel6_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel7_IRQHandler
+ .thumb_set BDMA_Channel7_IRQHandler,Default_Handler
+
+ .weak COMP1_IRQHandler
+ .thumb_set COMP1_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak LPTIM4_IRQHandler
+ .thumb_set LPTIM4_IRQHandler,Default_Handler
+
+ .weak LPTIM5_IRQHandler
+ .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak CRS_IRQHandler
+ .thumb_set CRS_IRQHandler,Default_Handler
+
+ .weak ECC_IRQHandler
+ .thumb_set ECC_IRQHandler,Default_Handler
+
+ .weak SAI4_IRQHandler
+ .thumb_set SAI4_IRQHandler,Default_Handler
+
+ .weak DTS_IRQHandler
+ .thumb_set DTS_IRQHandler,Default_Handler
+
+ .weak WAKEUP_PIN_IRQHandler
+ .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+ .weak OCTOSPI2_IRQHandler
+ .thumb_set OCTOSPI2_IRQHandler,Default_Handler
+
+ .weak OTFDEC1_IRQHandler
+ .thumb_set OTFDEC1_IRQHandler,Default_Handler
+
+ .weak OTFDEC2_IRQHandler
+ .thumb_set OTFDEC2_IRQHandler,Default_Handler
+
+ .weak FMAC_IRQHandler
+ .thumb_set FMAC_IRQHandler,Default_Handler
+
+ .weak CORDIC_IRQHandler
+ .thumb_set CORDIC_IRQHandler,Default_Handler
+
+ .weak UART9_IRQHandler
+ .thumb_set UART9_IRQHandler,Default_Handler
+
+ .weak USART10_IRQHandler
+ .thumb_set USART10_IRQHandler,Default_Handler
+
+ .weak I2C5_EV_IRQHandler
+ .thumb_set I2C5_EV_IRQHandler,Default_Handler
+
+ .weak I2C5_ER_IRQHandler
+ .thumb_set I2C5_ER_IRQHandler,Default_Handler
+
+ .weak FDCAN3_IT0_IRQHandler
+ .thumb_set FDCAN3_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN3_IT1_IRQHandler
+ .thumb_set FDCAN3_IT1_IRQHandler,Default_Handler
+
+ .weak TIM23_IRQHandler
+ .thumb_set TIM23_IRQHandler,Default_Handler
+
+ .weak TIM24_IRQHandler
+ .thumb_set TIM24_IRQHandler,Default_Handler
+
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h733xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h733xx.s new file mode 100644 index 0000000..c953724 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h733xx.s @@ -0,0 +1,765 @@ +/**
+ ******************************************************************************
+ * @file startup_stm32h733xx.s
+ * @author MCD Application Team
+ * @brief STM32H733xx Devices vector table for GCC based toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m7
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+ /* External Interrupts */
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
+ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_IRQHandler /* EXTI Line0 */
+ .word EXTI1_IRQHandler /* EXTI Line1 */
+ .word EXTI2_IRQHandler /* EXTI Line2 */
+ .word EXTI3_IRQHandler /* EXTI Line3 */
+ .word EXTI4_IRQHandler /* EXTI Line4 */
+ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
+ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
+ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
+ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
+ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
+ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
+ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
+ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
+ .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
+ .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
+ .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
+ .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
+ .word EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
+ .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
+ .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM4_IRQHandler /* TIM4 */
+ .word I2C1_EV_IRQHandler /* I2C1 Event */
+ .word I2C1_ER_IRQHandler /* I2C1 Error */
+ .word I2C2_EV_IRQHandler /* I2C2 Event */
+ .word I2C2_ER_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
+ .word 0 /* Reserved */
+ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
+ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
+ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
+ .word FMC_IRQHandler /* FMC */
+ .word SDMMC1_IRQHandler /* SDMMC1 */
+ .word TIM5_IRQHandler /* TIM5 */
+ .word SPI3_IRQHandler /* SPI3 */
+ .word UART4_IRQHandler /* UART4 */
+ .word UART5_IRQHandler /* UART5 */
+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
+ .word TIM7_IRQHandler /* TIM7 */
+ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
+ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
+ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
+ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
+ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
+ .word ETH_IRQHandler /* Ethernet */
+ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
+ .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
+ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
+ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
+ .word USART6_IRQHandler /* USART6 */
+ .word I2C3_EV_IRQHandler /* I2C3 event */
+ .word I2C3_ER_IRQHandler /* I2C3 error */
+ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
+ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
+ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
+ .word OTG_HS_IRQHandler /* USB OTG HS */
+ .word DCMI_PSSI_IRQHandler /* DCMI, PSSI */
+ .word CRYP_IRQHandler /* CRYP */
+ .word HASH_RNG_IRQHandler /* Hash and Rng */
+ .word FPU_IRQHandler /* FPU */
+ .word UART7_IRQHandler /* UART7 */
+ .word UART8_IRQHandler /* UART8 */
+ .word SPI4_IRQHandler /* SPI4 */
+ .word SPI5_IRQHandler /* SPI5 */
+ .word SPI6_IRQHandler /* SPI6 */
+ .word SAI1_IRQHandler /* SAI1 */
+ .word LTDC_IRQHandler /* LTDC */
+ .word LTDC_ER_IRQHandler /* LTDC error */
+ .word DMA2D_IRQHandler /* DMA2D */
+ .word 0 /* Reserved */
+ .word OCTOSPI1_IRQHandler /* OCTOSPI1 */
+ .word LPTIM1_IRQHandler /* LPTIM1 */
+ .word CEC_IRQHandler /* HDMI_CEC */
+ .word I2C4_EV_IRQHandler /* I2C4 Event */
+ .word I2C4_ER_IRQHandler /* I2C4 Error */
+ .word SPDIF_RX_IRQHandler /* SPDIF_RX */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
+ .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
+ .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
+ .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
+ .word 0 /* Reserved */
+ .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
+ .word TIM15_IRQHandler /* TIM15 global Interrupt */
+ .word TIM16_IRQHandler /* TIM16 global Interrupt */
+ .word TIM17_IRQHandler /* TIM17 global Interrupt */
+ .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
+ .word MDIOS_IRQHandler /* MDIOS global Interrupt */
+ .word 0 /* Reserved */
+ .word MDMA_IRQHandler /* MDMA global Interrupt */
+ .word 0 /* Reserved */
+ .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
+ .word HSEM1_IRQHandler /* HSEM1 global Interrupt */
+ .word 0 /* Reserved */
+ .word ADC3_IRQHandler /* ADC3 global Interrupt */
+ .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
+ .word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
+ .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
+ .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
+ .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
+ .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
+ .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
+ .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
+ .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
+ .word COMP1_IRQHandler /* COMP1 global Interrupt */
+ .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
+ .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
+ .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
+ .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
+ .word LPUART1_IRQHandler /* LP UART1 interrupt */
+ .word 0 /* Reserved */
+ .word CRS_IRQHandler /* Clock Recovery Global Interrupt */
+ .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
+ .word SAI4_IRQHandler /* SAI4 global interrupt */
+ .word DTS_IRQHandler /* Digital Temperature Sensor interrupt */
+ .word 0 /* Reserved */
+ .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
+ .word OCTOSPI2_IRQHandler /* OCTOSPI2 Interrupt */
+ .word OTFDEC1_IRQHandler /* OTFDEC1 Interrupt */
+ .word OTFDEC2_IRQHandler /* OTFDEC2 Interrupt */
+ .word FMAC_IRQHandler /* FMAC Interrupt */
+ .word CORDIC_IRQHandler /* CORDIC Interrupt */
+ .word UART9_IRQHandler /* UART9 Interrupt */
+ .word USART10_IRQHandler /* UART10 Interrupt */
+ .word I2C5_EV_IRQHandler /* I2C5 Event Interrupt */
+ .word I2C5_ER_IRQHandler /* I2C5 Error Interrupt */
+ .word FDCAN3_IT0_IRQHandler /* FDCAN3 interrupt line 0 */
+ .word FDCAN3_IT1_IRQHandler /* FDCAN3 interrupt line 1 */
+ .word TIM23_IRQHandler /* TIM23 global interrupt */
+ .word TIM24_IRQHandler /* TIM24 global interrupt */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_AVD_IRQHandler
+ .thumb_set PVD_AVD_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream0_IRQHandler
+ .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream1_IRQHandler
+ .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream2_IRQHandler
+ .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream3_IRQHandler
+ .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream4_IRQHandler
+ .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream5_IRQHandler
+ .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream6_IRQHandler
+ .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT0_IRQHandler
+ .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT0_IRQHandler
+ .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT1_IRQHandler
+ .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT1_IRQHandler
+ .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_TIM12_IRQHandler
+ .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_TIM13_IRQHandler
+ .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_TIM14_IRQHandler
+ .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream7_IRQHandler
+ .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+ .weak FMC_IRQHandler
+ .thumb_set FMC_IRQHandler,Default_Handler
+
+ .weak SDMMC1_IRQHandler
+ .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream0_IRQHandler
+ .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream1_IRQHandler
+ .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream2_IRQHandler
+ .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream3_IRQHandler
+ .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream4_IRQHandler
+ .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+ .weak ETH_IRQHandler
+ .thumb_set ETH_IRQHandler,Default_Handler
+
+ .weak ETH_WKUP_IRQHandler
+ .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+ .weak FDCAN_CAL_IRQHandler
+ .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream5_IRQHandler
+ .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream6_IRQHandler
+ .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream7_IRQHandler
+ .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+ .weak USART6_IRQHandler
+ .thumb_set USART6_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_OUT_IRQHandler
+ .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_IN_IRQHandler
+ .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_HS_WKUP_IRQHandler
+ .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_HS_IRQHandler
+ .thumb_set OTG_HS_IRQHandler,Default_Handler
+
+ .weak DCMI_PSSI_IRQHandler
+ .thumb_set DCMI_PSSI_IRQHandler,Default_Handler
+
+ .weak CRYP_IRQHandler
+ .thumb_set CRYP_IRQHandler,Default_Handler
+
+ .weak HASH_RNG_IRQHandler
+ .thumb_set HASH_RNG_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak UART7_IRQHandler
+ .thumb_set UART7_IRQHandler,Default_Handler
+
+ .weak UART8_IRQHandler
+ .thumb_set UART8_IRQHandler,Default_Handler
+
+ .weak SPI4_IRQHandler
+ .thumb_set SPI4_IRQHandler,Default_Handler
+
+ .weak SPI5_IRQHandler
+ .thumb_set SPI5_IRQHandler,Default_Handler
+
+ .weak SPI6_IRQHandler
+ .thumb_set SPI6_IRQHandler,Default_Handler
+
+ .weak SAI1_IRQHandler
+ .thumb_set SAI1_IRQHandler,Default_Handler
+
+ .weak LTDC_IRQHandler
+ .thumb_set LTDC_IRQHandler,Default_Handler
+
+ .weak LTDC_ER_IRQHandler
+ .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+ .weak DMA2D_IRQHandler
+ .thumb_set DMA2D_IRQHandler,Default_Handler
+
+ .weak OCTOSPI1_IRQHandler
+ .thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak I2C4_EV_IRQHandler
+ .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+ .weak I2C4_ER_IRQHandler
+ .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+ .weak SPDIF_RX_IRQHandler
+ .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+ .weak DMAMUX1_OVR_IRQHandler
+ .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT0_IRQHandler
+ .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT1_IRQHandler
+ .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT2_IRQHandler
+ .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT3_IRQHandler
+ .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+ .weak SWPMI1_IRQHandler
+ .thumb_set SWPMI1_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak MDIOS_WKUP_IRQHandler
+ .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
+
+ .weak MDIOS_IRQHandler
+ .thumb_set MDIOS_IRQHandler,Default_Handler
+
+ .weak MDMA_IRQHandler
+ .thumb_set MDMA_IRQHandler,Default_Handler
+
+ .weak SDMMC2_IRQHandler
+ .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+ .weak HSEM1_IRQHandler
+ .thumb_set HSEM1_IRQHandler,Default_Handler
+
+ .weak ADC3_IRQHandler
+ .thumb_set ADC3_IRQHandler,Default_Handler
+
+ .weak DMAMUX2_OVR_IRQHandler
+ .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel0_IRQHandler
+ .thumb_set BDMA_Channel0_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel1_IRQHandler
+ .thumb_set BDMA_Channel1_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel2_IRQHandler
+ .thumb_set BDMA_Channel2_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel3_IRQHandler
+ .thumb_set BDMA_Channel3_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel4_IRQHandler
+ .thumb_set BDMA_Channel4_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel5_IRQHandler
+ .thumb_set BDMA_Channel5_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel6_IRQHandler
+ .thumb_set BDMA_Channel6_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel7_IRQHandler
+ .thumb_set BDMA_Channel7_IRQHandler,Default_Handler
+
+ .weak COMP1_IRQHandler
+ .thumb_set COMP1_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak LPTIM4_IRQHandler
+ .thumb_set LPTIM4_IRQHandler,Default_Handler
+
+ .weak LPTIM5_IRQHandler
+ .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak CRS_IRQHandler
+ .thumb_set CRS_IRQHandler,Default_Handler
+
+ .weak ECC_IRQHandler
+ .thumb_set ECC_IRQHandler,Default_Handler
+
+ .weak SAI4_IRQHandler
+ .thumb_set SAI4_IRQHandler,Default_Handler
+
+ .weak DTS_IRQHandler
+ .thumb_set DTS_IRQHandler,Default_Handler
+
+ .weak WAKEUP_PIN_IRQHandler
+ .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+ .weak OCTOSPI2_IRQHandler
+ .thumb_set OCTOSPI2_IRQHandler,Default_Handler
+
+ .weak OTFDEC1_IRQHandler
+ .thumb_set OTFDEC1_IRQHandler,Default_Handler
+
+ .weak OTFDEC2_IRQHandler
+ .thumb_set OTFDEC2_IRQHandler,Default_Handler
+
+ .weak FMAC_IRQHandler
+ .thumb_set FMAC_IRQHandler,Default_Handler
+
+ .weak CORDIC_IRQHandler
+ .thumb_set CORDIC_IRQHandler,Default_Handler
+
+ .weak UART9_IRQHandler
+ .thumb_set UART9_IRQHandler,Default_Handler
+
+ .weak USART10_IRQHandler
+ .thumb_set USART10_IRQHandler,Default_Handler
+
+ .weak I2C5_EV_IRQHandler
+ .thumb_set I2C5_EV_IRQHandler,Default_Handler
+
+ .weak I2C5_ER_IRQHandler
+ .thumb_set I2C5_ER_IRQHandler,Default_Handler
+
+ .weak FDCAN3_IT0_IRQHandler
+ .thumb_set FDCAN3_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN3_IT1_IRQHandler
+ .thumb_set FDCAN3_IT1_IRQHandler,Default_Handler
+
+ .weak TIM23_IRQHandler
+ .thumb_set TIM23_IRQHandler,Default_Handler
+
+ .weak TIM24_IRQHandler
+ .thumb_set TIM24_IRQHandler,Default_Handler
+
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h735xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h735xx.s new file mode 100644 index 0000000..7c0b54a --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h735xx.s @@ -0,0 +1,765 @@ +/**
+ ******************************************************************************
+ * @file startup_stm32h735xx.s
+ * @author MCD Application Team
+ * @brief STM32H735xx Devices vector table for GCC based toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m7
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+ /* External Interrupts */
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
+ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_IRQHandler /* EXTI Line0 */
+ .word EXTI1_IRQHandler /* EXTI Line1 */
+ .word EXTI2_IRQHandler /* EXTI Line2 */
+ .word EXTI3_IRQHandler /* EXTI Line3 */
+ .word EXTI4_IRQHandler /* EXTI Line4 */
+ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
+ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
+ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
+ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
+ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
+ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
+ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
+ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
+ .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
+ .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
+ .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
+ .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
+ .word EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
+ .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
+ .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM4_IRQHandler /* TIM4 */
+ .word I2C1_EV_IRQHandler /* I2C1 Event */
+ .word I2C1_ER_IRQHandler /* I2C1 Error */
+ .word I2C2_EV_IRQHandler /* I2C2 Event */
+ .word I2C2_ER_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
+ .word 0 /* Reserved */
+ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
+ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
+ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
+ .word FMC_IRQHandler /* FMC */
+ .word SDMMC1_IRQHandler /* SDMMC1 */
+ .word TIM5_IRQHandler /* TIM5 */
+ .word SPI3_IRQHandler /* SPI3 */
+ .word UART4_IRQHandler /* UART4 */
+ .word UART5_IRQHandler /* UART5 */
+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
+ .word TIM7_IRQHandler /* TIM7 */
+ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
+ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
+ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
+ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
+ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
+ .word ETH_IRQHandler /* Ethernet */
+ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
+ .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
+ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
+ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
+ .word USART6_IRQHandler /* USART6 */
+ .word I2C3_EV_IRQHandler /* I2C3 event */
+ .word I2C3_ER_IRQHandler /* I2C3 error */
+ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
+ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
+ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
+ .word OTG_HS_IRQHandler /* USB OTG HS */
+ .word DCMI_PSSI_IRQHandler /* DCMI, PSSI */
+ .word CRYP_IRQHandler /* CRYP */
+ .word HASH_RNG_IRQHandler /* Hash and Rng */
+ .word FPU_IRQHandler /* FPU */
+ .word UART7_IRQHandler /* UART7 */
+ .word UART8_IRQHandler /* UART8 */
+ .word SPI4_IRQHandler /* SPI4 */
+ .word SPI5_IRQHandler /* SPI5 */
+ .word SPI6_IRQHandler /* SPI6 */
+ .word SAI1_IRQHandler /* SAI1 */
+ .word LTDC_IRQHandler /* LTDC */
+ .word LTDC_ER_IRQHandler /* LTDC error */
+ .word DMA2D_IRQHandler /* DMA2D */
+ .word 0 /* Reserved */
+ .word OCTOSPI1_IRQHandler /* OCTOSPI1 */
+ .word LPTIM1_IRQHandler /* LPTIM1 */
+ .word CEC_IRQHandler /* HDMI_CEC */
+ .word I2C4_EV_IRQHandler /* I2C4 Event */
+ .word I2C4_ER_IRQHandler /* I2C4 Error */
+ .word SPDIF_RX_IRQHandler /* SPDIF_RX */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
+ .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
+ .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
+ .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
+ .word 0 /* Reserved */
+ .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
+ .word TIM15_IRQHandler /* TIM15 global Interrupt */
+ .word TIM16_IRQHandler /* TIM16 global Interrupt */
+ .word TIM17_IRQHandler /* TIM17 global Interrupt */
+ .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
+ .word MDIOS_IRQHandler /* MDIOS global Interrupt */
+ .word 0 /* Reserved */
+ .word MDMA_IRQHandler /* MDMA global Interrupt */
+ .word 0 /* Reserved */
+ .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
+ .word HSEM1_IRQHandler /* HSEM1 global Interrupt */
+ .word 0 /* Reserved */
+ .word ADC3_IRQHandler /* ADC3 global Interrupt */
+ .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
+ .word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
+ .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
+ .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
+ .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
+ .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
+ .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
+ .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
+ .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
+ .word COMP1_IRQHandler /* COMP1 global Interrupt */
+ .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
+ .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
+ .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
+ .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
+ .word LPUART1_IRQHandler /* LP UART1 interrupt */
+ .word 0 /* Reserved */
+ .word CRS_IRQHandler /* Clock Recovery Global Interrupt */
+ .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
+ .word SAI4_IRQHandler /* SAI4 global interrupt */
+ .word DTS_IRQHandler /* Digital Temperature Sensor interrupt */
+ .word 0 /* Reserved */
+ .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
+ .word OCTOSPI2_IRQHandler /* OCTOSPI2 Interrupt */
+ .word OTFDEC1_IRQHandler /* OTFDEC1 Interrupt */
+ .word OTFDEC2_IRQHandler /* OTFDEC2 Interrupt */
+ .word FMAC_IRQHandler /* FMAC Interrupt */
+ .word CORDIC_IRQHandler /* CORDIC Interrupt */
+ .word UART9_IRQHandler /* UART9 Interrupt */
+ .word USART10_IRQHandler /* UART10 Interrupt */
+ .word I2C5_EV_IRQHandler /* I2C5 Event Interrupt */
+ .word I2C5_ER_IRQHandler /* I2C5 Error Interrupt */
+ .word FDCAN3_IT0_IRQHandler /* FDCAN3 interrupt line 0 */
+ .word FDCAN3_IT1_IRQHandler /* FDCAN3 interrupt line 1 */
+ .word TIM23_IRQHandler /* TIM23 global interrupt */
+ .word TIM24_IRQHandler /* TIM24 global interrupt */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_AVD_IRQHandler
+ .thumb_set PVD_AVD_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream0_IRQHandler
+ .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream1_IRQHandler
+ .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream2_IRQHandler
+ .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream3_IRQHandler
+ .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream4_IRQHandler
+ .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream5_IRQHandler
+ .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream6_IRQHandler
+ .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT0_IRQHandler
+ .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT0_IRQHandler
+ .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT1_IRQHandler
+ .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT1_IRQHandler
+ .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_TIM12_IRQHandler
+ .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_TIM13_IRQHandler
+ .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_TIM14_IRQHandler
+ .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream7_IRQHandler
+ .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+ .weak FMC_IRQHandler
+ .thumb_set FMC_IRQHandler,Default_Handler
+
+ .weak SDMMC1_IRQHandler
+ .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream0_IRQHandler
+ .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream1_IRQHandler
+ .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream2_IRQHandler
+ .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream3_IRQHandler
+ .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream4_IRQHandler
+ .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+ .weak ETH_IRQHandler
+ .thumb_set ETH_IRQHandler,Default_Handler
+
+ .weak ETH_WKUP_IRQHandler
+ .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+ .weak FDCAN_CAL_IRQHandler
+ .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream5_IRQHandler
+ .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream6_IRQHandler
+ .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream7_IRQHandler
+ .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+ .weak USART6_IRQHandler
+ .thumb_set USART6_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_OUT_IRQHandler
+ .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_IN_IRQHandler
+ .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_HS_WKUP_IRQHandler
+ .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_HS_IRQHandler
+ .thumb_set OTG_HS_IRQHandler,Default_Handler
+
+ .weak DCMI_PSSI_IRQHandler
+ .thumb_set DCMI_PSSI_IRQHandler,Default_Handler
+
+ .weak CRYP_IRQHandler
+ .thumb_set CRYP_IRQHandler,Default_Handler
+
+ .weak HASH_RNG_IRQHandler
+ .thumb_set HASH_RNG_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak UART7_IRQHandler
+ .thumb_set UART7_IRQHandler,Default_Handler
+
+ .weak UART8_IRQHandler
+ .thumb_set UART8_IRQHandler,Default_Handler
+
+ .weak SPI4_IRQHandler
+ .thumb_set SPI4_IRQHandler,Default_Handler
+
+ .weak SPI5_IRQHandler
+ .thumb_set SPI5_IRQHandler,Default_Handler
+
+ .weak SPI6_IRQHandler
+ .thumb_set SPI6_IRQHandler,Default_Handler
+
+ .weak SAI1_IRQHandler
+ .thumb_set SAI1_IRQHandler,Default_Handler
+
+ .weak LTDC_IRQHandler
+ .thumb_set LTDC_IRQHandler,Default_Handler
+
+ .weak LTDC_ER_IRQHandler
+ .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+ .weak DMA2D_IRQHandler
+ .thumb_set DMA2D_IRQHandler,Default_Handler
+
+ .weak OCTOSPI1_IRQHandler
+ .thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak I2C4_EV_IRQHandler
+ .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+ .weak I2C4_ER_IRQHandler
+ .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+ .weak SPDIF_RX_IRQHandler
+ .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+ .weak DMAMUX1_OVR_IRQHandler
+ .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT0_IRQHandler
+ .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT1_IRQHandler
+ .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT2_IRQHandler
+ .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT3_IRQHandler
+ .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+ .weak SWPMI1_IRQHandler
+ .thumb_set SWPMI1_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak MDIOS_WKUP_IRQHandler
+ .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
+
+ .weak MDIOS_IRQHandler
+ .thumb_set MDIOS_IRQHandler,Default_Handler
+
+ .weak MDMA_IRQHandler
+ .thumb_set MDMA_IRQHandler,Default_Handler
+
+ .weak SDMMC2_IRQHandler
+ .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+ .weak HSEM1_IRQHandler
+ .thumb_set HSEM1_IRQHandler,Default_Handler
+
+ .weak ADC3_IRQHandler
+ .thumb_set ADC3_IRQHandler,Default_Handler
+
+ .weak DMAMUX2_OVR_IRQHandler
+ .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel0_IRQHandler
+ .thumb_set BDMA_Channel0_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel1_IRQHandler
+ .thumb_set BDMA_Channel1_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel2_IRQHandler
+ .thumb_set BDMA_Channel2_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel3_IRQHandler
+ .thumb_set BDMA_Channel3_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel4_IRQHandler
+ .thumb_set BDMA_Channel4_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel5_IRQHandler
+ .thumb_set BDMA_Channel5_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel6_IRQHandler
+ .thumb_set BDMA_Channel6_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel7_IRQHandler
+ .thumb_set BDMA_Channel7_IRQHandler,Default_Handler
+
+ .weak COMP1_IRQHandler
+ .thumb_set COMP1_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak LPTIM4_IRQHandler
+ .thumb_set LPTIM4_IRQHandler,Default_Handler
+
+ .weak LPTIM5_IRQHandler
+ .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak CRS_IRQHandler
+ .thumb_set CRS_IRQHandler,Default_Handler
+
+ .weak ECC_IRQHandler
+ .thumb_set ECC_IRQHandler,Default_Handler
+
+ .weak SAI4_IRQHandler
+ .thumb_set SAI4_IRQHandler,Default_Handler
+
+ .weak DTS_IRQHandler
+ .thumb_set DTS_IRQHandler,Default_Handler
+
+ .weak WAKEUP_PIN_IRQHandler
+ .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+ .weak OCTOSPI2_IRQHandler
+ .thumb_set OCTOSPI2_IRQHandler,Default_Handler
+
+ .weak OTFDEC1_IRQHandler
+ .thumb_set OTFDEC1_IRQHandler,Default_Handler
+
+ .weak OTFDEC2_IRQHandler
+ .thumb_set OTFDEC2_IRQHandler,Default_Handler
+
+ .weak FMAC_IRQHandler
+ .thumb_set FMAC_IRQHandler,Default_Handler
+
+ .weak CORDIC_IRQHandler
+ .thumb_set CORDIC_IRQHandler,Default_Handler
+
+ .weak UART9_IRQHandler
+ .thumb_set UART9_IRQHandler,Default_Handler
+
+ .weak USART10_IRQHandler
+ .thumb_set USART10_IRQHandler,Default_Handler
+
+ .weak I2C5_EV_IRQHandler
+ .thumb_set I2C5_EV_IRQHandler,Default_Handler
+
+ .weak I2C5_ER_IRQHandler
+ .thumb_set I2C5_ER_IRQHandler,Default_Handler
+
+ .weak FDCAN3_IT0_IRQHandler
+ .thumb_set FDCAN3_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN3_IT1_IRQHandler
+ .thumb_set FDCAN3_IT1_IRQHandler,Default_Handler
+
+ .weak TIM23_IRQHandler
+ .thumb_set TIM23_IRQHandler,Default_Handler
+
+ .weak TIM24_IRQHandler
+ .thumb_set TIM24_IRQHandler,Default_Handler
+
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h742xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h742xx.s new file mode 100644 index 0000000..03f8539 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h742xx.s @@ -0,0 +1,740 @@ +/**
+ ******************************************************************************
+ * @file startup_stm32h742xx.s
+ * @author MCD Application Team
+ * @brief STM32H742xx Devices vector table for GCC based toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m7
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+ /* External Interrupts */
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
+ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_IRQHandler /* EXTI Line0 */
+ .word EXTI1_IRQHandler /* EXTI Line1 */
+ .word EXTI2_IRQHandler /* EXTI Line2 */
+ .word EXTI3_IRQHandler /* EXTI Line3 */
+ .word EXTI4_IRQHandler /* EXTI Line4 */
+ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
+ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
+ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
+ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
+ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
+ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
+ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
+ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
+ .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
+ .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
+ .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
+ .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
+ .word EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
+ .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
+ .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM4_IRQHandler /* TIM4 */
+ .word I2C1_EV_IRQHandler /* I2C1 Event */
+ .word I2C1_ER_IRQHandler /* I2C1 Error */
+ .word I2C2_EV_IRQHandler /* I2C2 Event */
+ .word I2C2_ER_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
+ .word 0 /* Reserved */
+ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
+ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
+ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
+ .word FMC_IRQHandler /* FMC */
+ .word SDMMC1_IRQHandler /* SDMMC1 */
+ .word TIM5_IRQHandler /* TIM5 */
+ .word SPI3_IRQHandler /* SPI3 */
+ .word UART4_IRQHandler /* UART4 */
+ .word UART5_IRQHandler /* UART5 */
+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
+ .word TIM7_IRQHandler /* TIM7 */
+ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
+ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
+ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
+ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
+ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
+ .word ETH_IRQHandler /* Ethernet */
+ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
+ .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
+ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
+ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
+ .word USART6_IRQHandler /* USART6 */
+ .word I2C3_EV_IRQHandler /* I2C3 event */
+ .word I2C3_ER_IRQHandler /* I2C3 error */
+ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
+ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
+ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
+ .word OTG_HS_IRQHandler /* USB OTG HS */
+ .word DCMI_IRQHandler /* DCMI */
+ .word 0 /* Reserved */
+ .word RNG_IRQHandler /* Rng */
+ .word FPU_IRQHandler /* FPU */
+ .word UART7_IRQHandler /* UART7 */
+ .word UART8_IRQHandler /* UART8 */
+ .word SPI4_IRQHandler /* SPI4 */
+ .word SPI5_IRQHandler /* SPI5 */
+ .word SPI6_IRQHandler /* SPI6 */
+ .word SAI1_IRQHandler /* SAI1 */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMA2D_IRQHandler /* DMA2D */
+ .word SAI2_IRQHandler /* SAI2 */
+ .word QUADSPI_IRQHandler /* QUADSPI */
+ .word LPTIM1_IRQHandler /* LPTIM1 */
+ .word CEC_IRQHandler /* HDMI_CEC */
+ .word I2C4_EV_IRQHandler /* I2C4 Event */
+ .word I2C4_ER_IRQHandler /* I2C4 Error */
+ .word SPDIF_RX_IRQHandler /* SPDIF_RX */
+ .word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */
+ .word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */
+ .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */
+ .word OTG_FS_IRQHandler /* USB OTG FS */
+ .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
+ .word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */
+ .word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */
+ .word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */
+ .word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */
+ .word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */
+ .word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */
+ .word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */
+ .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
+ .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
+ .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
+ .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
+ .word SAI3_IRQHandler /* SAI3 global Interrupt */
+ .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
+ .word TIM15_IRQHandler /* TIM15 global Interrupt */
+ .word TIM16_IRQHandler /* TIM16 global Interrupt */
+ .word TIM17_IRQHandler /* TIM17 global Interrupt */
+ .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
+ .word MDIOS_IRQHandler /* MDIOS global Interrupt */
+ .word 0 /* Reserved */
+ .word MDMA_IRQHandler /* MDMA global Interrupt */
+ .word 0 /* Reserved */
+ .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
+ .word HSEM1_IRQHandler /* HSEM1 global Interrupt */
+ .word 0 /* Reserved */
+ .word ADC3_IRQHandler /* ADC3 global Interrupt */
+ .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
+ .word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
+ .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
+ .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
+ .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
+ .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
+ .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
+ .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
+ .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
+ .word COMP1_IRQHandler /* COMP1 global Interrupt */
+ .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
+ .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
+ .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
+ .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
+ .word LPUART1_IRQHandler /* LP UART1 interrupt */
+ .word 0 /* Reserved */
+ .word CRS_IRQHandler /* Clock Recovery Global Interrupt */
+ .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
+ .word SAI4_IRQHandler /* SAI4 global interrupt */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_AVD_IRQHandler
+ .thumb_set PVD_AVD_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream0_IRQHandler
+ .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream1_IRQHandler
+ .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream2_IRQHandler
+ .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream3_IRQHandler
+ .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream4_IRQHandler
+ .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream5_IRQHandler
+ .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream6_IRQHandler
+ .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT0_IRQHandler
+ .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT0_IRQHandler
+ .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT1_IRQHandler
+ .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT1_IRQHandler
+ .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_TIM12_IRQHandler
+ .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_TIM13_IRQHandler
+ .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_TIM14_IRQHandler
+ .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream7_IRQHandler
+ .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+ .weak FMC_IRQHandler
+ .thumb_set FMC_IRQHandler,Default_Handler
+
+ .weak SDMMC1_IRQHandler
+ .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream0_IRQHandler
+ .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream1_IRQHandler
+ .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream2_IRQHandler
+ .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream3_IRQHandler
+ .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream4_IRQHandler
+ .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+ .weak ETH_IRQHandler
+ .thumb_set ETH_IRQHandler,Default_Handler
+
+ .weak ETH_WKUP_IRQHandler
+ .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+ .weak FDCAN_CAL_IRQHandler
+ .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream5_IRQHandler
+ .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream6_IRQHandler
+ .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream7_IRQHandler
+ .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+ .weak USART6_IRQHandler
+ .thumb_set USART6_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_OUT_IRQHandler
+ .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_IN_IRQHandler
+ .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_HS_WKUP_IRQHandler
+ .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_HS_IRQHandler
+ .thumb_set OTG_HS_IRQHandler,Default_Handler
+
+ .weak DCMI_IRQHandler
+ .thumb_set DCMI_IRQHandler,Default_Handler
+
+ .weak RNG_IRQHandler
+ .thumb_set RNG_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak UART7_IRQHandler
+ .thumb_set UART7_IRQHandler,Default_Handler
+
+ .weak UART8_IRQHandler
+ .thumb_set UART8_IRQHandler,Default_Handler
+
+ .weak SPI4_IRQHandler
+ .thumb_set SPI4_IRQHandler,Default_Handler
+
+ .weak SPI5_IRQHandler
+ .thumb_set SPI5_IRQHandler,Default_Handler
+
+ .weak SPI6_IRQHandler
+ .thumb_set SPI6_IRQHandler,Default_Handler
+
+ .weak SAI1_IRQHandler
+ .thumb_set SAI1_IRQHandler,Default_Handler
+
+ .weak DMA2D_IRQHandler
+ .thumb_set DMA2D_IRQHandler,Default_Handler
+
+ .weak SAI2_IRQHandler
+ .thumb_set SAI2_IRQHandler,Default_Handler
+
+ .weak QUADSPI_IRQHandler
+ .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak I2C4_EV_IRQHandler
+ .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+ .weak I2C4_ER_IRQHandler
+ .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+ .weak SPDIF_RX_IRQHandler
+ .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+ .weak OTG_FS_EP1_OUT_IRQHandler
+ .thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_FS_EP1_IN_IRQHandler
+ .thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_FS_WKUP_IRQHandler
+ .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_FS_IRQHandler
+ .thumb_set OTG_FS_IRQHandler,Default_Handler
+
+ .weak DMAMUX1_OVR_IRQHandler
+ .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+ .weak HRTIM1_Master_IRQHandler
+ .thumb_set HRTIM1_Master_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMA_IRQHandler
+ .thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMB_IRQHandler
+ .thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMC_IRQHandler
+ .thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMD_IRQHandler
+ .thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIME_IRQHandler
+ .thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
+
+ .weak HRTIM1_FLT_IRQHandler
+ .thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT0_IRQHandler
+ .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT1_IRQHandler
+ .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT2_IRQHandler
+ .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT3_IRQHandler
+ .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+ .weak SAI3_IRQHandler
+ .thumb_set SAI3_IRQHandler,Default_Handler
+
+ .weak SWPMI1_IRQHandler
+ .thumb_set SWPMI1_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak MDIOS_WKUP_IRQHandler
+ .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
+
+ .weak MDIOS_IRQHandler
+ .thumb_set MDIOS_IRQHandler,Default_Handler
+
+ .weak MDMA_IRQHandler
+ .thumb_set MDMA_IRQHandler,Default_Handler
+
+ .weak SDMMC2_IRQHandler
+ .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+ .weak HSEM1_IRQHandler
+ .thumb_set HSEM1_IRQHandler,Default_Handler
+
+ .weak ADC3_IRQHandler
+ .thumb_set ADC3_IRQHandler,Default_Handler
+
+ .weak DMAMUX2_OVR_IRQHandler
+ .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel0_IRQHandler
+ .thumb_set BDMA_Channel0_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel1_IRQHandler
+ .thumb_set BDMA_Channel1_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel2_IRQHandler
+ .thumb_set BDMA_Channel2_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel3_IRQHandler
+ .thumb_set BDMA_Channel3_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel4_IRQHandler
+ .thumb_set BDMA_Channel4_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel5_IRQHandler
+ .thumb_set BDMA_Channel5_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel6_IRQHandler
+ .thumb_set BDMA_Channel6_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel7_IRQHandler
+ .thumb_set BDMA_Channel7_IRQHandler,Default_Handler
+
+ .weak COMP1_IRQHandler
+ .thumb_set COMP1_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak LPTIM4_IRQHandler
+ .thumb_set LPTIM4_IRQHandler,Default_Handler
+
+ .weak LPTIM5_IRQHandler
+ .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak CRS_IRQHandler
+ .thumb_set CRS_IRQHandler,Default_Handler
+
+ .weak ECC_IRQHandler
+ .thumb_set ECC_IRQHandler,Default_Handler
+
+ .weak SAI4_IRQHandler
+ .thumb_set SAI4_IRQHandler,Default_Handler
+
+ .weak WAKEUP_PIN_IRQHandler
+ .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h743xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h743xx.s new file mode 100644 index 0000000..cbc5446 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h743xx.s @@ -0,0 +1,749 @@ +/**
+ ******************************************************************************
+ * @file startup_stm32h743xx.s
+ * @author MCD Application Team
+ * @brief STM32H743xx Devices vector table for GCC based toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m7
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+ /* External Interrupts */
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
+ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_IRQHandler /* EXTI Line0 */
+ .word EXTI1_IRQHandler /* EXTI Line1 */
+ .word EXTI2_IRQHandler /* EXTI Line2 */
+ .word EXTI3_IRQHandler /* EXTI Line3 */
+ .word EXTI4_IRQHandler /* EXTI Line4 */
+ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
+ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
+ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
+ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
+ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
+ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
+ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
+ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
+ .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
+ .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
+ .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
+ .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
+ .word EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
+ .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
+ .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM4_IRQHandler /* TIM4 */
+ .word I2C1_EV_IRQHandler /* I2C1 Event */
+ .word I2C1_ER_IRQHandler /* I2C1 Error */
+ .word I2C2_EV_IRQHandler /* I2C2 Event */
+ .word I2C2_ER_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
+ .word 0 /* Reserved */
+ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
+ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
+ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
+ .word FMC_IRQHandler /* FMC */
+ .word SDMMC1_IRQHandler /* SDMMC1 */
+ .word TIM5_IRQHandler /* TIM5 */
+ .word SPI3_IRQHandler /* SPI3 */
+ .word UART4_IRQHandler /* UART4 */
+ .word UART5_IRQHandler /* UART5 */
+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
+ .word TIM7_IRQHandler /* TIM7 */
+ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
+ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
+ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
+ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
+ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
+ .word ETH_IRQHandler /* Ethernet */
+ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
+ .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
+ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
+ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
+ .word USART6_IRQHandler /* USART6 */
+ .word I2C3_EV_IRQHandler /* I2C3 event */
+ .word I2C3_ER_IRQHandler /* I2C3 error */
+ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
+ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
+ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
+ .word OTG_HS_IRQHandler /* USB OTG HS */
+ .word DCMI_IRQHandler /* DCMI */
+ .word 0 /* Reserved */
+ .word RNG_IRQHandler /* Rng */
+ .word FPU_IRQHandler /* FPU */
+ .word UART7_IRQHandler /* UART7 */
+ .word UART8_IRQHandler /* UART8 */
+ .word SPI4_IRQHandler /* SPI4 */
+ .word SPI5_IRQHandler /* SPI5 */
+ .word SPI6_IRQHandler /* SPI6 */
+ .word SAI1_IRQHandler /* SAI1 */
+ .word LTDC_IRQHandler /* LTDC */
+ .word LTDC_ER_IRQHandler /* LTDC error */
+ .word DMA2D_IRQHandler /* DMA2D */
+ .word SAI2_IRQHandler /* SAI2 */
+ .word QUADSPI_IRQHandler /* QUADSPI */
+ .word LPTIM1_IRQHandler /* LPTIM1 */
+ .word CEC_IRQHandler /* HDMI_CEC */
+ .word I2C4_EV_IRQHandler /* I2C4 Event */
+ .word I2C4_ER_IRQHandler /* I2C4 Error */
+ .word SPDIF_RX_IRQHandler /* SPDIF_RX */
+ .word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */
+ .word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */
+ .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */
+ .word OTG_FS_IRQHandler /* USB OTG FS */
+ .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
+ .word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */
+ .word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */
+ .word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */
+ .word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */
+ .word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */
+ .word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */
+ .word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */
+ .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
+ .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
+ .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
+ .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
+ .word SAI3_IRQHandler /* SAI3 global Interrupt */
+ .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
+ .word TIM15_IRQHandler /* TIM15 global Interrupt */
+ .word TIM16_IRQHandler /* TIM16 global Interrupt */
+ .word TIM17_IRQHandler /* TIM17 global Interrupt */
+ .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
+ .word MDIOS_IRQHandler /* MDIOS global Interrupt */
+ .word JPEG_IRQHandler /* JPEG global Interrupt */
+ .word MDMA_IRQHandler /* MDMA global Interrupt */
+ .word 0 /* Reserved */
+ .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
+ .word HSEM1_IRQHandler /* HSEM1 global Interrupt */
+ .word 0 /* Reserved */
+ .word ADC3_IRQHandler /* ADC3 global Interrupt */
+ .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
+ .word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
+ .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
+ .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
+ .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
+ .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
+ .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
+ .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
+ .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
+ .word COMP1_IRQHandler /* COMP1 global Interrupt */
+ .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
+ .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
+ .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
+ .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
+ .word LPUART1_IRQHandler /* LP UART1 interrupt */
+ .word 0 /* Reserved */
+ .word CRS_IRQHandler /* Clock Recovery Global Interrupt */
+ .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
+ .word SAI4_IRQHandler /* SAI4 global interrupt */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_AVD_IRQHandler
+ .thumb_set PVD_AVD_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream0_IRQHandler
+ .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream1_IRQHandler
+ .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream2_IRQHandler
+ .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream3_IRQHandler
+ .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream4_IRQHandler
+ .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream5_IRQHandler
+ .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream6_IRQHandler
+ .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT0_IRQHandler
+ .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT0_IRQHandler
+ .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT1_IRQHandler
+ .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT1_IRQHandler
+ .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_TIM12_IRQHandler
+ .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_TIM13_IRQHandler
+ .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_TIM14_IRQHandler
+ .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream7_IRQHandler
+ .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+ .weak FMC_IRQHandler
+ .thumb_set FMC_IRQHandler,Default_Handler
+
+ .weak SDMMC1_IRQHandler
+ .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream0_IRQHandler
+ .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream1_IRQHandler
+ .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream2_IRQHandler
+ .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream3_IRQHandler
+ .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream4_IRQHandler
+ .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+ .weak ETH_IRQHandler
+ .thumb_set ETH_IRQHandler,Default_Handler
+
+ .weak ETH_WKUP_IRQHandler
+ .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+ .weak FDCAN_CAL_IRQHandler
+ .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream5_IRQHandler
+ .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream6_IRQHandler
+ .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream7_IRQHandler
+ .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+ .weak USART6_IRQHandler
+ .thumb_set USART6_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_OUT_IRQHandler
+ .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_IN_IRQHandler
+ .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_HS_WKUP_IRQHandler
+ .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_HS_IRQHandler
+ .thumb_set OTG_HS_IRQHandler,Default_Handler
+
+ .weak DCMI_IRQHandler
+ .thumb_set DCMI_IRQHandler,Default_Handler
+
+ .weak RNG_IRQHandler
+ .thumb_set RNG_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak UART7_IRQHandler
+ .thumb_set UART7_IRQHandler,Default_Handler
+
+ .weak UART8_IRQHandler
+ .thumb_set UART8_IRQHandler,Default_Handler
+
+ .weak SPI4_IRQHandler
+ .thumb_set SPI4_IRQHandler,Default_Handler
+
+ .weak SPI5_IRQHandler
+ .thumb_set SPI5_IRQHandler,Default_Handler
+
+ .weak SPI6_IRQHandler
+ .thumb_set SPI6_IRQHandler,Default_Handler
+
+ .weak SAI1_IRQHandler
+ .thumb_set SAI1_IRQHandler,Default_Handler
+
+ .weak LTDC_IRQHandler
+ .thumb_set LTDC_IRQHandler,Default_Handler
+
+ .weak LTDC_ER_IRQHandler
+ .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+ .weak DMA2D_IRQHandler
+ .thumb_set DMA2D_IRQHandler,Default_Handler
+
+ .weak SAI2_IRQHandler
+ .thumb_set SAI2_IRQHandler,Default_Handler
+
+ .weak QUADSPI_IRQHandler
+ .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak I2C4_EV_IRQHandler
+ .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+ .weak I2C4_ER_IRQHandler
+ .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+ .weak SPDIF_RX_IRQHandler
+ .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+ .weak OTG_FS_EP1_OUT_IRQHandler
+ .thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_FS_EP1_IN_IRQHandler
+ .thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_FS_WKUP_IRQHandler
+ .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_FS_IRQHandler
+ .thumb_set OTG_FS_IRQHandler,Default_Handler
+
+ .weak DMAMUX1_OVR_IRQHandler
+ .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+ .weak HRTIM1_Master_IRQHandler
+ .thumb_set HRTIM1_Master_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMA_IRQHandler
+ .thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMB_IRQHandler
+ .thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMC_IRQHandler
+ .thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMD_IRQHandler
+ .thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIME_IRQHandler
+ .thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
+
+ .weak HRTIM1_FLT_IRQHandler
+ .thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT0_IRQHandler
+ .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT1_IRQHandler
+ .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT2_IRQHandler
+ .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT3_IRQHandler
+ .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+ .weak SAI3_IRQHandler
+ .thumb_set SAI3_IRQHandler,Default_Handler
+
+ .weak SWPMI1_IRQHandler
+ .thumb_set SWPMI1_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak MDIOS_WKUP_IRQHandler
+ .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
+
+ .weak MDIOS_IRQHandler
+ .thumb_set MDIOS_IRQHandler,Default_Handler
+
+ .weak JPEG_IRQHandler
+ .thumb_set JPEG_IRQHandler,Default_Handler
+
+ .weak MDMA_IRQHandler
+ .thumb_set MDMA_IRQHandler,Default_Handler
+
+ .weak SDMMC2_IRQHandler
+ .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+ .weak HSEM1_IRQHandler
+ .thumb_set HSEM1_IRQHandler,Default_Handler
+
+ .weak ADC3_IRQHandler
+ .thumb_set ADC3_IRQHandler,Default_Handler
+
+ .weak DMAMUX2_OVR_IRQHandler
+ .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel0_IRQHandler
+ .thumb_set BDMA_Channel0_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel1_IRQHandler
+ .thumb_set BDMA_Channel1_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel2_IRQHandler
+ .thumb_set BDMA_Channel2_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel3_IRQHandler
+ .thumb_set BDMA_Channel3_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel4_IRQHandler
+ .thumb_set BDMA_Channel4_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel5_IRQHandler
+ .thumb_set BDMA_Channel5_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel6_IRQHandler
+ .thumb_set BDMA_Channel6_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel7_IRQHandler
+ .thumb_set BDMA_Channel7_IRQHandler,Default_Handler
+
+ .weak COMP1_IRQHandler
+ .thumb_set COMP1_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak LPTIM4_IRQHandler
+ .thumb_set LPTIM4_IRQHandler,Default_Handler
+
+ .weak LPTIM5_IRQHandler
+ .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak CRS_IRQHandler
+ .thumb_set CRS_IRQHandler,Default_Handler
+
+ .weak ECC_IRQHandler
+ .thumb_set ECC_IRQHandler,Default_Handler
+
+ .weak SAI4_IRQHandler
+ .thumb_set SAI4_IRQHandler,Default_Handler
+
+ .weak WAKEUP_PIN_IRQHandler
+ .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h745xg.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h745xg.s new file mode 100644 index 0000000..13ec8ac --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h745xg.s @@ -0,0 +1,764 @@ +/**
+ ******************************************************************************
+ * @file startup_stm32h745xx.s
+ * @author MCD Application Team
+ * @brief STM32H745xx Devices vector table for GCC based toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m7
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+ /* External Interrupts */
+ .word WWDG_IRQHandler /* Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */
+ .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
+ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_IRQHandler /* EXTI Line0 */
+ .word EXTI1_IRQHandler /* EXTI Line1 */
+ .word EXTI2_IRQHandler /* EXTI Line2 */
+ .word EXTI3_IRQHandler /* EXTI Line3 */
+ .word EXTI4_IRQHandler /* EXTI Line4 */
+ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
+ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
+ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
+ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
+ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
+ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
+ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
+ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
+ .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
+ .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
+ .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
+ .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
+ .word EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
+ .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
+ .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM4_IRQHandler /* TIM4 */
+ .word I2C1_EV_IRQHandler /* I2C1 Event */
+ .word I2C1_ER_IRQHandler /* I2C1 Error */
+ .word I2C2_EV_IRQHandler /* I2C2 Event */
+ .word I2C2_ER_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
+ .word 0 /* Reserved */
+ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
+ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
+ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
+ .word FMC_IRQHandler /* FMC */
+ .word SDMMC1_IRQHandler /* SDMMC1 */
+ .word TIM5_IRQHandler /* TIM5 */
+ .word SPI3_IRQHandler /* SPI3 */
+ .word UART4_IRQHandler /* UART4 */
+ .word UART5_IRQHandler /* UART5 */
+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
+ .word TIM7_IRQHandler /* TIM7 */
+ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
+ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
+ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
+ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
+ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
+ .word ETH_IRQHandler /* Ethernet */
+ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
+ .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt */
+ .word CM7_SEV_IRQHandler /* CM7 Send event interrupt for CM4 */
+ .word CM4_SEV_IRQHandler /* CM4 Send event interrupt for CM7 */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
+ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
+ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
+ .word USART6_IRQHandler /* USART6 */
+ .word I2C3_EV_IRQHandler /* I2C3 event */
+ .word I2C3_ER_IRQHandler /* I2C3 error */
+ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
+ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
+ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
+ .word OTG_HS_IRQHandler /* USB OTG HS */
+ .word DCMI_IRQHandler /* DCMI */
+ .word 0 /* Reserved */
+ .word RNG_IRQHandler /* Rng */
+ .word FPU_IRQHandler /* FPU */
+ .word UART7_IRQHandler /* UART7 */
+ .word UART8_IRQHandler /* UART8 */
+ .word SPI4_IRQHandler /* SPI4 */
+ .word SPI5_IRQHandler /* SPI5 */
+ .word SPI6_IRQHandler /* SPI6 */
+ .word SAI1_IRQHandler /* SAI1 */
+ .word LTDC_IRQHandler /* LTDC */
+ .word LTDC_ER_IRQHandler /* LTDC error */
+ .word DMA2D_IRQHandler /* DMA2D */
+ .word SAI2_IRQHandler /* SAI2 */
+ .word QUADSPI_IRQHandler /* QUADSPI */
+ .word LPTIM1_IRQHandler /* LPTIM1 */
+ .word CEC_IRQHandler /* HDMI_CEC */
+ .word I2C4_EV_IRQHandler /* I2C4 Event */
+ .word I2C4_ER_IRQHandler /* I2C4 Error */
+ .word SPDIF_RX_IRQHandler /* SPDIF_RX */
+ .word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */
+ .word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */
+ .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */
+ .word OTG_FS_IRQHandler /* USB OTG FS */
+ .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
+ .word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */
+ .word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */
+ .word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */
+ .word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */
+ .word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */
+ .word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */
+ .word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */
+ .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
+ .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
+ .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
+ .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
+ .word SAI3_IRQHandler /* SAI3 global Interrupt */
+ .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
+ .word TIM15_IRQHandler /* TIM15 global Interrupt */
+ .word TIM16_IRQHandler /* TIM16 global Interrupt */
+ .word TIM17_IRQHandler /* TIM17 global Interrupt */
+ .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
+ .word MDIOS_IRQHandler /* MDIOS global Interrupt */
+ .word JPEG_IRQHandler /* JPEG global Interrupt */
+ .word MDMA_IRQHandler /* MDMA global Interrupt */
+ .word 0 /* Reserved */
+ .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
+ .word HSEM1_IRQHandler /* HSEM1 global Interrupt */
+ .word HSEM2_IRQHandler /* HSEM1 global Interrupt */
+ .word ADC3_IRQHandler /* ADC3 global Interrupt */
+ .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
+ .word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
+ .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
+ .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
+ .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
+ .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
+ .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
+ .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
+ .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
+ .word COMP1_IRQHandler /* COMP1 global Interrupt */
+ .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
+ .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
+ .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
+ .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
+ .word LPUART1_IRQHandler /* LP UART1 interrupt */
+ .word WWDG_RST_IRQHandler /* Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) */
+ .word CRS_IRQHandler /* Clock Recovery Global Interrupt */
+ .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
+ .word SAI4_IRQHandler /* SAI4 global interrupt */
+ .word 0 /* Reserved */
+ .word HOLD_CORE_IRQHandler /* Hold core interrupt */
+ .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_AVD_IRQHandler
+ .thumb_set PVD_AVD_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream0_IRQHandler
+ .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream1_IRQHandler
+ .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream2_IRQHandler
+ .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream3_IRQHandler
+ .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream4_IRQHandler
+ .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream5_IRQHandler
+ .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream6_IRQHandler
+ .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT0_IRQHandler
+ .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT0_IRQHandler
+ .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT1_IRQHandler
+ .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT1_IRQHandler
+ .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_TIM12_IRQHandler
+ .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_TIM13_IRQHandler
+ .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_TIM14_IRQHandler
+ .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream7_IRQHandler
+ .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+ .weak FMC_IRQHandler
+ .thumb_set FMC_IRQHandler,Default_Handler
+
+ .weak SDMMC1_IRQHandler
+ .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream0_IRQHandler
+ .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream1_IRQHandler
+ .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream2_IRQHandler
+ .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream3_IRQHandler
+ .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream4_IRQHandler
+ .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+ .weak ETH_IRQHandler
+ .thumb_set ETH_IRQHandler,Default_Handler
+
+ .weak ETH_WKUP_IRQHandler
+ .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+ .weak FDCAN_CAL_IRQHandler
+ .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+
+ .weak CM7_SEV_IRQHandler
+ .thumb_set CM7_SEV_IRQHandler,Default_Handler
+
+ .weak CM4_SEV_IRQHandler
+ .thumb_set CM4_SEV_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream5_IRQHandler
+ .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream6_IRQHandler
+ .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream7_IRQHandler
+ .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+ .weak USART6_IRQHandler
+ .thumb_set USART6_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_OUT_IRQHandler
+ .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_IN_IRQHandler
+ .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_HS_WKUP_IRQHandler
+ .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_HS_IRQHandler
+ .thumb_set OTG_HS_IRQHandler,Default_Handler
+
+ .weak DCMI_IRQHandler
+ .thumb_set DCMI_IRQHandler,Default_Handler
+
+ .weak RNG_IRQHandler
+ .thumb_set RNG_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak UART7_IRQHandler
+ .thumb_set UART7_IRQHandler,Default_Handler
+
+ .weak UART8_IRQHandler
+ .thumb_set UART8_IRQHandler,Default_Handler
+
+ .weak SPI4_IRQHandler
+ .thumb_set SPI4_IRQHandler,Default_Handler
+
+ .weak SPI5_IRQHandler
+ .thumb_set SPI5_IRQHandler,Default_Handler
+
+ .weak SPI6_IRQHandler
+ .thumb_set SPI6_IRQHandler,Default_Handler
+
+ .weak SAI1_IRQHandler
+ .thumb_set SAI1_IRQHandler,Default_Handler
+
+ .weak LTDC_IRQHandler
+ .thumb_set LTDC_IRQHandler,Default_Handler
+
+ .weak LTDC_ER_IRQHandler
+ .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+ .weak DMA2D_IRQHandler
+ .thumb_set DMA2D_IRQHandler,Default_Handler
+
+ .weak SAI2_IRQHandler
+ .thumb_set SAI2_IRQHandler,Default_Handler
+
+ .weak QUADSPI_IRQHandler
+ .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak I2C4_EV_IRQHandler
+ .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+ .weak I2C4_ER_IRQHandler
+ .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+ .weak SPDIF_RX_IRQHandler
+ .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+ .weak OTG_FS_EP1_OUT_IRQHandler
+ .thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_FS_EP1_IN_IRQHandler
+ .thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_FS_WKUP_IRQHandler
+ .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_FS_IRQHandler
+ .thumb_set OTG_FS_IRQHandler,Default_Handler
+
+ .weak DMAMUX1_OVR_IRQHandler
+ .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+ .weak HRTIM1_Master_IRQHandler
+ .thumb_set HRTIM1_Master_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMA_IRQHandler
+ .thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMB_IRQHandler
+ .thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMC_IRQHandler
+ .thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMD_IRQHandler
+ .thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIME_IRQHandler
+ .thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
+
+ .weak HRTIM1_FLT_IRQHandler
+ .thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT0_IRQHandler
+ .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT1_IRQHandler
+ .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT2_IRQHandler
+ .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT3_IRQHandler
+ .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+ .weak SAI3_IRQHandler
+ .thumb_set SAI3_IRQHandler,Default_Handler
+
+ .weak SWPMI1_IRQHandler
+ .thumb_set SWPMI1_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak MDIOS_WKUP_IRQHandler
+ .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
+
+ .weak MDIOS_IRQHandler
+ .thumb_set MDIOS_IRQHandler,Default_Handler
+
+ .weak JPEG_IRQHandler
+ .thumb_set JPEG_IRQHandler,Default_Handler
+
+ .weak MDMA_IRQHandler
+ .thumb_set MDMA_IRQHandler,Default_Handler
+
+ .weak SDMMC2_IRQHandler
+ .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+ .weak HSEM1_IRQHandler
+ .thumb_set HSEM1_IRQHandler,Default_Handler
+
+ .weak HSEM2_IRQHandler
+ .thumb_set HSEM2_IRQHandler,Default_Handler
+
+ .weak ADC3_IRQHandler
+ .thumb_set ADC3_IRQHandler,Default_Handler
+
+ .weak DMAMUX2_OVR_IRQHandler
+ .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel0_IRQHandler
+ .thumb_set BDMA_Channel0_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel1_IRQHandler
+ .thumb_set BDMA_Channel1_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel2_IRQHandler
+ .thumb_set BDMA_Channel2_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel3_IRQHandler
+ .thumb_set BDMA_Channel3_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel4_IRQHandler
+ .thumb_set BDMA_Channel4_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel5_IRQHandler
+ .thumb_set BDMA_Channel5_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel6_IRQHandler
+ .thumb_set BDMA_Channel6_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel7_IRQHandler
+ .thumb_set BDMA_Channel7_IRQHandler,Default_Handler
+
+ .weak COMP1_IRQHandler
+ .thumb_set COMP1_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak LPTIM4_IRQHandler
+ .thumb_set LPTIM4_IRQHandler,Default_Handler
+
+ .weak LPTIM5_IRQHandler
+ .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak WWDG_RST_IRQHandler
+ .thumb_set WWDG_RST_IRQHandler,Default_Handler
+
+ .weak CRS_IRQHandler
+ .thumb_set CRS_IRQHandler,Default_Handler
+
+ .weak ECC_IRQHandler
+ .thumb_set ECC_IRQHandler,Default_Handler
+
+ .weak SAI4_IRQHandler
+ .thumb_set SAI4_IRQHandler,Default_Handler
+
+ .weak HOLD_CORE_IRQHandler
+ .thumb_set HOLD_CORE_IRQHandler,Default_Handler
+
+ .weak WAKEUP_PIN_IRQHandler
+ .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h745xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h745xx.s new file mode 100644 index 0000000..13ec8ac --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h745xx.s @@ -0,0 +1,764 @@ +/**
+ ******************************************************************************
+ * @file startup_stm32h745xx.s
+ * @author MCD Application Team
+ * @brief STM32H745xx Devices vector table for GCC based toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m7
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+ /* External Interrupts */
+ .word WWDG_IRQHandler /* Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */
+ .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
+ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_IRQHandler /* EXTI Line0 */
+ .word EXTI1_IRQHandler /* EXTI Line1 */
+ .word EXTI2_IRQHandler /* EXTI Line2 */
+ .word EXTI3_IRQHandler /* EXTI Line3 */
+ .word EXTI4_IRQHandler /* EXTI Line4 */
+ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
+ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
+ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
+ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
+ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
+ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
+ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
+ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
+ .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
+ .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
+ .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
+ .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
+ .word EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
+ .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
+ .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM4_IRQHandler /* TIM4 */
+ .word I2C1_EV_IRQHandler /* I2C1 Event */
+ .word I2C1_ER_IRQHandler /* I2C1 Error */
+ .word I2C2_EV_IRQHandler /* I2C2 Event */
+ .word I2C2_ER_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
+ .word 0 /* Reserved */
+ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
+ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
+ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
+ .word FMC_IRQHandler /* FMC */
+ .word SDMMC1_IRQHandler /* SDMMC1 */
+ .word TIM5_IRQHandler /* TIM5 */
+ .word SPI3_IRQHandler /* SPI3 */
+ .word UART4_IRQHandler /* UART4 */
+ .word UART5_IRQHandler /* UART5 */
+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
+ .word TIM7_IRQHandler /* TIM7 */
+ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
+ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
+ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
+ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
+ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
+ .word ETH_IRQHandler /* Ethernet */
+ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
+ .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt */
+ .word CM7_SEV_IRQHandler /* CM7 Send event interrupt for CM4 */
+ .word CM4_SEV_IRQHandler /* CM4 Send event interrupt for CM7 */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
+ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
+ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
+ .word USART6_IRQHandler /* USART6 */
+ .word I2C3_EV_IRQHandler /* I2C3 event */
+ .word I2C3_ER_IRQHandler /* I2C3 error */
+ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
+ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
+ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
+ .word OTG_HS_IRQHandler /* USB OTG HS */
+ .word DCMI_IRQHandler /* DCMI */
+ .word 0 /* Reserved */
+ .word RNG_IRQHandler /* Rng */
+ .word FPU_IRQHandler /* FPU */
+ .word UART7_IRQHandler /* UART7 */
+ .word UART8_IRQHandler /* UART8 */
+ .word SPI4_IRQHandler /* SPI4 */
+ .word SPI5_IRQHandler /* SPI5 */
+ .word SPI6_IRQHandler /* SPI6 */
+ .word SAI1_IRQHandler /* SAI1 */
+ .word LTDC_IRQHandler /* LTDC */
+ .word LTDC_ER_IRQHandler /* LTDC error */
+ .word DMA2D_IRQHandler /* DMA2D */
+ .word SAI2_IRQHandler /* SAI2 */
+ .word QUADSPI_IRQHandler /* QUADSPI */
+ .word LPTIM1_IRQHandler /* LPTIM1 */
+ .word CEC_IRQHandler /* HDMI_CEC */
+ .word I2C4_EV_IRQHandler /* I2C4 Event */
+ .word I2C4_ER_IRQHandler /* I2C4 Error */
+ .word SPDIF_RX_IRQHandler /* SPDIF_RX */
+ .word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */
+ .word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */
+ .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */
+ .word OTG_FS_IRQHandler /* USB OTG FS */
+ .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
+ .word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */
+ .word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */
+ .word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */
+ .word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */
+ .word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */
+ .word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */
+ .word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */
+ .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
+ .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
+ .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
+ .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
+ .word SAI3_IRQHandler /* SAI3 global Interrupt */
+ .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
+ .word TIM15_IRQHandler /* TIM15 global Interrupt */
+ .word TIM16_IRQHandler /* TIM16 global Interrupt */
+ .word TIM17_IRQHandler /* TIM17 global Interrupt */
+ .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
+ .word MDIOS_IRQHandler /* MDIOS global Interrupt */
+ .word JPEG_IRQHandler /* JPEG global Interrupt */
+ .word MDMA_IRQHandler /* MDMA global Interrupt */
+ .word 0 /* Reserved */
+ .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
+ .word HSEM1_IRQHandler /* HSEM1 global Interrupt */
+ .word HSEM2_IRQHandler /* HSEM1 global Interrupt */
+ .word ADC3_IRQHandler /* ADC3 global Interrupt */
+ .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
+ .word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
+ .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
+ .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
+ .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
+ .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
+ .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
+ .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
+ .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
+ .word COMP1_IRQHandler /* COMP1 global Interrupt */
+ .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
+ .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
+ .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
+ .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
+ .word LPUART1_IRQHandler /* LP UART1 interrupt */
+ .word WWDG_RST_IRQHandler /* Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) */
+ .word CRS_IRQHandler /* Clock Recovery Global Interrupt */
+ .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
+ .word SAI4_IRQHandler /* SAI4 global interrupt */
+ .word 0 /* Reserved */
+ .word HOLD_CORE_IRQHandler /* Hold core interrupt */
+ .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_AVD_IRQHandler
+ .thumb_set PVD_AVD_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream0_IRQHandler
+ .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream1_IRQHandler
+ .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream2_IRQHandler
+ .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream3_IRQHandler
+ .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream4_IRQHandler
+ .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream5_IRQHandler
+ .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream6_IRQHandler
+ .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT0_IRQHandler
+ .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT0_IRQHandler
+ .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT1_IRQHandler
+ .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT1_IRQHandler
+ .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_TIM12_IRQHandler
+ .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_TIM13_IRQHandler
+ .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_TIM14_IRQHandler
+ .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream7_IRQHandler
+ .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+ .weak FMC_IRQHandler
+ .thumb_set FMC_IRQHandler,Default_Handler
+
+ .weak SDMMC1_IRQHandler
+ .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream0_IRQHandler
+ .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream1_IRQHandler
+ .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream2_IRQHandler
+ .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream3_IRQHandler
+ .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream4_IRQHandler
+ .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+ .weak ETH_IRQHandler
+ .thumb_set ETH_IRQHandler,Default_Handler
+
+ .weak ETH_WKUP_IRQHandler
+ .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+ .weak FDCAN_CAL_IRQHandler
+ .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+
+ .weak CM7_SEV_IRQHandler
+ .thumb_set CM7_SEV_IRQHandler,Default_Handler
+
+ .weak CM4_SEV_IRQHandler
+ .thumb_set CM4_SEV_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream5_IRQHandler
+ .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream6_IRQHandler
+ .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream7_IRQHandler
+ .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+ .weak USART6_IRQHandler
+ .thumb_set USART6_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_OUT_IRQHandler
+ .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_IN_IRQHandler
+ .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_HS_WKUP_IRQHandler
+ .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_HS_IRQHandler
+ .thumb_set OTG_HS_IRQHandler,Default_Handler
+
+ .weak DCMI_IRQHandler
+ .thumb_set DCMI_IRQHandler,Default_Handler
+
+ .weak RNG_IRQHandler
+ .thumb_set RNG_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak UART7_IRQHandler
+ .thumb_set UART7_IRQHandler,Default_Handler
+
+ .weak UART8_IRQHandler
+ .thumb_set UART8_IRQHandler,Default_Handler
+
+ .weak SPI4_IRQHandler
+ .thumb_set SPI4_IRQHandler,Default_Handler
+
+ .weak SPI5_IRQHandler
+ .thumb_set SPI5_IRQHandler,Default_Handler
+
+ .weak SPI6_IRQHandler
+ .thumb_set SPI6_IRQHandler,Default_Handler
+
+ .weak SAI1_IRQHandler
+ .thumb_set SAI1_IRQHandler,Default_Handler
+
+ .weak LTDC_IRQHandler
+ .thumb_set LTDC_IRQHandler,Default_Handler
+
+ .weak LTDC_ER_IRQHandler
+ .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+ .weak DMA2D_IRQHandler
+ .thumb_set DMA2D_IRQHandler,Default_Handler
+
+ .weak SAI2_IRQHandler
+ .thumb_set SAI2_IRQHandler,Default_Handler
+
+ .weak QUADSPI_IRQHandler
+ .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak I2C4_EV_IRQHandler
+ .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+ .weak I2C4_ER_IRQHandler
+ .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+ .weak SPDIF_RX_IRQHandler
+ .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+ .weak OTG_FS_EP1_OUT_IRQHandler
+ .thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_FS_EP1_IN_IRQHandler
+ .thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_FS_WKUP_IRQHandler
+ .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_FS_IRQHandler
+ .thumb_set OTG_FS_IRQHandler,Default_Handler
+
+ .weak DMAMUX1_OVR_IRQHandler
+ .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+ .weak HRTIM1_Master_IRQHandler
+ .thumb_set HRTIM1_Master_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMA_IRQHandler
+ .thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMB_IRQHandler
+ .thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMC_IRQHandler
+ .thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMD_IRQHandler
+ .thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIME_IRQHandler
+ .thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
+
+ .weak HRTIM1_FLT_IRQHandler
+ .thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT0_IRQHandler
+ .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT1_IRQHandler
+ .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT2_IRQHandler
+ .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT3_IRQHandler
+ .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+ .weak SAI3_IRQHandler
+ .thumb_set SAI3_IRQHandler,Default_Handler
+
+ .weak SWPMI1_IRQHandler
+ .thumb_set SWPMI1_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak MDIOS_WKUP_IRQHandler
+ .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
+
+ .weak MDIOS_IRQHandler
+ .thumb_set MDIOS_IRQHandler,Default_Handler
+
+ .weak JPEG_IRQHandler
+ .thumb_set JPEG_IRQHandler,Default_Handler
+
+ .weak MDMA_IRQHandler
+ .thumb_set MDMA_IRQHandler,Default_Handler
+
+ .weak SDMMC2_IRQHandler
+ .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+ .weak HSEM1_IRQHandler
+ .thumb_set HSEM1_IRQHandler,Default_Handler
+
+ .weak HSEM2_IRQHandler
+ .thumb_set HSEM2_IRQHandler,Default_Handler
+
+ .weak ADC3_IRQHandler
+ .thumb_set ADC3_IRQHandler,Default_Handler
+
+ .weak DMAMUX2_OVR_IRQHandler
+ .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel0_IRQHandler
+ .thumb_set BDMA_Channel0_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel1_IRQHandler
+ .thumb_set BDMA_Channel1_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel2_IRQHandler
+ .thumb_set BDMA_Channel2_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel3_IRQHandler
+ .thumb_set BDMA_Channel3_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel4_IRQHandler
+ .thumb_set BDMA_Channel4_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel5_IRQHandler
+ .thumb_set BDMA_Channel5_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel6_IRQHandler
+ .thumb_set BDMA_Channel6_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel7_IRQHandler
+ .thumb_set BDMA_Channel7_IRQHandler,Default_Handler
+
+ .weak COMP1_IRQHandler
+ .thumb_set COMP1_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak LPTIM4_IRQHandler
+ .thumb_set LPTIM4_IRQHandler,Default_Handler
+
+ .weak LPTIM5_IRQHandler
+ .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak WWDG_RST_IRQHandler
+ .thumb_set WWDG_RST_IRQHandler,Default_Handler
+
+ .weak CRS_IRQHandler
+ .thumb_set CRS_IRQHandler,Default_Handler
+
+ .weak ECC_IRQHandler
+ .thumb_set ECC_IRQHandler,Default_Handler
+
+ .weak SAI4_IRQHandler
+ .thumb_set SAI4_IRQHandler,Default_Handler
+
+ .weak HOLD_CORE_IRQHandler
+ .thumb_set HOLD_CORE_IRQHandler,Default_Handler
+
+ .weak WAKEUP_PIN_IRQHandler
+ .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h747xg.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h747xg.s new file mode 100644 index 0000000..b2fed1e --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h747xg.s @@ -0,0 +1,767 @@ +/**
+ ******************************************************************************
+ * @file startup_stm32h747xg.s
+ * @author MCD Application Team
+ * @brief STM32H747xg Devices vector table for GCC based toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m7
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+ /* External Interrupts */
+ .word WWDG_IRQHandler /* Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */
+ .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
+ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_IRQHandler /* EXTI Line0 */
+ .word EXTI1_IRQHandler /* EXTI Line1 */
+ .word EXTI2_IRQHandler /* EXTI Line2 */
+ .word EXTI3_IRQHandler /* EXTI Line3 */
+ .word EXTI4_IRQHandler /* EXTI Line4 */
+ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
+ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
+ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
+ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
+ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
+ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
+ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
+ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
+ .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
+ .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
+ .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
+ .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
+ .word EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
+ .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
+ .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM4_IRQHandler /* TIM4 */
+ .word I2C1_EV_IRQHandler /* I2C1 Event */
+ .word I2C1_ER_IRQHandler /* I2C1 Error */
+ .word I2C2_EV_IRQHandler /* I2C2 Event */
+ .word I2C2_ER_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
+ .word 0 /* Reserved */
+ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
+ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
+ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
+ .word FMC_IRQHandler /* FMC */
+ .word SDMMC1_IRQHandler /* SDMMC1 */
+ .word TIM5_IRQHandler /* TIM5 */
+ .word SPI3_IRQHandler /* SPI3 */
+ .word UART4_IRQHandler /* UART4 */
+ .word UART5_IRQHandler /* UART5 */
+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
+ .word TIM7_IRQHandler /* TIM7 */
+ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
+ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
+ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
+ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
+ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
+ .word ETH_IRQHandler /* Ethernet */
+ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
+ .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt */
+ .word CM7_SEV_IRQHandler /* CM7 Send event interrupt for CM4 */
+ .word CM4_SEV_IRQHandler /* CM4 Send event interrupt for CM7 */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
+ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
+ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
+ .word USART6_IRQHandler /* USART6 */
+ .word I2C3_EV_IRQHandler /* I2C3 event */
+ .word I2C3_ER_IRQHandler /* I2C3 error */
+ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
+ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
+ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
+ .word OTG_HS_IRQHandler /* USB OTG HS */
+ .word DCMI_IRQHandler /* DCMI */
+ .word 0 /* Reserved */
+ .word RNG_IRQHandler /* Rng */
+ .word FPU_IRQHandler /* FPU */
+ .word UART7_IRQHandler /* UART7 */
+ .word UART8_IRQHandler /* UART8 */
+ .word SPI4_IRQHandler /* SPI4 */
+ .word SPI5_IRQHandler /* SPI5 */
+ .word SPI6_IRQHandler /* SPI6 */
+ .word SAI1_IRQHandler /* SAI1 */
+ .word LTDC_IRQHandler /* LTDC */
+ .word LTDC_ER_IRQHandler /* LTDC error */
+ .word DMA2D_IRQHandler /* DMA2D */
+ .word SAI2_IRQHandler /* SAI2 */
+ .word QUADSPI_IRQHandler /* QUADSPI */
+ .word LPTIM1_IRQHandler /* LPTIM1 */
+ .word CEC_IRQHandler /* HDMI_CEC */
+ .word I2C4_EV_IRQHandler /* I2C4 Event */
+ .word I2C4_ER_IRQHandler /* I2C4 Error */
+ .word SPDIF_RX_IRQHandler /* SPDIF_RX */
+ .word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */
+ .word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */
+ .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */
+ .word OTG_FS_IRQHandler /* USB OTG FS */
+ .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
+ .word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */
+ .word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */
+ .word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */
+ .word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */
+ .word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */
+ .word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */
+ .word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */
+ .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
+ .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
+ .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
+ .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
+ .word SAI3_IRQHandler /* SAI3 global Interrupt */
+ .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
+ .word TIM15_IRQHandler /* TIM15 global Interrupt */
+ .word TIM16_IRQHandler /* TIM16 global Interrupt */
+ .word TIM17_IRQHandler /* TIM17 global Interrupt */
+ .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
+ .word MDIOS_IRQHandler /* MDIOS global Interrupt */
+ .word JPEG_IRQHandler /* JPEG global Interrupt */
+ .word MDMA_IRQHandler /* MDMA global Interrupt */
+ .word DSI_IRQHandler /* DSI global Interrupt */
+ .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
+ .word HSEM1_IRQHandler /* HSEM1 global Interrupt */
+ .word HSEM2_IRQHandler /* HSEM1 global Interrupt */
+ .word ADC3_IRQHandler /* ADC3 global Interrupt */
+ .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
+ .word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
+ .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
+ .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
+ .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
+ .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
+ .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
+ .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
+ .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
+ .word COMP1_IRQHandler /* COMP1 global Interrupt */
+ .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
+ .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
+ .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
+ .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
+ .word LPUART1_IRQHandler /* LP UART1 interrupt */
+ .word WWDG_RST_IRQHandler /* Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) */
+ .word CRS_IRQHandler /* Clock Recovery Global Interrupt */
+ .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
+ .word SAI4_IRQHandler /* SAI4 global interrupt */
+ .word 0 /* Reserved */
+ .word HOLD_CORE_IRQHandler /* Hold core interrupt */
+ .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_AVD_IRQHandler
+ .thumb_set PVD_AVD_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream0_IRQHandler
+ .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream1_IRQHandler
+ .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream2_IRQHandler
+ .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream3_IRQHandler
+ .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream4_IRQHandler
+ .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream5_IRQHandler
+ .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream6_IRQHandler
+ .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT0_IRQHandler
+ .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT0_IRQHandler
+ .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT1_IRQHandler
+ .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT1_IRQHandler
+ .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_TIM12_IRQHandler
+ .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_TIM13_IRQHandler
+ .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_TIM14_IRQHandler
+ .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream7_IRQHandler
+ .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+ .weak FMC_IRQHandler
+ .thumb_set FMC_IRQHandler,Default_Handler
+
+ .weak SDMMC1_IRQHandler
+ .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream0_IRQHandler
+ .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream1_IRQHandler
+ .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream2_IRQHandler
+ .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream3_IRQHandler
+ .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream4_IRQHandler
+ .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+ .weak ETH_IRQHandler
+ .thumb_set ETH_IRQHandler,Default_Handler
+
+ .weak ETH_WKUP_IRQHandler
+ .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+ .weak FDCAN_CAL_IRQHandler
+ .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+
+ .weak CM7_SEV_IRQHandler
+ .thumb_set CM7_SEV_IRQHandler,Default_Handler
+
+ .weak CM4_SEV_IRQHandler
+ .thumb_set CM4_SEV_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream5_IRQHandler
+ .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream6_IRQHandler
+ .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream7_IRQHandler
+ .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+ .weak USART6_IRQHandler
+ .thumb_set USART6_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_OUT_IRQHandler
+ .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_IN_IRQHandler
+ .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_HS_WKUP_IRQHandler
+ .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_HS_IRQHandler
+ .thumb_set OTG_HS_IRQHandler,Default_Handler
+
+ .weak DCMI_IRQHandler
+ .thumb_set DCMI_IRQHandler,Default_Handler
+
+ .weak RNG_IRQHandler
+ .thumb_set RNG_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak UART7_IRQHandler
+ .thumb_set UART7_IRQHandler,Default_Handler
+
+ .weak UART8_IRQHandler
+ .thumb_set UART8_IRQHandler,Default_Handler
+
+ .weak SPI4_IRQHandler
+ .thumb_set SPI4_IRQHandler,Default_Handler
+
+ .weak SPI5_IRQHandler
+ .thumb_set SPI5_IRQHandler,Default_Handler
+
+ .weak SPI6_IRQHandler
+ .thumb_set SPI6_IRQHandler,Default_Handler
+
+ .weak SAI1_IRQHandler
+ .thumb_set SAI1_IRQHandler,Default_Handler
+
+ .weak LTDC_IRQHandler
+ .thumb_set LTDC_IRQHandler,Default_Handler
+
+ .weak LTDC_ER_IRQHandler
+ .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+ .weak DMA2D_IRQHandler
+ .thumb_set DMA2D_IRQHandler,Default_Handler
+
+ .weak SAI2_IRQHandler
+ .thumb_set SAI2_IRQHandler,Default_Handler
+
+ .weak QUADSPI_IRQHandler
+ .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak I2C4_EV_IRQHandler
+ .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+ .weak I2C4_ER_IRQHandler
+ .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+ .weak SPDIF_RX_IRQHandler
+ .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+ .weak OTG_FS_EP1_OUT_IRQHandler
+ .thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_FS_EP1_IN_IRQHandler
+ .thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_FS_WKUP_IRQHandler
+ .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_FS_IRQHandler
+ .thumb_set OTG_FS_IRQHandler,Default_Handler
+
+ .weak DMAMUX1_OVR_IRQHandler
+ .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+ .weak HRTIM1_Master_IRQHandler
+ .thumb_set HRTIM1_Master_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMA_IRQHandler
+ .thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMB_IRQHandler
+ .thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMC_IRQHandler
+ .thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMD_IRQHandler
+ .thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIME_IRQHandler
+ .thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
+
+ .weak HRTIM1_FLT_IRQHandler
+ .thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT0_IRQHandler
+ .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT1_IRQHandler
+ .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT2_IRQHandler
+ .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT3_IRQHandler
+ .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+ .weak SAI3_IRQHandler
+ .thumb_set SAI3_IRQHandler,Default_Handler
+
+ .weak SWPMI1_IRQHandler
+ .thumb_set SWPMI1_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak MDIOS_WKUP_IRQHandler
+ .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
+
+ .weak MDIOS_IRQHandler
+ .thumb_set MDIOS_IRQHandler,Default_Handler
+
+ .weak JPEG_IRQHandler
+ .thumb_set JPEG_IRQHandler,Default_Handler
+
+ .weak MDMA_IRQHandler
+ .thumb_set MDMA_IRQHandler,Default_Handler
+
+ .weak DSI_IRQHandler
+ .thumb_set DSI_IRQHandler,Default_Handler
+
+ .weak SDMMC2_IRQHandler
+ .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+ .weak HSEM1_IRQHandler
+ .thumb_set HSEM1_IRQHandler,Default_Handler
+
+ .weak HSEM2_IRQHandler
+ .thumb_set HSEM2_IRQHandler,Default_Handler
+
+ .weak ADC3_IRQHandler
+ .thumb_set ADC3_IRQHandler,Default_Handler
+
+ .weak DMAMUX2_OVR_IRQHandler
+ .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel0_IRQHandler
+ .thumb_set BDMA_Channel0_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel1_IRQHandler
+ .thumb_set BDMA_Channel1_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel2_IRQHandler
+ .thumb_set BDMA_Channel2_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel3_IRQHandler
+ .thumb_set BDMA_Channel3_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel4_IRQHandler
+ .thumb_set BDMA_Channel4_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel5_IRQHandler
+ .thumb_set BDMA_Channel5_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel6_IRQHandler
+ .thumb_set BDMA_Channel6_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel7_IRQHandler
+ .thumb_set BDMA_Channel7_IRQHandler,Default_Handler
+
+ .weak COMP1_IRQHandler
+ .thumb_set COMP1_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak LPTIM4_IRQHandler
+ .thumb_set LPTIM4_IRQHandler,Default_Handler
+
+ .weak LPTIM5_IRQHandler
+ .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak WWDG_RST_IRQHandler
+ .thumb_set WWDG_RST_IRQHandler,Default_Handler
+
+ .weak CRS_IRQHandler
+ .thumb_set CRS_IRQHandler,Default_Handler
+
+ .weak ECC_IRQHandler
+ .thumb_set ECC_IRQHandler,Default_Handler
+
+ .weak SAI4_IRQHandler
+ .thumb_set SAI4_IRQHandler,Default_Handler
+
+ .weak HOLD_CORE_IRQHandler
+ .thumb_set HOLD_CORE_IRQHandler,Default_Handler
+
+ .weak WAKEUP_PIN_IRQHandler
+ .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h747xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h747xx.s new file mode 100644 index 0000000..473f40f --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h747xx.s @@ -0,0 +1,767 @@ +/**
+ ******************************************************************************
+ * @file startup_stm32h747xx.s
+ * @author MCD Application Team
+ * @brief STM32H747xx Devices vector table for GCC based toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m7
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+ /* External Interrupts */
+ .word WWDG_IRQHandler /* Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */
+ .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
+ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_IRQHandler /* EXTI Line0 */
+ .word EXTI1_IRQHandler /* EXTI Line1 */
+ .word EXTI2_IRQHandler /* EXTI Line2 */
+ .word EXTI3_IRQHandler /* EXTI Line3 */
+ .word EXTI4_IRQHandler /* EXTI Line4 */
+ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
+ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
+ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
+ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
+ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
+ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
+ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
+ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
+ .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
+ .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
+ .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
+ .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
+ .word EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
+ .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
+ .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM4_IRQHandler /* TIM4 */
+ .word I2C1_EV_IRQHandler /* I2C1 Event */
+ .word I2C1_ER_IRQHandler /* I2C1 Error */
+ .word I2C2_EV_IRQHandler /* I2C2 Event */
+ .word I2C2_ER_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
+ .word 0 /* Reserved */
+ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
+ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
+ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
+ .word FMC_IRQHandler /* FMC */
+ .word SDMMC1_IRQHandler /* SDMMC1 */
+ .word TIM5_IRQHandler /* TIM5 */
+ .word SPI3_IRQHandler /* SPI3 */
+ .word UART4_IRQHandler /* UART4 */
+ .word UART5_IRQHandler /* UART5 */
+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
+ .word TIM7_IRQHandler /* TIM7 */
+ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
+ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
+ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
+ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
+ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
+ .word ETH_IRQHandler /* Ethernet */
+ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
+ .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt */
+ .word CM7_SEV_IRQHandler /* CM7 Send event interrupt for CM4 */
+ .word CM4_SEV_IRQHandler /* CM4 Send event interrupt for CM7 */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
+ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
+ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
+ .word USART6_IRQHandler /* USART6 */
+ .word I2C3_EV_IRQHandler /* I2C3 event */
+ .word I2C3_ER_IRQHandler /* I2C3 error */
+ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
+ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
+ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
+ .word OTG_HS_IRQHandler /* USB OTG HS */
+ .word DCMI_IRQHandler /* DCMI */
+ .word 0 /* Reserved */
+ .word RNG_IRQHandler /* Rng */
+ .word FPU_IRQHandler /* FPU */
+ .word UART7_IRQHandler /* UART7 */
+ .word UART8_IRQHandler /* UART8 */
+ .word SPI4_IRQHandler /* SPI4 */
+ .word SPI5_IRQHandler /* SPI5 */
+ .word SPI6_IRQHandler /* SPI6 */
+ .word SAI1_IRQHandler /* SAI1 */
+ .word LTDC_IRQHandler /* LTDC */
+ .word LTDC_ER_IRQHandler /* LTDC error */
+ .word DMA2D_IRQHandler /* DMA2D */
+ .word SAI2_IRQHandler /* SAI2 */
+ .word QUADSPI_IRQHandler /* QUADSPI */
+ .word LPTIM1_IRQHandler /* LPTIM1 */
+ .word CEC_IRQHandler /* HDMI_CEC */
+ .word I2C4_EV_IRQHandler /* I2C4 Event */
+ .word I2C4_ER_IRQHandler /* I2C4 Error */
+ .word SPDIF_RX_IRQHandler /* SPDIF_RX */
+ .word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */
+ .word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */
+ .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */
+ .word OTG_FS_IRQHandler /* USB OTG FS */
+ .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
+ .word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */
+ .word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */
+ .word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */
+ .word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */
+ .word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */
+ .word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */
+ .word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */
+ .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
+ .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
+ .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
+ .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
+ .word SAI3_IRQHandler /* SAI3 global Interrupt */
+ .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
+ .word TIM15_IRQHandler /* TIM15 global Interrupt */
+ .word TIM16_IRQHandler /* TIM16 global Interrupt */
+ .word TIM17_IRQHandler /* TIM17 global Interrupt */
+ .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
+ .word MDIOS_IRQHandler /* MDIOS global Interrupt */
+ .word JPEG_IRQHandler /* JPEG global Interrupt */
+ .word MDMA_IRQHandler /* MDMA global Interrupt */
+ .word DSI_IRQHandler /* DSI global Interrupt */
+ .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
+ .word HSEM1_IRQHandler /* HSEM1 global Interrupt */
+ .word HSEM2_IRQHandler /* HSEM1 global Interrupt */
+ .word ADC3_IRQHandler /* ADC3 global Interrupt */
+ .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
+ .word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
+ .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
+ .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
+ .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
+ .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
+ .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
+ .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
+ .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
+ .word COMP1_IRQHandler /* COMP1 global Interrupt */
+ .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
+ .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
+ .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
+ .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
+ .word LPUART1_IRQHandler /* LP UART1 interrupt */
+ .word WWDG_RST_IRQHandler /* Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) */
+ .word CRS_IRQHandler /* Clock Recovery Global Interrupt */
+ .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
+ .word SAI4_IRQHandler /* SAI4 global interrupt */
+ .word 0 /* Reserved */
+ .word HOLD_CORE_IRQHandler /* Hold core interrupt */
+ .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_AVD_IRQHandler
+ .thumb_set PVD_AVD_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream0_IRQHandler
+ .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream1_IRQHandler
+ .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream2_IRQHandler
+ .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream3_IRQHandler
+ .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream4_IRQHandler
+ .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream5_IRQHandler
+ .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream6_IRQHandler
+ .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT0_IRQHandler
+ .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT0_IRQHandler
+ .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT1_IRQHandler
+ .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT1_IRQHandler
+ .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_TIM12_IRQHandler
+ .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_TIM13_IRQHandler
+ .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_TIM14_IRQHandler
+ .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream7_IRQHandler
+ .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+ .weak FMC_IRQHandler
+ .thumb_set FMC_IRQHandler,Default_Handler
+
+ .weak SDMMC1_IRQHandler
+ .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream0_IRQHandler
+ .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream1_IRQHandler
+ .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream2_IRQHandler
+ .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream3_IRQHandler
+ .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream4_IRQHandler
+ .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+ .weak ETH_IRQHandler
+ .thumb_set ETH_IRQHandler,Default_Handler
+
+ .weak ETH_WKUP_IRQHandler
+ .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+ .weak FDCAN_CAL_IRQHandler
+ .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+
+ .weak CM7_SEV_IRQHandler
+ .thumb_set CM7_SEV_IRQHandler,Default_Handler
+
+ .weak CM4_SEV_IRQHandler
+ .thumb_set CM4_SEV_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream5_IRQHandler
+ .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream6_IRQHandler
+ .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream7_IRQHandler
+ .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+ .weak USART6_IRQHandler
+ .thumb_set USART6_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_OUT_IRQHandler
+ .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_IN_IRQHandler
+ .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_HS_WKUP_IRQHandler
+ .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_HS_IRQHandler
+ .thumb_set OTG_HS_IRQHandler,Default_Handler
+
+ .weak DCMI_IRQHandler
+ .thumb_set DCMI_IRQHandler,Default_Handler
+
+ .weak RNG_IRQHandler
+ .thumb_set RNG_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak UART7_IRQHandler
+ .thumb_set UART7_IRQHandler,Default_Handler
+
+ .weak UART8_IRQHandler
+ .thumb_set UART8_IRQHandler,Default_Handler
+
+ .weak SPI4_IRQHandler
+ .thumb_set SPI4_IRQHandler,Default_Handler
+
+ .weak SPI5_IRQHandler
+ .thumb_set SPI5_IRQHandler,Default_Handler
+
+ .weak SPI6_IRQHandler
+ .thumb_set SPI6_IRQHandler,Default_Handler
+
+ .weak SAI1_IRQHandler
+ .thumb_set SAI1_IRQHandler,Default_Handler
+
+ .weak LTDC_IRQHandler
+ .thumb_set LTDC_IRQHandler,Default_Handler
+
+ .weak LTDC_ER_IRQHandler
+ .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+ .weak DMA2D_IRQHandler
+ .thumb_set DMA2D_IRQHandler,Default_Handler
+
+ .weak SAI2_IRQHandler
+ .thumb_set SAI2_IRQHandler,Default_Handler
+
+ .weak QUADSPI_IRQHandler
+ .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak I2C4_EV_IRQHandler
+ .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+ .weak I2C4_ER_IRQHandler
+ .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+ .weak SPDIF_RX_IRQHandler
+ .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+ .weak OTG_FS_EP1_OUT_IRQHandler
+ .thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_FS_EP1_IN_IRQHandler
+ .thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_FS_WKUP_IRQHandler
+ .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_FS_IRQHandler
+ .thumb_set OTG_FS_IRQHandler,Default_Handler
+
+ .weak DMAMUX1_OVR_IRQHandler
+ .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+ .weak HRTIM1_Master_IRQHandler
+ .thumb_set HRTIM1_Master_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMA_IRQHandler
+ .thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMB_IRQHandler
+ .thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMC_IRQHandler
+ .thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMD_IRQHandler
+ .thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIME_IRQHandler
+ .thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
+
+ .weak HRTIM1_FLT_IRQHandler
+ .thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT0_IRQHandler
+ .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT1_IRQHandler
+ .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT2_IRQHandler
+ .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT3_IRQHandler
+ .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+ .weak SAI3_IRQHandler
+ .thumb_set SAI3_IRQHandler,Default_Handler
+
+ .weak SWPMI1_IRQHandler
+ .thumb_set SWPMI1_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak MDIOS_WKUP_IRQHandler
+ .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
+
+ .weak MDIOS_IRQHandler
+ .thumb_set MDIOS_IRQHandler,Default_Handler
+
+ .weak JPEG_IRQHandler
+ .thumb_set JPEG_IRQHandler,Default_Handler
+
+ .weak MDMA_IRQHandler
+ .thumb_set MDMA_IRQHandler,Default_Handler
+
+ .weak DSI_IRQHandler
+ .thumb_set DSI_IRQHandler,Default_Handler
+
+ .weak SDMMC2_IRQHandler
+ .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+ .weak HSEM1_IRQHandler
+ .thumb_set HSEM1_IRQHandler,Default_Handler
+
+ .weak HSEM2_IRQHandler
+ .thumb_set HSEM2_IRQHandler,Default_Handler
+
+ .weak ADC3_IRQHandler
+ .thumb_set ADC3_IRQHandler,Default_Handler
+
+ .weak DMAMUX2_OVR_IRQHandler
+ .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel0_IRQHandler
+ .thumb_set BDMA_Channel0_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel1_IRQHandler
+ .thumb_set BDMA_Channel1_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel2_IRQHandler
+ .thumb_set BDMA_Channel2_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel3_IRQHandler
+ .thumb_set BDMA_Channel3_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel4_IRQHandler
+ .thumb_set BDMA_Channel4_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel5_IRQHandler
+ .thumb_set BDMA_Channel5_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel6_IRQHandler
+ .thumb_set BDMA_Channel6_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel7_IRQHandler
+ .thumb_set BDMA_Channel7_IRQHandler,Default_Handler
+
+ .weak COMP1_IRQHandler
+ .thumb_set COMP1_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak LPTIM4_IRQHandler
+ .thumb_set LPTIM4_IRQHandler,Default_Handler
+
+ .weak LPTIM5_IRQHandler
+ .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak WWDG_RST_IRQHandler
+ .thumb_set WWDG_RST_IRQHandler,Default_Handler
+
+ .weak CRS_IRQHandler
+ .thumb_set CRS_IRQHandler,Default_Handler
+
+ .weak ECC_IRQHandler
+ .thumb_set ECC_IRQHandler,Default_Handler
+
+ .weak SAI4_IRQHandler
+ .thumb_set SAI4_IRQHandler,Default_Handler
+
+ .weak HOLD_CORE_IRQHandler
+ .thumb_set HOLD_CORE_IRQHandler,Default_Handler
+
+ .weak WAKEUP_PIN_IRQHandler
+ .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h750xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h750xx.s new file mode 100644 index 0000000..08ca794 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h750xx.s @@ -0,0 +1,752 @@ +/**
+ ******************************************************************************
+ * @file startup_stm32h750xx.s
+ * @author MCD Application Team
+ * @brief STM32H750xx Devices vector table for GCC based toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m7
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+ /* External Interrupts */
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
+ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_IRQHandler /* EXTI Line0 */
+ .word EXTI1_IRQHandler /* EXTI Line1 */
+ .word EXTI2_IRQHandler /* EXTI Line2 */
+ .word EXTI3_IRQHandler /* EXTI Line3 */
+ .word EXTI4_IRQHandler /* EXTI Line4 */
+ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
+ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
+ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
+ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
+ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
+ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
+ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
+ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
+ .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
+ .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
+ .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
+ .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
+ .word EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
+ .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
+ .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM4_IRQHandler /* TIM4 */
+ .word I2C1_EV_IRQHandler /* I2C1 Event */
+ .word I2C1_ER_IRQHandler /* I2C1 Error */
+ .word I2C2_EV_IRQHandler /* I2C2 Event */
+ .word I2C2_ER_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
+ .word 0 /* Reserved */
+ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
+ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
+ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
+ .word FMC_IRQHandler /* FMC */
+ .word SDMMC1_IRQHandler /* SDMMC1 */
+ .word TIM5_IRQHandler /* TIM5 */
+ .word SPI3_IRQHandler /* SPI3 */
+ .word UART4_IRQHandler /* UART4 */
+ .word UART5_IRQHandler /* UART5 */
+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
+ .word TIM7_IRQHandler /* TIM7 */
+ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
+ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
+ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
+ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
+ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
+ .word ETH_IRQHandler /* Ethernet */
+ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
+ .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
+ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
+ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
+ .word USART6_IRQHandler /* USART6 */
+ .word I2C3_EV_IRQHandler /* I2C3 event */
+ .word I2C3_ER_IRQHandler /* I2C3 error */
+ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
+ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
+ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
+ .word OTG_HS_IRQHandler /* USB OTG HS */
+ .word DCMI_IRQHandler /* DCMI */
+ .word CRYP_IRQHandler /* Crypto */
+ .word HASH_RNG_IRQHandler /* Hash and Rng */
+ .word FPU_IRQHandler /* FPU */
+ .word UART7_IRQHandler /* UART7 */
+ .word UART8_IRQHandler /* UART8 */
+ .word SPI4_IRQHandler /* SPI4 */
+ .word SPI5_IRQHandler /* SPI5 */
+ .word SPI6_IRQHandler /* SPI6 */
+ .word SAI1_IRQHandler /* SAI1 */
+ .word LTDC_IRQHandler /* LTDC */
+ .word LTDC_ER_IRQHandler /* LTDC error */
+ .word DMA2D_IRQHandler /* DMA2D */
+ .word SAI2_IRQHandler /* SAI2 */
+ .word QUADSPI_IRQHandler /* QUADSPI */
+ .word LPTIM1_IRQHandler /* LPTIM1 */
+ .word CEC_IRQHandler /* HDMI_CEC */
+ .word I2C4_EV_IRQHandler /* I2C4 Event */
+ .word I2C4_ER_IRQHandler /* I2C4 Error */
+ .word SPDIF_RX_IRQHandler /* SPDIF_RX */
+ .word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */
+ .word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */
+ .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */
+ .word OTG_FS_IRQHandler /* USB OTG FS */
+ .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
+ .word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */
+ .word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */
+ .word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */
+ .word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */
+ .word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */
+ .word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */
+ .word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */
+ .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
+ .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
+ .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
+ .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
+ .word SAI3_IRQHandler /* SAI3 global Interrupt */
+ .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
+ .word TIM15_IRQHandler /* TIM15 global Interrupt */
+ .word TIM16_IRQHandler /* TIM16 global Interrupt */
+ .word TIM17_IRQHandler /* TIM17 global Interrupt */
+ .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
+ .word MDIOS_IRQHandler /* MDIOS global Interrupt */
+ .word JPEG_IRQHandler /* JPEG global Interrupt */
+ .word MDMA_IRQHandler /* MDMA global Interrupt */
+ .word 0 /* Reserved */
+ .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
+ .word HSEM1_IRQHandler /* HSEM1 global Interrupt */
+ .word 0 /* Reserved */
+ .word ADC3_IRQHandler /* ADC3 global Interrupt */
+ .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
+ .word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
+ .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
+ .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
+ .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
+ .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
+ .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
+ .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
+ .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
+ .word COMP1_IRQHandler /* COMP1 global Interrupt */
+ .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
+ .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
+ .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
+ .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
+ .word LPUART1_IRQHandler /* LP UART1 interrupt */
+ .word 0 /* Reserved */
+ .word CRS_IRQHandler /* Clock Recovery Global Interrupt */
+ .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
+ .word SAI4_IRQHandler /* SAI4 global interrupt */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_AVD_IRQHandler
+ .thumb_set PVD_AVD_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream0_IRQHandler
+ .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream1_IRQHandler
+ .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream2_IRQHandler
+ .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream3_IRQHandler
+ .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream4_IRQHandler
+ .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream5_IRQHandler
+ .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream6_IRQHandler
+ .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT0_IRQHandler
+ .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT0_IRQHandler
+ .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT1_IRQHandler
+ .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT1_IRQHandler
+ .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_TIM12_IRQHandler
+ .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_TIM13_IRQHandler
+ .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_TIM14_IRQHandler
+ .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream7_IRQHandler
+ .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+ .weak FMC_IRQHandler
+ .thumb_set FMC_IRQHandler,Default_Handler
+
+ .weak SDMMC1_IRQHandler
+ .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream0_IRQHandler
+ .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream1_IRQHandler
+ .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream2_IRQHandler
+ .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream3_IRQHandler
+ .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream4_IRQHandler
+ .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+ .weak ETH_IRQHandler
+ .thumb_set ETH_IRQHandler,Default_Handler
+
+ .weak ETH_WKUP_IRQHandler
+ .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+ .weak FDCAN_CAL_IRQHandler
+ .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream5_IRQHandler
+ .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream6_IRQHandler
+ .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream7_IRQHandler
+ .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+ .weak USART6_IRQHandler
+ .thumb_set USART6_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_OUT_IRQHandler
+ .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_IN_IRQHandler
+ .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_HS_WKUP_IRQHandler
+ .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_HS_IRQHandler
+ .thumb_set OTG_HS_IRQHandler,Default_Handler
+
+ .weak DCMI_IRQHandler
+ .thumb_set DCMI_IRQHandler,Default_Handler
+
+ .weak CRYP_IRQHandler
+ .thumb_set CRYP_IRQHandler,Default_Handler
+
+ .weak HASH_RNG_IRQHandler
+ .thumb_set HASH_RNG_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak UART7_IRQHandler
+ .thumb_set UART7_IRQHandler,Default_Handler
+
+ .weak UART8_IRQHandler
+ .thumb_set UART8_IRQHandler,Default_Handler
+
+ .weak SPI4_IRQHandler
+ .thumb_set SPI4_IRQHandler,Default_Handler
+
+ .weak SPI5_IRQHandler
+ .thumb_set SPI5_IRQHandler,Default_Handler
+
+ .weak SPI6_IRQHandler
+ .thumb_set SPI6_IRQHandler,Default_Handler
+
+ .weak SAI1_IRQHandler
+ .thumb_set SAI1_IRQHandler,Default_Handler
+
+ .weak LTDC_IRQHandler
+ .thumb_set LTDC_IRQHandler,Default_Handler
+
+ .weak LTDC_ER_IRQHandler
+ .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+ .weak DMA2D_IRQHandler
+ .thumb_set DMA2D_IRQHandler,Default_Handler
+
+ .weak SAI2_IRQHandler
+ .thumb_set SAI2_IRQHandler,Default_Handler
+
+ .weak QUADSPI_IRQHandler
+ .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak I2C4_EV_IRQHandler
+ .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+ .weak I2C4_ER_IRQHandler
+ .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+ .weak SPDIF_RX_IRQHandler
+ .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+ .weak OTG_FS_EP1_OUT_IRQHandler
+ .thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_FS_EP1_IN_IRQHandler
+ .thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_FS_WKUP_IRQHandler
+ .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_FS_IRQHandler
+ .thumb_set OTG_FS_IRQHandler,Default_Handler
+
+ .weak DMAMUX1_OVR_IRQHandler
+ .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+ .weak HRTIM1_Master_IRQHandler
+ .thumb_set HRTIM1_Master_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMA_IRQHandler
+ .thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMB_IRQHandler
+ .thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMC_IRQHandler
+ .thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMD_IRQHandler
+ .thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIME_IRQHandler
+ .thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
+
+ .weak HRTIM1_FLT_IRQHandler
+ .thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT0_IRQHandler
+ .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT1_IRQHandler
+ .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT2_IRQHandler
+ .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT3_IRQHandler
+ .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+ .weak SAI3_IRQHandler
+ .thumb_set SAI3_IRQHandler,Default_Handler
+
+ .weak SWPMI1_IRQHandler
+ .thumb_set SWPMI1_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak MDIOS_WKUP_IRQHandler
+ .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
+
+ .weak MDIOS_IRQHandler
+ .thumb_set MDIOS_IRQHandler,Default_Handler
+
+ .weak JPEG_IRQHandler
+ .thumb_set JPEG_IRQHandler,Default_Handler
+
+ .weak MDMA_IRQHandler
+ .thumb_set MDMA_IRQHandler,Default_Handler
+
+ .weak SDMMC2_IRQHandler
+ .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+ .weak HSEM1_IRQHandler
+ .thumb_set HSEM1_IRQHandler,Default_Handler
+
+ .weak ADC3_IRQHandler
+ .thumb_set ADC3_IRQHandler,Default_Handler
+
+ .weak DMAMUX2_OVR_IRQHandler
+ .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel0_IRQHandler
+ .thumb_set BDMA_Channel0_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel1_IRQHandler
+ .thumb_set BDMA_Channel1_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel2_IRQHandler
+ .thumb_set BDMA_Channel2_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel3_IRQHandler
+ .thumb_set BDMA_Channel3_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel4_IRQHandler
+ .thumb_set BDMA_Channel4_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel5_IRQHandler
+ .thumb_set BDMA_Channel5_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel6_IRQHandler
+ .thumb_set BDMA_Channel6_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel7_IRQHandler
+ .thumb_set BDMA_Channel7_IRQHandler,Default_Handler
+
+ .weak COMP1_IRQHandler
+ .thumb_set COMP1_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak LPTIM4_IRQHandler
+ .thumb_set LPTIM4_IRQHandler,Default_Handler
+
+ .weak LPTIM5_IRQHandler
+ .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak CRS_IRQHandler
+ .thumb_set CRS_IRQHandler,Default_Handler
+
+ .weak ECC_IRQHandler
+ .thumb_set ECC_IRQHandler,Default_Handler
+
+ .weak SAI4_IRQHandler
+ .thumb_set SAI4_IRQHandler,Default_Handler
+
+ .weak WAKEUP_PIN_IRQHandler
+ .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h753xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h753xx.s new file mode 100644 index 0000000..1551654 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h753xx.s @@ -0,0 +1,752 @@ +/**
+ ******************************************************************************
+ * @file startup_stm32h753xx.s
+ * @author MCD Application Team
+ * @brief STM32H753xx Devices vector table for GCC based toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m7
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+ /* External Interrupts */
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
+ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_IRQHandler /* EXTI Line0 */
+ .word EXTI1_IRQHandler /* EXTI Line1 */
+ .word EXTI2_IRQHandler /* EXTI Line2 */
+ .word EXTI3_IRQHandler /* EXTI Line3 */
+ .word EXTI4_IRQHandler /* EXTI Line4 */
+ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
+ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
+ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
+ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
+ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
+ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
+ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
+ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
+ .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
+ .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
+ .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
+ .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
+ .word EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
+ .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
+ .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM4_IRQHandler /* TIM4 */
+ .word I2C1_EV_IRQHandler /* I2C1 Event */
+ .word I2C1_ER_IRQHandler /* I2C1 Error */
+ .word I2C2_EV_IRQHandler /* I2C2 Event */
+ .word I2C2_ER_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
+ .word 0 /* Reserved */
+ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
+ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
+ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
+ .word FMC_IRQHandler /* FMC */
+ .word SDMMC1_IRQHandler /* SDMMC1 */
+ .word TIM5_IRQHandler /* TIM5 */
+ .word SPI3_IRQHandler /* SPI3 */
+ .word UART4_IRQHandler /* UART4 */
+ .word UART5_IRQHandler /* UART5 */
+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
+ .word TIM7_IRQHandler /* TIM7 */
+ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
+ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
+ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
+ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
+ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
+ .word ETH_IRQHandler /* Ethernet */
+ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
+ .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
+ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
+ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
+ .word USART6_IRQHandler /* USART6 */
+ .word I2C3_EV_IRQHandler /* I2C3 event */
+ .word I2C3_ER_IRQHandler /* I2C3 error */
+ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
+ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
+ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
+ .word OTG_HS_IRQHandler /* USB OTG HS */
+ .word DCMI_IRQHandler /* DCMI */
+ .word CRYP_IRQHandler /* Crypto */
+ .word HASH_RNG_IRQHandler /* Hash and Rng */
+ .word FPU_IRQHandler /* FPU */
+ .word UART7_IRQHandler /* UART7 */
+ .word UART8_IRQHandler /* UART8 */
+ .word SPI4_IRQHandler /* SPI4 */
+ .word SPI5_IRQHandler /* SPI5 */
+ .word SPI6_IRQHandler /* SPI6 */
+ .word SAI1_IRQHandler /* SAI1 */
+ .word LTDC_IRQHandler /* LTDC */
+ .word LTDC_ER_IRQHandler /* LTDC error */
+ .word DMA2D_IRQHandler /* DMA2D */
+ .word SAI2_IRQHandler /* SAI2 */
+ .word QUADSPI_IRQHandler /* QUADSPI */
+ .word LPTIM1_IRQHandler /* LPTIM1 */
+ .word CEC_IRQHandler /* HDMI_CEC */
+ .word I2C4_EV_IRQHandler /* I2C4 Event */
+ .word I2C4_ER_IRQHandler /* I2C4 Error */
+ .word SPDIF_RX_IRQHandler /* SPDIF_RX */
+ .word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */
+ .word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */
+ .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */
+ .word OTG_FS_IRQHandler /* USB OTG FS */
+ .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
+ .word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */
+ .word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */
+ .word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */
+ .word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */
+ .word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */
+ .word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */
+ .word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */
+ .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
+ .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
+ .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
+ .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
+ .word SAI3_IRQHandler /* SAI3 global Interrupt */
+ .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
+ .word TIM15_IRQHandler /* TIM15 global Interrupt */
+ .word TIM16_IRQHandler /* TIM16 global Interrupt */
+ .word TIM17_IRQHandler /* TIM17 global Interrupt */
+ .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
+ .word MDIOS_IRQHandler /* MDIOS global Interrupt */
+ .word JPEG_IRQHandler /* JPEG global Interrupt */
+ .word MDMA_IRQHandler /* MDMA global Interrupt */
+ .word 0 /* Reserved */
+ .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
+ .word HSEM1_IRQHandler /* HSEM1 global Interrupt */
+ .word 0 /* Reserved */
+ .word ADC3_IRQHandler /* ADC3 global Interrupt */
+ .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
+ .word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
+ .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
+ .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
+ .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
+ .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
+ .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
+ .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
+ .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
+ .word COMP1_IRQHandler /* COMP1 global Interrupt */
+ .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
+ .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
+ .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
+ .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
+ .word LPUART1_IRQHandler /* LP UART1 interrupt */
+ .word 0 /* Reserved */
+ .word CRS_IRQHandler /* Clock Recovery Global Interrupt */
+ .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
+ .word SAI4_IRQHandler /* SAI4 global interrupt */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_AVD_IRQHandler
+ .thumb_set PVD_AVD_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream0_IRQHandler
+ .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream1_IRQHandler
+ .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream2_IRQHandler
+ .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream3_IRQHandler
+ .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream4_IRQHandler
+ .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream5_IRQHandler
+ .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream6_IRQHandler
+ .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT0_IRQHandler
+ .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT0_IRQHandler
+ .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT1_IRQHandler
+ .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT1_IRQHandler
+ .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_TIM12_IRQHandler
+ .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_TIM13_IRQHandler
+ .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_TIM14_IRQHandler
+ .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream7_IRQHandler
+ .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+ .weak FMC_IRQHandler
+ .thumb_set FMC_IRQHandler,Default_Handler
+
+ .weak SDMMC1_IRQHandler
+ .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream0_IRQHandler
+ .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream1_IRQHandler
+ .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream2_IRQHandler
+ .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream3_IRQHandler
+ .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream4_IRQHandler
+ .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+ .weak ETH_IRQHandler
+ .thumb_set ETH_IRQHandler,Default_Handler
+
+ .weak ETH_WKUP_IRQHandler
+ .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+ .weak FDCAN_CAL_IRQHandler
+ .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream5_IRQHandler
+ .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream6_IRQHandler
+ .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream7_IRQHandler
+ .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+ .weak USART6_IRQHandler
+ .thumb_set USART6_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_OUT_IRQHandler
+ .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_IN_IRQHandler
+ .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_HS_WKUP_IRQHandler
+ .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_HS_IRQHandler
+ .thumb_set OTG_HS_IRQHandler,Default_Handler
+
+ .weak DCMI_IRQHandler
+ .thumb_set DCMI_IRQHandler,Default_Handler
+
+ .weak CRYP_IRQHandler
+ .thumb_set CRYP_IRQHandler,Default_Handler
+
+ .weak HASH_RNG_IRQHandler
+ .thumb_set HASH_RNG_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak UART7_IRQHandler
+ .thumb_set UART7_IRQHandler,Default_Handler
+
+ .weak UART8_IRQHandler
+ .thumb_set UART8_IRQHandler,Default_Handler
+
+ .weak SPI4_IRQHandler
+ .thumb_set SPI4_IRQHandler,Default_Handler
+
+ .weak SPI5_IRQHandler
+ .thumb_set SPI5_IRQHandler,Default_Handler
+
+ .weak SPI6_IRQHandler
+ .thumb_set SPI6_IRQHandler,Default_Handler
+
+ .weak SAI1_IRQHandler
+ .thumb_set SAI1_IRQHandler,Default_Handler
+
+ .weak LTDC_IRQHandler
+ .thumb_set LTDC_IRQHandler,Default_Handler
+
+ .weak LTDC_ER_IRQHandler
+ .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+ .weak DMA2D_IRQHandler
+ .thumb_set DMA2D_IRQHandler,Default_Handler
+
+ .weak SAI2_IRQHandler
+ .thumb_set SAI2_IRQHandler,Default_Handler
+
+ .weak QUADSPI_IRQHandler
+ .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak I2C4_EV_IRQHandler
+ .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+ .weak I2C4_ER_IRQHandler
+ .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+ .weak SPDIF_RX_IRQHandler
+ .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+ .weak OTG_FS_EP1_OUT_IRQHandler
+ .thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_FS_EP1_IN_IRQHandler
+ .thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_FS_WKUP_IRQHandler
+ .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_FS_IRQHandler
+ .thumb_set OTG_FS_IRQHandler,Default_Handler
+
+ .weak DMAMUX1_OVR_IRQHandler
+ .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+ .weak HRTIM1_Master_IRQHandler
+ .thumb_set HRTIM1_Master_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMA_IRQHandler
+ .thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMB_IRQHandler
+ .thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMC_IRQHandler
+ .thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMD_IRQHandler
+ .thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIME_IRQHandler
+ .thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
+
+ .weak HRTIM1_FLT_IRQHandler
+ .thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT0_IRQHandler
+ .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT1_IRQHandler
+ .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT2_IRQHandler
+ .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT3_IRQHandler
+ .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+ .weak SAI3_IRQHandler
+ .thumb_set SAI3_IRQHandler,Default_Handler
+
+ .weak SWPMI1_IRQHandler
+ .thumb_set SWPMI1_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak MDIOS_WKUP_IRQHandler
+ .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
+
+ .weak MDIOS_IRQHandler
+ .thumb_set MDIOS_IRQHandler,Default_Handler
+
+ .weak JPEG_IRQHandler
+ .thumb_set JPEG_IRQHandler,Default_Handler
+
+ .weak MDMA_IRQHandler
+ .thumb_set MDMA_IRQHandler,Default_Handler
+
+ .weak SDMMC2_IRQHandler
+ .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+ .weak HSEM1_IRQHandler
+ .thumb_set HSEM1_IRQHandler,Default_Handler
+
+ .weak ADC3_IRQHandler
+ .thumb_set ADC3_IRQHandler,Default_Handler
+
+ .weak DMAMUX2_OVR_IRQHandler
+ .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel0_IRQHandler
+ .thumb_set BDMA_Channel0_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel1_IRQHandler
+ .thumb_set BDMA_Channel1_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel2_IRQHandler
+ .thumb_set BDMA_Channel2_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel3_IRQHandler
+ .thumb_set BDMA_Channel3_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel4_IRQHandler
+ .thumb_set BDMA_Channel4_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel5_IRQHandler
+ .thumb_set BDMA_Channel5_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel6_IRQHandler
+ .thumb_set BDMA_Channel6_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel7_IRQHandler
+ .thumb_set BDMA_Channel7_IRQHandler,Default_Handler
+
+ .weak COMP1_IRQHandler
+ .thumb_set COMP1_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak LPTIM4_IRQHandler
+ .thumb_set LPTIM4_IRQHandler,Default_Handler
+
+ .weak LPTIM5_IRQHandler
+ .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak CRS_IRQHandler
+ .thumb_set CRS_IRQHandler,Default_Handler
+
+ .weak ECC_IRQHandler
+ .thumb_set ECC_IRQHandler,Default_Handler
+
+ .weak SAI4_IRQHandler
+ .thumb_set SAI4_IRQHandler,Default_Handler
+
+ .weak WAKEUP_PIN_IRQHandler
+ .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h755xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h755xx.s new file mode 100644 index 0000000..3659855 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h755xx.s @@ -0,0 +1,767 @@ +/**
+ ******************************************************************************
+ * @file startup_stm32h755xx.s
+ * @author MCD Application Team
+ * @brief STM32H755xx Devices vector table for GCC based toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m7
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+ /* External Interrupts */
+ .word WWDG_IRQHandler /* Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */
+ .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
+ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_IRQHandler /* EXTI Line0 */
+ .word EXTI1_IRQHandler /* EXTI Line1 */
+ .word EXTI2_IRQHandler /* EXTI Line2 */
+ .word EXTI3_IRQHandler /* EXTI Line3 */
+ .word EXTI4_IRQHandler /* EXTI Line4 */
+ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
+ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
+ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
+ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
+ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
+ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
+ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
+ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
+ .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
+ .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
+ .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
+ .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
+ .word EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
+ .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
+ .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM4_IRQHandler /* TIM4 */
+ .word I2C1_EV_IRQHandler /* I2C1 Event */
+ .word I2C1_ER_IRQHandler /* I2C1 Error */
+ .word I2C2_EV_IRQHandler /* I2C2 Event */
+ .word I2C2_ER_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
+ .word 0 /* Reserved */
+ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
+ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
+ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
+ .word FMC_IRQHandler /* FMC */
+ .word SDMMC1_IRQHandler /* SDMMC1 */
+ .word TIM5_IRQHandler /* TIM5 */
+ .word SPI3_IRQHandler /* SPI3 */
+ .word UART4_IRQHandler /* UART4 */
+ .word UART5_IRQHandler /* UART5 */
+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
+ .word TIM7_IRQHandler /* TIM7 */
+ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
+ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
+ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
+ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
+ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
+ .word ETH_IRQHandler /* Ethernet */
+ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
+ .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt */
+ .word CM7_SEV_IRQHandler /* CM7 Send event interrupt for CM4 */
+ .word CM4_SEV_IRQHandler /* CM4 Send event interrupt for CM7 */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
+ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
+ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
+ .word USART6_IRQHandler /* USART6 */
+ .word I2C3_EV_IRQHandler /* I2C3 event */
+ .word I2C3_ER_IRQHandler /* I2C3 error */
+ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
+ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
+ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
+ .word OTG_HS_IRQHandler /* USB OTG HS */
+ .word DCMI_IRQHandler /* DCMI */
+ .word CRYP_IRQHandler /* Crypto */
+ .word HASH_RNG_IRQHandler /* Hash and Rng */
+ .word FPU_IRQHandler /* FPU */
+ .word UART7_IRQHandler /* UART7 */
+ .word UART8_IRQHandler /* UART8 */
+ .word SPI4_IRQHandler /* SPI4 */
+ .word SPI5_IRQHandler /* SPI5 */
+ .word SPI6_IRQHandler /* SPI6 */
+ .word SAI1_IRQHandler /* SAI1 */
+ .word LTDC_IRQHandler /* LTDC */
+ .word LTDC_ER_IRQHandler /* LTDC error */
+ .word DMA2D_IRQHandler /* DMA2D */
+ .word SAI2_IRQHandler /* SAI2 */
+ .word QUADSPI_IRQHandler /* QUADSPI */
+ .word LPTIM1_IRQHandler /* LPTIM1 */
+ .word CEC_IRQHandler /* HDMI_CEC */
+ .word I2C4_EV_IRQHandler /* I2C4 Event */
+ .word I2C4_ER_IRQHandler /* I2C4 Error */
+ .word SPDIF_RX_IRQHandler /* SPDIF_RX */
+ .word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */
+ .word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */
+ .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */
+ .word OTG_FS_IRQHandler /* USB OTG FS */
+ .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
+ .word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */
+ .word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */
+ .word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */
+ .word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */
+ .word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */
+ .word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */
+ .word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */
+ .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
+ .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
+ .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
+ .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
+ .word SAI3_IRQHandler /* SAI3 global Interrupt */
+ .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
+ .word TIM15_IRQHandler /* TIM15 global Interrupt */
+ .word TIM16_IRQHandler /* TIM16 global Interrupt */
+ .word TIM17_IRQHandler /* TIM17 global Interrupt */
+ .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
+ .word MDIOS_IRQHandler /* MDIOS global Interrupt */
+ .word JPEG_IRQHandler /* JPEG global Interrupt */
+ .word MDMA_IRQHandler /* MDMA global Interrupt */
+ .word 0 /* Reserved */
+ .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
+ .word HSEM1_IRQHandler /* HSEM1 global Interrupt */
+ .word HSEM2_IRQHandler /* HSEM1 global Interrupt */
+ .word ADC3_IRQHandler /* ADC3 global Interrupt */
+ .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
+ .word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
+ .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
+ .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
+ .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
+ .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
+ .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
+ .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
+ .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
+ .word COMP1_IRQHandler /* COMP1 global Interrupt */
+ .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
+ .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
+ .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
+ .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
+ .word LPUART1_IRQHandler /* LP UART1 interrupt */
+ .word WWDG_RST_IRQHandler /* Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) */
+ .word CRS_IRQHandler /* Clock Recovery Global Interrupt */
+ .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
+ .word SAI4_IRQHandler /* SAI4 global interrupt */
+ .word 0 /* Reserved */
+ .word HOLD_CORE_IRQHandler /* Hold core interrupt */
+ .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_AVD_IRQHandler
+ .thumb_set PVD_AVD_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream0_IRQHandler
+ .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream1_IRQHandler
+ .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream2_IRQHandler
+ .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream3_IRQHandler
+ .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream4_IRQHandler
+ .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream5_IRQHandler
+ .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream6_IRQHandler
+ .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT0_IRQHandler
+ .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT0_IRQHandler
+ .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT1_IRQHandler
+ .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT1_IRQHandler
+ .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_TIM12_IRQHandler
+ .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_TIM13_IRQHandler
+ .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_TIM14_IRQHandler
+ .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream7_IRQHandler
+ .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+ .weak FMC_IRQHandler
+ .thumb_set FMC_IRQHandler,Default_Handler
+
+ .weak SDMMC1_IRQHandler
+ .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream0_IRQHandler
+ .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream1_IRQHandler
+ .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream2_IRQHandler
+ .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream3_IRQHandler
+ .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream4_IRQHandler
+ .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+ .weak ETH_IRQHandler
+ .thumb_set ETH_IRQHandler,Default_Handler
+
+ .weak ETH_WKUP_IRQHandler
+ .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+ .weak FDCAN_CAL_IRQHandler
+ .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+
+ .weak CM7_SEV_IRQHandler
+ .thumb_set CM7_SEV_IRQHandler,Default_Handler
+
+ .weak CM4_SEV_IRQHandler
+ .thumb_set CM4_SEV_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream5_IRQHandler
+ .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream6_IRQHandler
+ .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream7_IRQHandler
+ .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+ .weak USART6_IRQHandler
+ .thumb_set USART6_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_OUT_IRQHandler
+ .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_IN_IRQHandler
+ .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_HS_WKUP_IRQHandler
+ .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_HS_IRQHandler
+ .thumb_set OTG_HS_IRQHandler,Default_Handler
+
+ .weak DCMI_IRQHandler
+ .thumb_set DCMI_IRQHandler,Default_Handler
+
+ .weak CRYP_IRQHandler
+ .thumb_set CRYP_IRQHandler,Default_Handler
+
+ .weak HASH_RNG_IRQHandler
+ .thumb_set HASH_RNG_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak UART7_IRQHandler
+ .thumb_set UART7_IRQHandler,Default_Handler
+
+ .weak UART8_IRQHandler
+ .thumb_set UART8_IRQHandler,Default_Handler
+
+ .weak SPI4_IRQHandler
+ .thumb_set SPI4_IRQHandler,Default_Handler
+
+ .weak SPI5_IRQHandler
+ .thumb_set SPI5_IRQHandler,Default_Handler
+
+ .weak SPI6_IRQHandler
+ .thumb_set SPI6_IRQHandler,Default_Handler
+
+ .weak SAI1_IRQHandler
+ .thumb_set SAI1_IRQHandler,Default_Handler
+
+ .weak LTDC_IRQHandler
+ .thumb_set LTDC_IRQHandler,Default_Handler
+
+ .weak LTDC_ER_IRQHandler
+ .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+ .weak DMA2D_IRQHandler
+ .thumb_set DMA2D_IRQHandler,Default_Handler
+
+ .weak SAI2_IRQHandler
+ .thumb_set SAI2_IRQHandler,Default_Handler
+
+ .weak QUADSPI_IRQHandler
+ .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak I2C4_EV_IRQHandler
+ .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+ .weak I2C4_ER_IRQHandler
+ .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+ .weak SPDIF_RX_IRQHandler
+ .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+ .weak OTG_FS_EP1_OUT_IRQHandler
+ .thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_FS_EP1_IN_IRQHandler
+ .thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_FS_WKUP_IRQHandler
+ .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_FS_IRQHandler
+ .thumb_set OTG_FS_IRQHandler,Default_Handler
+
+ .weak DMAMUX1_OVR_IRQHandler
+ .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+ .weak HRTIM1_Master_IRQHandler
+ .thumb_set HRTIM1_Master_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMA_IRQHandler
+ .thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMB_IRQHandler
+ .thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMC_IRQHandler
+ .thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMD_IRQHandler
+ .thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIME_IRQHandler
+ .thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
+
+ .weak HRTIM1_FLT_IRQHandler
+ .thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT0_IRQHandler
+ .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT1_IRQHandler
+ .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT2_IRQHandler
+ .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT3_IRQHandler
+ .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+ .weak SAI3_IRQHandler
+ .thumb_set SAI3_IRQHandler,Default_Handler
+
+ .weak SWPMI1_IRQHandler
+ .thumb_set SWPMI1_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak MDIOS_WKUP_IRQHandler
+ .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
+
+ .weak MDIOS_IRQHandler
+ .thumb_set MDIOS_IRQHandler,Default_Handler
+
+ .weak JPEG_IRQHandler
+ .thumb_set JPEG_IRQHandler,Default_Handler
+
+ .weak MDMA_IRQHandler
+ .thumb_set MDMA_IRQHandler,Default_Handler
+
+ .weak SDMMC2_IRQHandler
+ .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+ .weak HSEM1_IRQHandler
+ .thumb_set HSEM1_IRQHandler,Default_Handler
+
+ .weak HSEM2_IRQHandler
+ .thumb_set HSEM2_IRQHandler,Default_Handler
+
+ .weak ADC3_IRQHandler
+ .thumb_set ADC3_IRQHandler,Default_Handler
+
+ .weak DMAMUX2_OVR_IRQHandler
+ .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel0_IRQHandler
+ .thumb_set BDMA_Channel0_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel1_IRQHandler
+ .thumb_set BDMA_Channel1_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel2_IRQHandler
+ .thumb_set BDMA_Channel2_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel3_IRQHandler
+ .thumb_set BDMA_Channel3_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel4_IRQHandler
+ .thumb_set BDMA_Channel4_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel5_IRQHandler
+ .thumb_set BDMA_Channel5_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel6_IRQHandler
+ .thumb_set BDMA_Channel6_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel7_IRQHandler
+ .thumb_set BDMA_Channel7_IRQHandler,Default_Handler
+
+ .weak COMP1_IRQHandler
+ .thumb_set COMP1_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak LPTIM4_IRQHandler
+ .thumb_set LPTIM4_IRQHandler,Default_Handler
+
+ .weak LPTIM5_IRQHandler
+ .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak WWDG_RST_IRQHandler
+ .thumb_set WWDG_RST_IRQHandler,Default_Handler
+
+ .weak CRS_IRQHandler
+ .thumb_set CRS_IRQHandler,Default_Handler
+
+ .weak ECC_IRQHandler
+ .thumb_set ECC_IRQHandler,Default_Handler
+
+ .weak SAI4_IRQHandler
+ .thumb_set SAI4_IRQHandler,Default_Handler
+
+ .weak HOLD_CORE_IRQHandler
+ .thumb_set HOLD_CORE_IRQHandler,Default_Handler
+
+ .weak WAKEUP_PIN_IRQHandler
+ .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h757xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h757xx.s new file mode 100644 index 0000000..89a399b --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h757xx.s @@ -0,0 +1,770 @@ +/**
+ ******************************************************************************
+ * @file startup_stm32h757xx.s
+ * @author MCD Application Team
+ * @brief STM32H757xx Devices vector table for GCC based toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m7
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+ /* External Interrupts */
+ .word WWDG_IRQHandler /* Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */
+ .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
+ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_IRQHandler /* EXTI Line0 */
+ .word EXTI1_IRQHandler /* EXTI Line1 */
+ .word EXTI2_IRQHandler /* EXTI Line2 */
+ .word EXTI3_IRQHandler /* EXTI Line3 */
+ .word EXTI4_IRQHandler /* EXTI Line4 */
+ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
+ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
+ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
+ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
+ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
+ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
+ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
+ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
+ .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
+ .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
+ .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
+ .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
+ .word EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
+ .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
+ .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM4_IRQHandler /* TIM4 */
+ .word I2C1_EV_IRQHandler /* I2C1 Event */
+ .word I2C1_ER_IRQHandler /* I2C1 Error */
+ .word I2C2_EV_IRQHandler /* I2C2 Event */
+ .word I2C2_ER_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
+ .word 0 /* Reserved */
+ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
+ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
+ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
+ .word FMC_IRQHandler /* FMC */
+ .word SDMMC1_IRQHandler /* SDMMC1 */
+ .word TIM5_IRQHandler /* TIM5 */
+ .word SPI3_IRQHandler /* SPI3 */
+ .word UART4_IRQHandler /* UART4 */
+ .word UART5_IRQHandler /* UART5 */
+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
+ .word TIM7_IRQHandler /* TIM7 */
+ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
+ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
+ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
+ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
+ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
+ .word ETH_IRQHandler /* Ethernet */
+ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
+ .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt */
+ .word CM7_SEV_IRQHandler /* CM7 Send event interrupt for CM4 */
+ .word CM4_SEV_IRQHandler /* CM4 Send event interrupt for CM7 */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
+ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
+ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
+ .word USART6_IRQHandler /* USART6 */
+ .word I2C3_EV_IRQHandler /* I2C3 event */
+ .word I2C3_ER_IRQHandler /* I2C3 error */
+ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
+ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
+ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
+ .word OTG_HS_IRQHandler /* USB OTG HS */
+ .word DCMI_IRQHandler /* DCMI */
+ .word CRYP_IRQHandler /* Crypto */
+ .word HASH_RNG_IRQHandler /* Hash and Rng */
+ .word FPU_IRQHandler /* FPU */
+ .word UART7_IRQHandler /* UART7 */
+ .word UART8_IRQHandler /* UART8 */
+ .word SPI4_IRQHandler /* SPI4 */
+ .word SPI5_IRQHandler /* SPI5 */
+ .word SPI6_IRQHandler /* SPI6 */
+ .word SAI1_IRQHandler /* SAI1 */
+ .word LTDC_IRQHandler /* LTDC */
+ .word LTDC_ER_IRQHandler /* LTDC error */
+ .word DMA2D_IRQHandler /* DMA2D */
+ .word SAI2_IRQHandler /* SAI2 */
+ .word QUADSPI_IRQHandler /* QUADSPI */
+ .word LPTIM1_IRQHandler /* LPTIM1 */
+ .word CEC_IRQHandler /* HDMI_CEC */
+ .word I2C4_EV_IRQHandler /* I2C4 Event */
+ .word I2C4_ER_IRQHandler /* I2C4 Error */
+ .word SPDIF_RX_IRQHandler /* SPDIF_RX */
+ .word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */
+ .word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */
+ .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */
+ .word OTG_FS_IRQHandler /* USB OTG FS */
+ .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
+ .word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */
+ .word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */
+ .word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */
+ .word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */
+ .word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */
+ .word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */
+ .word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */
+ .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
+ .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
+ .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
+ .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
+ .word SAI3_IRQHandler /* SAI3 global Interrupt */
+ .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
+ .word TIM15_IRQHandler /* TIM15 global Interrupt */
+ .word TIM16_IRQHandler /* TIM16 global Interrupt */
+ .word TIM17_IRQHandler /* TIM17 global Interrupt */
+ .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
+ .word MDIOS_IRQHandler /* MDIOS global Interrupt */
+ .word JPEG_IRQHandler /* JPEG global Interrupt */
+ .word MDMA_IRQHandler /* MDMA global Interrupt */
+ .word DSI_IRQHandler /* DSI global Interrupt */
+ .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
+ .word HSEM1_IRQHandler /* HSEM1 global Interrupt */
+ .word HSEM2_IRQHandler /* HSEM1 global Interrupt */
+ .word ADC3_IRQHandler /* ADC3 global Interrupt */
+ .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
+ .word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
+ .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
+ .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
+ .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
+ .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
+ .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
+ .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
+ .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
+ .word COMP1_IRQHandler /* COMP1 global Interrupt */
+ .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
+ .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
+ .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
+ .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
+ .word LPUART1_IRQHandler /* LP UART1 interrupt */
+ .word WWDG_RST_IRQHandler /* Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) */
+ .word CRS_IRQHandler /* Clock Recovery Global Interrupt */
+ .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
+ .word SAI4_IRQHandler /* SAI4 global interrupt */
+ .word 0 /* Reserved */
+ .word HOLD_CORE_IRQHandler /* Hold core interrupt */
+ .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_AVD_IRQHandler
+ .thumb_set PVD_AVD_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream0_IRQHandler
+ .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream1_IRQHandler
+ .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream2_IRQHandler
+ .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream3_IRQHandler
+ .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream4_IRQHandler
+ .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream5_IRQHandler
+ .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream6_IRQHandler
+ .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT0_IRQHandler
+ .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT0_IRQHandler
+ .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT1_IRQHandler
+ .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT1_IRQHandler
+ .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_TIM12_IRQHandler
+ .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_TIM13_IRQHandler
+ .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_TIM14_IRQHandler
+ .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream7_IRQHandler
+ .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+ .weak FMC_IRQHandler
+ .thumb_set FMC_IRQHandler,Default_Handler
+
+ .weak SDMMC1_IRQHandler
+ .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream0_IRQHandler
+ .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream1_IRQHandler
+ .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream2_IRQHandler
+ .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream3_IRQHandler
+ .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream4_IRQHandler
+ .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+ .weak ETH_IRQHandler
+ .thumb_set ETH_IRQHandler,Default_Handler
+
+ .weak ETH_WKUP_IRQHandler
+ .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+ .weak FDCAN_CAL_IRQHandler
+ .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+
+ .weak CM7_SEV_IRQHandler
+ .thumb_set CM7_SEV_IRQHandler,Default_Handler
+
+ .weak CM4_SEV_IRQHandler
+ .thumb_set CM4_SEV_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream5_IRQHandler
+ .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream6_IRQHandler
+ .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream7_IRQHandler
+ .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+ .weak USART6_IRQHandler
+ .thumb_set USART6_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_OUT_IRQHandler
+ .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_IN_IRQHandler
+ .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_HS_WKUP_IRQHandler
+ .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_HS_IRQHandler
+ .thumb_set OTG_HS_IRQHandler,Default_Handler
+
+ .weak DCMI_IRQHandler
+ .thumb_set DCMI_IRQHandler,Default_Handler
+
+ .weak CRYP_IRQHandler
+ .thumb_set CRYP_IRQHandler,Default_Handler
+
+ .weak HASH_RNG_IRQHandler
+ .thumb_set HASH_RNG_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak UART7_IRQHandler
+ .thumb_set UART7_IRQHandler,Default_Handler
+
+ .weak UART8_IRQHandler
+ .thumb_set UART8_IRQHandler,Default_Handler
+
+ .weak SPI4_IRQHandler
+ .thumb_set SPI4_IRQHandler,Default_Handler
+
+ .weak SPI5_IRQHandler
+ .thumb_set SPI5_IRQHandler,Default_Handler
+
+ .weak SPI6_IRQHandler
+ .thumb_set SPI6_IRQHandler,Default_Handler
+
+ .weak SAI1_IRQHandler
+ .thumb_set SAI1_IRQHandler,Default_Handler
+
+ .weak LTDC_IRQHandler
+ .thumb_set LTDC_IRQHandler,Default_Handler
+
+ .weak LTDC_ER_IRQHandler
+ .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+ .weak DMA2D_IRQHandler
+ .thumb_set DMA2D_IRQHandler,Default_Handler
+
+ .weak SAI2_IRQHandler
+ .thumb_set SAI2_IRQHandler,Default_Handler
+
+ .weak QUADSPI_IRQHandler
+ .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak I2C4_EV_IRQHandler
+ .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+ .weak I2C4_ER_IRQHandler
+ .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+ .weak SPDIF_RX_IRQHandler
+ .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+ .weak OTG_FS_EP1_OUT_IRQHandler
+ .thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_FS_EP1_IN_IRQHandler
+ .thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_FS_WKUP_IRQHandler
+ .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_FS_IRQHandler
+ .thumb_set OTG_FS_IRQHandler,Default_Handler
+
+ .weak DMAMUX1_OVR_IRQHandler
+ .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+ .weak HRTIM1_Master_IRQHandler
+ .thumb_set HRTIM1_Master_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMA_IRQHandler
+ .thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMB_IRQHandler
+ .thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMC_IRQHandler
+ .thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIMD_IRQHandler
+ .thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
+
+ .weak HRTIM1_TIME_IRQHandler
+ .thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
+
+ .weak HRTIM1_FLT_IRQHandler
+ .thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT0_IRQHandler
+ .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT1_IRQHandler
+ .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT2_IRQHandler
+ .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT3_IRQHandler
+ .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+ .weak SAI3_IRQHandler
+ .thumb_set SAI3_IRQHandler,Default_Handler
+
+ .weak SWPMI1_IRQHandler
+ .thumb_set SWPMI1_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak MDIOS_WKUP_IRQHandler
+ .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
+
+ .weak MDIOS_IRQHandler
+ .thumb_set MDIOS_IRQHandler,Default_Handler
+
+ .weak JPEG_IRQHandler
+ .thumb_set JPEG_IRQHandler,Default_Handler
+
+ .weak MDMA_IRQHandler
+ .thumb_set MDMA_IRQHandler,Default_Handler
+
+ .weak DSI_IRQHandler
+ .thumb_set DSI_IRQHandler,Default_Handler
+
+ .weak SDMMC2_IRQHandler
+ .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+ .weak HSEM1_IRQHandler
+ .thumb_set HSEM1_IRQHandler,Default_Handler
+
+ .weak HSEM2_IRQHandler
+ .thumb_set HSEM2_IRQHandler,Default_Handler
+
+ .weak ADC3_IRQHandler
+ .thumb_set ADC3_IRQHandler,Default_Handler
+
+ .weak DMAMUX2_OVR_IRQHandler
+ .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel0_IRQHandler
+ .thumb_set BDMA_Channel0_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel1_IRQHandler
+ .thumb_set BDMA_Channel1_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel2_IRQHandler
+ .thumb_set BDMA_Channel2_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel3_IRQHandler
+ .thumb_set BDMA_Channel3_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel4_IRQHandler
+ .thumb_set BDMA_Channel4_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel5_IRQHandler
+ .thumb_set BDMA_Channel5_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel6_IRQHandler
+ .thumb_set BDMA_Channel6_IRQHandler,Default_Handler
+
+ .weak BDMA_Channel7_IRQHandler
+ .thumb_set BDMA_Channel7_IRQHandler,Default_Handler
+
+ .weak COMP1_IRQHandler
+ .thumb_set COMP1_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak LPTIM4_IRQHandler
+ .thumb_set LPTIM4_IRQHandler,Default_Handler
+
+ .weak LPTIM5_IRQHandler
+ .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak WWDG_RST_IRQHandler
+ .thumb_set WWDG_RST_IRQHandler,Default_Handler
+
+ .weak CRS_IRQHandler
+ .thumb_set CRS_IRQHandler,Default_Handler
+
+ .weak ECC_IRQHandler
+ .thumb_set ECC_IRQHandler,Default_Handler
+
+ .weak SAI4_IRQHandler
+ .thumb_set SAI4_IRQHandler,Default_Handler
+
+ .weak HOLD_CORE_IRQHandler
+ .thumb_set HOLD_CORE_IRQHandler,Default_Handler
+
+ .weak WAKEUP_PIN_IRQHandler
+ .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7a3xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7a3xx.s new file mode 100644 index 0000000..ef595b2 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7a3xx.s @@ -0,0 +1,742 @@ +/**
+ ******************************************************************************
+ * @file startup_stm32h7a3xx.s
+ * @author MCD Application Team
+ * @brief STM32H7B3xx Devices vector table for GCC based toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m7
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+ /* External Interrupts */
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word PVD_PVM_IRQHandler /* PVD/PVM through EXTI Line detection */
+ .word RTC_TAMP_STAMP_CSS_LSE_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_IRQHandler /* EXTI Line0 */
+ .word EXTI1_IRQHandler /* EXTI Line1 */
+ .word EXTI2_IRQHandler /* EXTI Line2 */
+ .word EXTI3_IRQHandler /* EXTI Line3 */
+ .word EXTI4_IRQHandler /* EXTI Line4 */
+ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
+ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
+ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
+ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
+ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
+ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
+ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
+ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
+ .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
+ .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
+ .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
+ .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
+ .word EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
+ .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
+ .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM4_IRQHandler /* TIM4 */
+ .word I2C1_EV_IRQHandler /* I2C1 Event */
+ .word I2C1_ER_IRQHandler /* I2C1 Error */
+ .word I2C2_EV_IRQHandler /* I2C2 Event */
+ .word I2C2_ER_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
+ .word DFSDM2_IRQHandler /* DFSDM2 Interrupt */
+ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
+ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
+ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
+ .word FMC_IRQHandler /* FMC */
+ .word SDMMC1_IRQHandler /* SDMMC1 */
+ .word TIM5_IRQHandler /* TIM5 */
+ .word SPI3_IRQHandler /* SPI3 */
+ .word UART4_IRQHandler /* UART4 */
+ .word UART5_IRQHandler /* UART5 */
+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
+ .word TIM7_IRQHandler /* TIM7 */
+ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
+ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
+ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
+ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
+ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
+ .word DFSDM1_FLT4_IRQHandler /* DFSDM Filter4 Interrupt */
+ .word DFSDM1_FLT5_IRQHandler /* DFSDM Filter5 Interrupt */
+ .word DFSDM1_FLT6_IRQHandler /* DFSDM Filter6 Interrupt */
+ .word DFSDM1_FLT7_IRQHandler /* DFSDM Filter7 Interrupt */
+ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
+ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
+ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
+ .word USART6_IRQHandler /* USART6 */
+ .word I2C3_EV_IRQHandler /* I2C3 event */
+ .word I2C3_ER_IRQHandler /* I2C3 error */
+ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
+ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
+ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
+ .word OTG_HS_IRQHandler /* USB OTG HS */
+ .word DCMI_PSSI_IRQHandler /* DCMI, PSSI */
+ .word 0 /* Reserved */
+ .word RNG_IRQHandler /* RNG */
+ .word FPU_IRQHandler /* FPU */
+ .word UART7_IRQHandler /* UART7 */
+ .word UART8_IRQHandler /* UART8 */
+ .word SPI4_IRQHandler /* SPI4 */
+ .word SPI5_IRQHandler /* SPI5 */
+ .word SPI6_IRQHandler /* SPI6 */
+ .word SAI1_IRQHandler /* SAI1 */
+ .word LTDC_IRQHandler /* LTDC */
+ .word LTDC_ER_IRQHandler /* LTDC error */
+ .word DMA2D_IRQHandler /* DMA2D */
+ .word SAI2_IRQHandler /* SAI2 */
+ .word OCTOSPI1_IRQHandler /* OCTOSPI1 */
+ .word LPTIM1_IRQHandler /* LPTIM1 */
+ .word CEC_IRQHandler /* HDMI_CEC */
+ .word I2C4_EV_IRQHandler /* I2C4 Event */
+ .word I2C4_ER_IRQHandler /* I2C4 Error */
+ .word SPDIF_RX_IRQHandler /* SPDIF_RX */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
+ .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
+ .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
+ .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
+ .word 0 /* Reserved */
+ .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
+ .word TIM15_IRQHandler /* TIM15 global Interrupt */
+ .word TIM16_IRQHandler /* TIM16 global Interrupt */
+ .word TIM17_IRQHandler /* TIM17 global Interrupt */
+ .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
+ .word MDIOS_IRQHandler /* MDIOS global Interrupt */
+ .word JPEG_IRQHandler /* JPEG global Interrupt */
+ .word MDMA_IRQHandler /* MDMA global Interrupt */
+ .word 0 /* Reserved */
+ .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
+ .word HSEM1_IRQHandler /* HSEM1 global Interrupt */
+ .word 0 /* Reserved */
+ .word DAC2_IRQHandler /* DAC2 global Interrupt */
+ .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
+ .word BDMA2_Channel0_IRQHandler /* BDMA2 Channel 0 global Interrupt */
+ .word BDMA2_Channel1_IRQHandler /* BDMA2 Channel 1 global Interrupt */
+ .word BDMA2_Channel2_IRQHandler /* BDMA2 Channel 2 global Interrupt */
+ .word BDMA2_Channel3_IRQHandler /* BDMA2 Channel 3 global Interrupt */
+ .word BDMA2_Channel4_IRQHandler /* BDMA2 Channel 4 global Interrupt */
+ .word BDMA2_Channel5_IRQHandler /* BDMA2 Channel 5 global Interrupt */
+ .word BDMA2_Channel6_IRQHandler /* BDMA2 Channel 6 global Interrupt */
+ .word BDMA2_Channel7_IRQHandler /* BDMA2 Channel 7 global Interrupt */
+ .word COMP_IRQHandler /* COMP global Interrupt */
+ .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
+ .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
+ .word UART9_IRQHandler /* UART9 global interrupt */
+ .word USART10_IRQHandler /* USART10 global interrupt */
+ .word LPUART1_IRQHandler /* LP UART1 interrupt */
+ .word 0 /* Reserved */
+ .word CRS_IRQHandler /* Clock Recovery Global Interrupt */
+ .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
+ .word 0 /* Reserved */
+ .word DTS_IRQHandler /* DTS */
+ .word 0 /* Reserved */
+ .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
+ .word OCTOSPI2_IRQHandler /* OCTOSPI2 */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word GFXMMU_IRQHandler /* GFXMMU */
+ .word BDMA1_IRQHandler /* BDMA1 */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_PVM_IRQHandler
+ .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+ .weak RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+ .thumb_set RTC_TAMP_STAMP_CSS_LSE_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream0_IRQHandler
+ .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream1_IRQHandler
+ .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream2_IRQHandler
+ .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream3_IRQHandler
+ .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream4_IRQHandler
+ .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream5_IRQHandler
+ .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream6_IRQHandler
+ .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT0_IRQHandler
+ .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT0_IRQHandler
+ .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT1_IRQHandler
+ .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT1_IRQHandler
+ .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak DFSDM2_IRQHandler
+ .thumb_set DFSDM2_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_TIM12_IRQHandler
+ .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_TIM13_IRQHandler
+ .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_TIM14_IRQHandler
+ .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream7_IRQHandler
+ .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+ .weak FMC_IRQHandler
+ .thumb_set FMC_IRQHandler,Default_Handler
+
+ .weak SDMMC1_IRQHandler
+ .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream0_IRQHandler
+ .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream1_IRQHandler
+ .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream2_IRQHandler
+ .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream3_IRQHandler
+ .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream4_IRQHandler
+ .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+ .weak FDCAN_CAL_IRQHandler
+ .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT4_IRQHandler
+ .thumb_set DFSDM1_FLT4_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT5_IRQHandler
+ .thumb_set DFSDM1_FLT5_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT6_IRQHandler
+ .thumb_set DFSDM1_FLT6_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT7_IRQHandler
+ .thumb_set DFSDM1_FLT7_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream5_IRQHandler
+ .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream6_IRQHandler
+ .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream7_IRQHandler
+ .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+ .weak USART6_IRQHandler
+ .thumb_set USART6_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_OUT_IRQHandler
+ .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_IN_IRQHandler
+ .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_HS_WKUP_IRQHandler
+ .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_HS_IRQHandler
+ .thumb_set OTG_HS_IRQHandler,Default_Handler
+
+ .weak DCMI_PSSI_IRQHandler
+ .thumb_set DCMI_PSSI_IRQHandler,Default_Handler
+
+ .weak RNG_IRQHandler
+ .thumb_set RNG_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak UART7_IRQHandler
+ .thumb_set UART7_IRQHandler,Default_Handler
+
+ .weak UART8_IRQHandler
+ .thumb_set UART8_IRQHandler,Default_Handler
+
+ .weak SPI4_IRQHandler
+ .thumb_set SPI4_IRQHandler,Default_Handler
+
+ .weak SPI5_IRQHandler
+ .thumb_set SPI5_IRQHandler,Default_Handler
+
+ .weak SPI6_IRQHandler
+ .thumb_set SPI6_IRQHandler,Default_Handler
+
+ .weak SAI1_IRQHandler
+ .thumb_set SAI1_IRQHandler,Default_Handler
+
+ .weak LTDC_IRQHandler
+ .thumb_set LTDC_IRQHandler,Default_Handler
+
+ .weak LTDC_ER_IRQHandler
+ .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+ .weak DMA2D_IRQHandler
+ .thumb_set DMA2D_IRQHandler,Default_Handler
+
+ .weak SAI2_IRQHandler
+ .thumb_set SAI2_IRQHandler,Default_Handler
+
+ .weak OCTOSPI1_IRQHandler
+ .thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak I2C4_EV_IRQHandler
+ .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+ .weak I2C4_ER_IRQHandler
+ .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+ .weak SPDIF_RX_IRQHandler
+ .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+ .weak DMAMUX1_OVR_IRQHandler
+ .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT0_IRQHandler
+ .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT1_IRQHandler
+ .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT2_IRQHandler
+ .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT3_IRQHandler
+ .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+ .weak SWPMI1_IRQHandler
+ .thumb_set SWPMI1_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak MDIOS_WKUP_IRQHandler
+ .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
+
+ .weak MDIOS_IRQHandler
+ .thumb_set MDIOS_IRQHandler,Default_Handler
+
+ .weak JPEG_IRQHandler
+ .thumb_set JPEG_IRQHandler,Default_Handler
+
+ .weak MDMA_IRQHandler
+ .thumb_set MDMA_IRQHandler,Default_Handler
+
+ .weak SDMMC2_IRQHandler
+ .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+ .weak HSEM1_IRQHandler
+ .thumb_set HSEM1_IRQHandler,Default_Handler
+
+ .weak DAC2_IRQHandler
+ .thumb_set DAC2_IRQHandler,Default_Handler
+
+ .weak DMAMUX2_OVR_IRQHandler
+ .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel0_IRQHandler
+ .thumb_set BDMA2_Channel0_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel1_IRQHandler
+ .thumb_set BDMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel2_IRQHandler
+ .thumb_set BDMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel3_IRQHandler
+ .thumb_set BDMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel4_IRQHandler
+ .thumb_set BDMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel5_IRQHandler
+ .thumb_set BDMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel6_IRQHandler
+ .thumb_set BDMA2_Channel6_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel7_IRQHandler
+ .thumb_set BDMA2_Channel7_IRQHandler,Default_Handler
+
+ .weak COMP_IRQHandler
+ .thumb_set COMP_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak LPTIM4_IRQHandler
+ .thumb_set LPTIM4_IRQHandler,Default_Handler
+
+ .weak LPTIM5_IRQHandler
+ .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+ .weak UART9_IRQHandler
+ .thumb_set UART9_IRQHandler,Default_Handler
+
+ .weak USART10_IRQHandler
+ .thumb_set USART10_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak CRS_IRQHandler
+ .thumb_set CRS_IRQHandler,Default_Handler
+
+ .weak ECC_IRQHandler
+ .thumb_set ECC_IRQHandler,Default_Handler
+
+ .weak DTS_IRQHandler
+ .thumb_set DTS_IRQHandler,Default_Handler
+
+ .weak WAKEUP_PIN_IRQHandler
+ .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+ .weak OCTOSPI2_IRQHandler
+ .thumb_set OCTOSPI2_IRQHandler,Default_Handler
+
+ .weak GFXMMU_IRQHandler
+ .thumb_set GFXMMU_IRQHandler,Default_Handler
+
+ .weak BDMA1_IRQHandler
+ .thumb_set BDMA1_IRQHandler,Default_Handler
+
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7a3xxq.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7a3xxq.s new file mode 100644 index 0000000..6585996 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7a3xxq.s @@ -0,0 +1,742 @@ +/**
+ ******************************************************************************
+ * @file startup_stm32h7a3xxq.s
+ * @author MCD Application Team
+ * @brief STM32H7B3xx Devices vector table for GCC based toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m7
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+ /* External Interrupts */
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word PVD_PVM_IRQHandler /* PVD/PVM through EXTI Line detection */
+ .word RTC_TAMP_STAMP_CSS_LSE_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_IRQHandler /* EXTI Line0 */
+ .word EXTI1_IRQHandler /* EXTI Line1 */
+ .word EXTI2_IRQHandler /* EXTI Line2 */
+ .word EXTI3_IRQHandler /* EXTI Line3 */
+ .word EXTI4_IRQHandler /* EXTI Line4 */
+ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
+ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
+ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
+ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
+ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
+ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
+ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
+ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
+ .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
+ .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
+ .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
+ .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
+ .word EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
+ .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
+ .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM4_IRQHandler /* TIM4 */
+ .word I2C1_EV_IRQHandler /* I2C1 Event */
+ .word I2C1_ER_IRQHandler /* I2C1 Error */
+ .word I2C2_EV_IRQHandler /* I2C2 Event */
+ .word I2C2_ER_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
+ .word DFSDM2_IRQHandler /* DFSDM2 Interrupt */
+ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
+ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
+ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
+ .word FMC_IRQHandler /* FMC */
+ .word SDMMC1_IRQHandler /* SDMMC1 */
+ .word TIM5_IRQHandler /* TIM5 */
+ .word SPI3_IRQHandler /* SPI3 */
+ .word UART4_IRQHandler /* UART4 */
+ .word UART5_IRQHandler /* UART5 */
+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
+ .word TIM7_IRQHandler /* TIM7 */
+ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
+ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
+ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
+ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
+ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
+ .word DFSDM1_FLT4_IRQHandler /* DFSDM Filter4 Interrupt */
+ .word DFSDM1_FLT5_IRQHandler /* DFSDM Filter5 Interrupt */
+ .word DFSDM1_FLT6_IRQHandler /* DFSDM Filter6 Interrupt */
+ .word DFSDM1_FLT7_IRQHandler /* DFSDM Filter7 Interrupt */
+ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
+ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
+ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
+ .word USART6_IRQHandler /* USART6 */
+ .word I2C3_EV_IRQHandler /* I2C3 event */
+ .word I2C3_ER_IRQHandler /* I2C3 error */
+ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
+ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
+ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
+ .word OTG_HS_IRQHandler /* USB OTG HS */
+ .word DCMI_PSSI_IRQHandler /* DCMI, PSSI */
+ .word 0 /* Reserved */
+ .word RNG_IRQHandler /* RNG */
+ .word FPU_IRQHandler /* FPU */
+ .word UART7_IRQHandler /* UART7 */
+ .word UART8_IRQHandler /* UART8 */
+ .word SPI4_IRQHandler /* SPI4 */
+ .word SPI5_IRQHandler /* SPI5 */
+ .word SPI6_IRQHandler /* SPI6 */
+ .word SAI1_IRQHandler /* SAI1 */
+ .word LTDC_IRQHandler /* LTDC */
+ .word LTDC_ER_IRQHandler /* LTDC error */
+ .word DMA2D_IRQHandler /* DMA2D */
+ .word SAI2_IRQHandler /* SAI2 */
+ .word OCTOSPI1_IRQHandler /* OCTOSPI1 */
+ .word LPTIM1_IRQHandler /* LPTIM1 */
+ .word CEC_IRQHandler /* HDMI_CEC */
+ .word I2C4_EV_IRQHandler /* I2C4 Event */
+ .word I2C4_ER_IRQHandler /* I2C4 Error */
+ .word SPDIF_RX_IRQHandler /* SPDIF_RX */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
+ .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
+ .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
+ .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
+ .word 0 /* Reserved */
+ .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
+ .word TIM15_IRQHandler /* TIM15 global Interrupt */
+ .word TIM16_IRQHandler /* TIM16 global Interrupt */
+ .word TIM17_IRQHandler /* TIM17 global Interrupt */
+ .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
+ .word MDIOS_IRQHandler /* MDIOS global Interrupt */
+ .word JPEG_IRQHandler /* JPEG global Interrupt */
+ .word MDMA_IRQHandler /* MDMA global Interrupt */
+ .word 0 /* Reserved */
+ .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
+ .word HSEM1_IRQHandler /* HSEM1 global Interrupt */
+ .word 0 /* Reserved */
+ .word DAC2_IRQHandler /* DAC2 global Interrupt */
+ .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
+ .word BDMA2_Channel0_IRQHandler /* BDMA2 Channel 0 global Interrupt */
+ .word BDMA2_Channel1_IRQHandler /* BDMA2 Channel 1 global Interrupt */
+ .word BDMA2_Channel2_IRQHandler /* BDMA2 Channel 2 global Interrupt */
+ .word BDMA2_Channel3_IRQHandler /* BDMA2 Channel 3 global Interrupt */
+ .word BDMA2_Channel4_IRQHandler /* BDMA2 Channel 4 global Interrupt */
+ .word BDMA2_Channel5_IRQHandler /* BDMA2 Channel 5 global Interrupt */
+ .word BDMA2_Channel6_IRQHandler /* BDMA2 Channel 6 global Interrupt */
+ .word BDMA2_Channel7_IRQHandler /* BDMA2 Channel 7 global Interrupt */
+ .word COMP_IRQHandler /* COMP global Interrupt */
+ .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
+ .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
+ .word UART9_IRQHandler /* UART9 global interrupt */
+ .word USART10_IRQHandler /* USART10 global interrupt */
+ .word LPUART1_IRQHandler /* LP UART1 interrupt */
+ .word 0 /* Reserved */
+ .word CRS_IRQHandler /* Clock Recovery Global Interrupt */
+ .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
+ .word 0 /* Reserved */
+ .word DTS_IRQHandler /* DTS */
+ .word 0 /* Reserved */
+ .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
+ .word OCTOSPI2_IRQHandler /* OCTOSPI2 */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word GFXMMU_IRQHandler /* GFXMMU */
+ .word BDMA1_IRQHandler /* BDMA1 */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_PVM_IRQHandler
+ .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+ .weak RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+ .thumb_set RTC_TAMP_STAMP_CSS_LSE_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream0_IRQHandler
+ .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream1_IRQHandler
+ .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream2_IRQHandler
+ .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream3_IRQHandler
+ .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream4_IRQHandler
+ .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream5_IRQHandler
+ .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream6_IRQHandler
+ .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT0_IRQHandler
+ .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT0_IRQHandler
+ .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT1_IRQHandler
+ .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT1_IRQHandler
+ .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak DFSDM2_IRQHandler
+ .thumb_set DFSDM2_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_TIM12_IRQHandler
+ .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_TIM13_IRQHandler
+ .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_TIM14_IRQHandler
+ .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream7_IRQHandler
+ .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+ .weak FMC_IRQHandler
+ .thumb_set FMC_IRQHandler,Default_Handler
+
+ .weak SDMMC1_IRQHandler
+ .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream0_IRQHandler
+ .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream1_IRQHandler
+ .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream2_IRQHandler
+ .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream3_IRQHandler
+ .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream4_IRQHandler
+ .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+ .weak FDCAN_CAL_IRQHandler
+ .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT4_IRQHandler
+ .thumb_set DFSDM1_FLT4_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT5_IRQHandler
+ .thumb_set DFSDM1_FLT5_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT6_IRQHandler
+ .thumb_set DFSDM1_FLT6_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT7_IRQHandler
+ .thumb_set DFSDM1_FLT7_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream5_IRQHandler
+ .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream6_IRQHandler
+ .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream7_IRQHandler
+ .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+ .weak USART6_IRQHandler
+ .thumb_set USART6_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_OUT_IRQHandler
+ .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_IN_IRQHandler
+ .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_HS_WKUP_IRQHandler
+ .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_HS_IRQHandler
+ .thumb_set OTG_HS_IRQHandler,Default_Handler
+
+ .weak DCMI_PSSI_IRQHandler
+ .thumb_set DCMI_PSSI_IRQHandler,Default_Handler
+
+ .weak RNG_IRQHandler
+ .thumb_set RNG_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak UART7_IRQHandler
+ .thumb_set UART7_IRQHandler,Default_Handler
+
+ .weak UART8_IRQHandler
+ .thumb_set UART8_IRQHandler,Default_Handler
+
+ .weak SPI4_IRQHandler
+ .thumb_set SPI4_IRQHandler,Default_Handler
+
+ .weak SPI5_IRQHandler
+ .thumb_set SPI5_IRQHandler,Default_Handler
+
+ .weak SPI6_IRQHandler
+ .thumb_set SPI6_IRQHandler,Default_Handler
+
+ .weak SAI1_IRQHandler
+ .thumb_set SAI1_IRQHandler,Default_Handler
+
+ .weak LTDC_IRQHandler
+ .thumb_set LTDC_IRQHandler,Default_Handler
+
+ .weak LTDC_ER_IRQHandler
+ .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+ .weak DMA2D_IRQHandler
+ .thumb_set DMA2D_IRQHandler,Default_Handler
+
+ .weak SAI2_IRQHandler
+ .thumb_set SAI2_IRQHandler,Default_Handler
+
+ .weak OCTOSPI1_IRQHandler
+ .thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak I2C4_EV_IRQHandler
+ .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+ .weak I2C4_ER_IRQHandler
+ .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+ .weak SPDIF_RX_IRQHandler
+ .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+ .weak DMAMUX1_OVR_IRQHandler
+ .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT0_IRQHandler
+ .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT1_IRQHandler
+ .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT2_IRQHandler
+ .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT3_IRQHandler
+ .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+ .weak SWPMI1_IRQHandler
+ .thumb_set SWPMI1_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak MDIOS_WKUP_IRQHandler
+ .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
+
+ .weak MDIOS_IRQHandler
+ .thumb_set MDIOS_IRQHandler,Default_Handler
+
+ .weak JPEG_IRQHandler
+ .thumb_set JPEG_IRQHandler,Default_Handler
+
+ .weak MDMA_IRQHandler
+ .thumb_set MDMA_IRQHandler,Default_Handler
+
+ .weak SDMMC2_IRQHandler
+ .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+ .weak HSEM1_IRQHandler
+ .thumb_set HSEM1_IRQHandler,Default_Handler
+
+ .weak DAC2_IRQHandler
+ .thumb_set DAC2_IRQHandler,Default_Handler
+
+ .weak DMAMUX2_OVR_IRQHandler
+ .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel0_IRQHandler
+ .thumb_set BDMA2_Channel0_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel1_IRQHandler
+ .thumb_set BDMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel2_IRQHandler
+ .thumb_set BDMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel3_IRQHandler
+ .thumb_set BDMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel4_IRQHandler
+ .thumb_set BDMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel5_IRQHandler
+ .thumb_set BDMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel6_IRQHandler
+ .thumb_set BDMA2_Channel6_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel7_IRQHandler
+ .thumb_set BDMA2_Channel7_IRQHandler,Default_Handler
+
+ .weak COMP_IRQHandler
+ .thumb_set COMP_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak LPTIM4_IRQHandler
+ .thumb_set LPTIM4_IRQHandler,Default_Handler
+
+ .weak LPTIM5_IRQHandler
+ .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+ .weak UART9_IRQHandler
+ .thumb_set UART9_IRQHandler,Default_Handler
+
+ .weak USART10_IRQHandler
+ .thumb_set USART10_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak CRS_IRQHandler
+ .thumb_set CRS_IRQHandler,Default_Handler
+
+ .weak ECC_IRQHandler
+ .thumb_set ECC_IRQHandler,Default_Handler
+
+ .weak DTS_IRQHandler
+ .thumb_set DTS_IRQHandler,Default_Handler
+
+ .weak WAKEUP_PIN_IRQHandler
+ .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+ .weak OCTOSPI2_IRQHandler
+ .thumb_set OCTOSPI2_IRQHandler,Default_Handler
+
+ .weak GFXMMU_IRQHandler
+ .thumb_set GFXMMU_IRQHandler,Default_Handler
+
+ .weak BDMA1_IRQHandler
+ .thumb_set BDMA1_IRQHandler,Default_Handler
+
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b0xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b0xx.s new file mode 100644 index 0000000..c12203e --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b0xx.s @@ -0,0 +1,751 @@ +/**
+ ******************************************************************************
+ * @file startup_stm32h7b0xx.s
+ * @author MCD Application Team
+ * @brief STM32H7B0xx Devices vector table for GCC based toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m7
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+ /* External Interrupts */
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word PVD_PVM_IRQHandler /* PVD/PVM through EXTI Line detection */
+ .word RTC_TAMP_STAMP_CSS_LSE_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_IRQHandler /* EXTI Line0 */
+ .word EXTI1_IRQHandler /* EXTI Line1 */
+ .word EXTI2_IRQHandler /* EXTI Line2 */
+ .word EXTI3_IRQHandler /* EXTI Line3 */
+ .word EXTI4_IRQHandler /* EXTI Line4 */
+ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
+ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
+ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
+ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
+ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
+ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
+ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
+ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
+ .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
+ .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
+ .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
+ .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
+ .word EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
+ .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
+ .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM4_IRQHandler /* TIM4 */
+ .word I2C1_EV_IRQHandler /* I2C1 Event */
+ .word I2C1_ER_IRQHandler /* I2C1 Error */
+ .word I2C2_EV_IRQHandler /* I2C2 Event */
+ .word I2C2_ER_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
+ .word DFSDM2_IRQHandler /* DFSDM2 Interrupt */
+ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
+ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
+ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
+ .word FMC_IRQHandler /* FMC */
+ .word SDMMC1_IRQHandler /* SDMMC1 */
+ .word TIM5_IRQHandler /* TIM5 */
+ .word SPI3_IRQHandler /* SPI3 */
+ .word UART4_IRQHandler /* UART4 */
+ .word UART5_IRQHandler /* UART5 */
+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
+ .word TIM7_IRQHandler /* TIM7 */
+ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
+ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
+ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
+ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
+ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
+ .word DFSDM1_FLT4_IRQHandler /* DFSDM Filter4 Interrupt */
+ .word DFSDM1_FLT5_IRQHandler /* DFSDM Filter5 Interrupt */
+ .word DFSDM1_FLT6_IRQHandler /* DFSDM Filter6 Interrupt */
+ .word DFSDM1_FLT7_IRQHandler /* DFSDM Filter7 Interrupt */
+ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
+ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
+ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
+ .word USART6_IRQHandler /* USART6 */
+ .word I2C3_EV_IRQHandler /* I2C3 event */
+ .word I2C3_ER_IRQHandler /* I2C3 error */
+ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
+ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
+ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
+ .word OTG_HS_IRQHandler /* USB OTG HS */
+ .word DCMI_PSSI_IRQHandler /* DCMI, PSSI */
+ .word CRYP_IRQHandler /* CRYP crypto global interrupt */
+ .word HASH_RNG_IRQHandler /* RNG, HASH */
+ .word FPU_IRQHandler /* FPU */
+ .word UART7_IRQHandler /* UART7 */
+ .word UART8_IRQHandler /* UART8 */
+ .word SPI4_IRQHandler /* SPI4 */
+ .word SPI5_IRQHandler /* SPI5 */
+ .word SPI6_IRQHandler /* SPI6 */
+ .word SAI1_IRQHandler /* SAI1 */
+ .word LTDC_IRQHandler /* LTDC */
+ .word LTDC_ER_IRQHandler /* LTDC error */
+ .word DMA2D_IRQHandler /* DMA2D */
+ .word SAI2_IRQHandler /* SAI2 */
+ .word OCTOSPI1_IRQHandler /* OCTOSPI1 */
+ .word LPTIM1_IRQHandler /* LPTIM1 */
+ .word CEC_IRQHandler /* HDMI_CEC */
+ .word I2C4_EV_IRQHandler /* I2C4 Event */
+ .word I2C4_ER_IRQHandler /* I2C4 Error */
+ .word SPDIF_RX_IRQHandler /* SPDIF_RX */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
+ .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
+ .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
+ .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
+ .word 0 /* Reserved */
+ .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
+ .word TIM15_IRQHandler /* TIM15 global Interrupt */
+ .word TIM16_IRQHandler /* TIM16 global Interrupt */
+ .word TIM17_IRQHandler /* TIM17 global Interrupt */
+ .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
+ .word MDIOS_IRQHandler /* MDIOS global Interrupt */
+ .word JPEG_IRQHandler /* JPEG global Interrupt */
+ .word MDMA_IRQHandler /* MDMA global Interrupt */
+ .word 0 /* Reserved */
+ .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
+ .word HSEM1_IRQHandler /* HSEM1 global Interrupt */
+ .word 0 /* Reserved */
+ .word DAC2_IRQHandler /* DAC2 global Interrupt */
+ .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
+ .word BDMA2_Channel0_IRQHandler /* BDMA2 Channel 0 global Interrupt */
+ .word BDMA2_Channel1_IRQHandler /* BDMA2 Channel 1 global Interrupt */
+ .word BDMA2_Channel2_IRQHandler /* BDMA2 Channel 2 global Interrupt */
+ .word BDMA2_Channel3_IRQHandler /* BDMA2 Channel 3 global Interrupt */
+ .word BDMA2_Channel4_IRQHandler /* BDMA2 Channel 4 global Interrupt */
+ .word BDMA2_Channel5_IRQHandler /* BDMA2 Channel 5 global Interrupt */
+ .word BDMA2_Channel6_IRQHandler /* BDMA2 Channel 6 global Interrupt */
+ .word BDMA2_Channel7_IRQHandler /* BDMA2 Channel 7 global Interrupt */
+ .word COMP_IRQHandler /* COMP global Interrupt */
+ .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
+ .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
+ .word UART9_IRQHandler /* UART9 global interrupt */
+ .word USART10_IRQHandler /* USART10 global interrupt */
+ .word LPUART1_IRQHandler /* LP UART1 interrupt */
+ .word 0 /* Reserved */
+ .word CRS_IRQHandler /* Clock Recovery Global Interrupt */
+ .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
+ .word 0 /* Reserved */
+ .word DTS_IRQHandler /* DTS */
+ .word 0 /* Reserved */
+ .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
+ .word OCTOSPI2_IRQHandler /* OCTOSPI2 */
+ .word OTFDEC1_IRQHandler /* OTFDEC1 */
+ .word OTFDEC2_IRQHandler /* OTFDEC2 */
+ .word GFXMMU_IRQHandler /* GFXMMU */
+ .word BDMA1_IRQHandler /* BDMA1 */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_PVM_IRQHandler
+ .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+ .weak RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+ .thumb_set RTC_TAMP_STAMP_CSS_LSE_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream0_IRQHandler
+ .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream1_IRQHandler
+ .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream2_IRQHandler
+ .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream3_IRQHandler
+ .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream4_IRQHandler
+ .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream5_IRQHandler
+ .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream6_IRQHandler
+ .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT0_IRQHandler
+ .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT0_IRQHandler
+ .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT1_IRQHandler
+ .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT1_IRQHandler
+ .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak DFSDM2_IRQHandler
+ .thumb_set DFSDM2_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_TIM12_IRQHandler
+ .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_TIM13_IRQHandler
+ .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_TIM14_IRQHandler
+ .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream7_IRQHandler
+ .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+ .weak FMC_IRQHandler
+ .thumb_set FMC_IRQHandler,Default_Handler
+
+ .weak SDMMC1_IRQHandler
+ .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream0_IRQHandler
+ .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream1_IRQHandler
+ .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream2_IRQHandler
+ .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream3_IRQHandler
+ .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream4_IRQHandler
+ .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+ .weak FDCAN_CAL_IRQHandler
+ .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT4_IRQHandler
+ .thumb_set DFSDM1_FLT4_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT5_IRQHandler
+ .thumb_set DFSDM1_FLT5_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT6_IRQHandler
+ .thumb_set DFSDM1_FLT6_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT7_IRQHandler
+ .thumb_set DFSDM1_FLT7_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream5_IRQHandler
+ .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream6_IRQHandler
+ .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream7_IRQHandler
+ .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+ .weak USART6_IRQHandler
+ .thumb_set USART6_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_OUT_IRQHandler
+ .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_IN_IRQHandler
+ .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_HS_WKUP_IRQHandler
+ .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_HS_IRQHandler
+ .thumb_set OTG_HS_IRQHandler,Default_Handler
+
+ .weak DCMI_PSSI_IRQHandler
+ .thumb_set DCMI_PSSI_IRQHandler,Default_Handler
+
+ .weak CRYP_IRQHandler
+ .thumb_set CRYP_IRQHandler,Default_Handler
+
+ .weak HASH_RNG_IRQHandler
+ .thumb_set HASH_RNG_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak UART7_IRQHandler
+ .thumb_set UART7_IRQHandler,Default_Handler
+
+ .weak UART8_IRQHandler
+ .thumb_set UART8_IRQHandler,Default_Handler
+
+ .weak SPI4_IRQHandler
+ .thumb_set SPI4_IRQHandler,Default_Handler
+
+ .weak SPI5_IRQHandler
+ .thumb_set SPI5_IRQHandler,Default_Handler
+
+ .weak SPI6_IRQHandler
+ .thumb_set SPI6_IRQHandler,Default_Handler
+
+ .weak SAI1_IRQHandler
+ .thumb_set SAI1_IRQHandler,Default_Handler
+
+ .weak LTDC_IRQHandler
+ .thumb_set LTDC_IRQHandler,Default_Handler
+
+ .weak LTDC_ER_IRQHandler
+ .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+ .weak DMA2D_IRQHandler
+ .thumb_set DMA2D_IRQHandler,Default_Handler
+
+ .weak SAI2_IRQHandler
+ .thumb_set SAI2_IRQHandler,Default_Handler
+
+ .weak OCTOSPI1_IRQHandler
+ .thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak I2C4_EV_IRQHandler
+ .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+ .weak I2C4_ER_IRQHandler
+ .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+ .weak SPDIF_RX_IRQHandler
+ .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+ .weak DMAMUX1_OVR_IRQHandler
+ .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT0_IRQHandler
+ .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT1_IRQHandler
+ .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT2_IRQHandler
+ .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT3_IRQHandler
+ .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+ .weak SWPMI1_IRQHandler
+ .thumb_set SWPMI1_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak MDIOS_WKUP_IRQHandler
+ .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
+
+ .weak MDIOS_IRQHandler
+ .thumb_set MDIOS_IRQHandler,Default_Handler
+
+ .weak JPEG_IRQHandler
+ .thumb_set JPEG_IRQHandler,Default_Handler
+
+ .weak MDMA_IRQHandler
+ .thumb_set MDMA_IRQHandler,Default_Handler
+
+ .weak SDMMC2_IRQHandler
+ .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+ .weak HSEM1_IRQHandler
+ .thumb_set HSEM1_IRQHandler,Default_Handler
+
+ .weak DAC2_IRQHandler
+ .thumb_set DAC2_IRQHandler,Default_Handler
+
+ .weak DMAMUX2_OVR_IRQHandler
+ .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel0_IRQHandler
+ .thumb_set BDMA2_Channel0_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel1_IRQHandler
+ .thumb_set BDMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel2_IRQHandler
+ .thumb_set BDMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel3_IRQHandler
+ .thumb_set BDMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel4_IRQHandler
+ .thumb_set BDMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel5_IRQHandler
+ .thumb_set BDMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel6_IRQHandler
+ .thumb_set BDMA2_Channel6_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel7_IRQHandler
+ .thumb_set BDMA2_Channel7_IRQHandler,Default_Handler
+
+ .weak COMP_IRQHandler
+ .thumb_set COMP_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak LPTIM4_IRQHandler
+ .thumb_set LPTIM4_IRQHandler,Default_Handler
+
+ .weak LPTIM5_IRQHandler
+ .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+ .weak UART9_IRQHandler
+ .thumb_set UART9_IRQHandler,Default_Handler
+
+ .weak USART10_IRQHandler
+ .thumb_set USART10_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak CRS_IRQHandler
+ .thumb_set CRS_IRQHandler,Default_Handler
+
+ .weak ECC_IRQHandler
+ .thumb_set ECC_IRQHandler,Default_Handler
+
+ .weak DTS_IRQHandler
+ .thumb_set DTS_IRQHandler,Default_Handler
+
+ .weak WAKEUP_PIN_IRQHandler
+ .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+ .weak OCTOSPI2_IRQHandler
+ .thumb_set OCTOSPI2_IRQHandler,Default_Handler
+
+ .weak OTFDEC1_IRQHandler
+ .thumb_set OTFDEC1_IRQHandler,Default_Handler
+
+ .weak OTFDEC2_IRQHandler
+ .thumb_set OTFDEC2_IRQHandler,Default_Handler
+
+ .weak GFXMMU_IRQHandler
+ .thumb_set GFXMMU_IRQHandler,Default_Handler
+
+ .weak BDMA1_IRQHandler
+ .thumb_set BDMA1_IRQHandler,Default_Handler
+
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b0xxq.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b0xxq.s new file mode 100644 index 0000000..256d145 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b0xxq.s @@ -0,0 +1,751 @@ +/**
+ ******************************************************************************
+ * @file startup_stm32h7b0xxq.s
+ * @author MCD Application Team
+ * @brief STM32H7B0xx Devices vector table for GCC based toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m7
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+ /* External Interrupts */
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word PVD_PVM_IRQHandler /* PVD/PVM through EXTI Line detection */
+ .word RTC_TAMP_STAMP_CSS_LSE_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_IRQHandler /* EXTI Line0 */
+ .word EXTI1_IRQHandler /* EXTI Line1 */
+ .word EXTI2_IRQHandler /* EXTI Line2 */
+ .word EXTI3_IRQHandler /* EXTI Line3 */
+ .word EXTI4_IRQHandler /* EXTI Line4 */
+ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
+ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
+ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
+ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
+ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
+ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
+ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
+ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
+ .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
+ .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
+ .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
+ .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
+ .word EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
+ .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
+ .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM4_IRQHandler /* TIM4 */
+ .word I2C1_EV_IRQHandler /* I2C1 Event */
+ .word I2C1_ER_IRQHandler /* I2C1 Error */
+ .word I2C2_EV_IRQHandler /* I2C2 Event */
+ .word I2C2_ER_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
+ .word DFSDM2_IRQHandler /* DFSDM2 Interrupt */
+ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
+ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
+ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
+ .word FMC_IRQHandler /* FMC */
+ .word SDMMC1_IRQHandler /* SDMMC1 */
+ .word TIM5_IRQHandler /* TIM5 */
+ .word SPI3_IRQHandler /* SPI3 */
+ .word UART4_IRQHandler /* UART4 */
+ .word UART5_IRQHandler /* UART5 */
+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
+ .word TIM7_IRQHandler /* TIM7 */
+ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
+ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
+ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
+ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
+ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
+ .word DFSDM1_FLT4_IRQHandler /* DFSDM Filter4 Interrupt */
+ .word DFSDM1_FLT5_IRQHandler /* DFSDM Filter5 Interrupt */
+ .word DFSDM1_FLT6_IRQHandler /* DFSDM Filter6 Interrupt */
+ .word DFSDM1_FLT7_IRQHandler /* DFSDM Filter7 Interrupt */
+ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
+ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
+ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
+ .word USART6_IRQHandler /* USART6 */
+ .word I2C3_EV_IRQHandler /* I2C3 event */
+ .word I2C3_ER_IRQHandler /* I2C3 error */
+ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
+ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
+ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
+ .word OTG_HS_IRQHandler /* USB OTG HS */
+ .word DCMI_PSSI_IRQHandler /* DCMI, PSSI */
+ .word CRYP_IRQHandler /* CRYP crypto global interrupt */
+ .word HASH_RNG_IRQHandler /* RNG, HASH */
+ .word FPU_IRQHandler /* FPU */
+ .word UART7_IRQHandler /* UART7 */
+ .word UART8_IRQHandler /* UART8 */
+ .word SPI4_IRQHandler /* SPI4 */
+ .word SPI5_IRQHandler /* SPI5 */
+ .word SPI6_IRQHandler /* SPI6 */
+ .word SAI1_IRQHandler /* SAI1 */
+ .word LTDC_IRQHandler /* LTDC */
+ .word LTDC_ER_IRQHandler /* LTDC error */
+ .word DMA2D_IRQHandler /* DMA2D */
+ .word SAI2_IRQHandler /* SAI2 */
+ .word OCTOSPI1_IRQHandler /* OCTOSPI1 */
+ .word LPTIM1_IRQHandler /* LPTIM1 */
+ .word CEC_IRQHandler /* HDMI_CEC */
+ .word I2C4_EV_IRQHandler /* I2C4 Event */
+ .word I2C4_ER_IRQHandler /* I2C4 Error */
+ .word SPDIF_RX_IRQHandler /* SPDIF_RX */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
+ .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
+ .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
+ .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
+ .word 0 /* Reserved */
+ .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
+ .word TIM15_IRQHandler /* TIM15 global Interrupt */
+ .word TIM16_IRQHandler /* TIM16 global Interrupt */
+ .word TIM17_IRQHandler /* TIM17 global Interrupt */
+ .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
+ .word MDIOS_IRQHandler /* MDIOS global Interrupt */
+ .word JPEG_IRQHandler /* JPEG global Interrupt */
+ .word MDMA_IRQHandler /* MDMA global Interrupt */
+ .word 0 /* Reserved */
+ .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
+ .word HSEM1_IRQHandler /* HSEM1 global Interrupt */
+ .word 0 /* Reserved */
+ .word DAC2_IRQHandler /* DAC2 global Interrupt */
+ .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
+ .word BDMA2_Channel0_IRQHandler /* BDMA2 Channel 0 global Interrupt */
+ .word BDMA2_Channel1_IRQHandler /* BDMA2 Channel 1 global Interrupt */
+ .word BDMA2_Channel2_IRQHandler /* BDMA2 Channel 2 global Interrupt */
+ .word BDMA2_Channel3_IRQHandler /* BDMA2 Channel 3 global Interrupt */
+ .word BDMA2_Channel4_IRQHandler /* BDMA2 Channel 4 global Interrupt */
+ .word BDMA2_Channel5_IRQHandler /* BDMA2 Channel 5 global Interrupt */
+ .word BDMA2_Channel6_IRQHandler /* BDMA2 Channel 6 global Interrupt */
+ .word BDMA2_Channel7_IRQHandler /* BDMA2 Channel 7 global Interrupt */
+ .word COMP_IRQHandler /* COMP global Interrupt */
+ .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
+ .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
+ .word UART9_IRQHandler /* UART9 global interrupt */
+ .word USART10_IRQHandler /* USART10 global interrupt */
+ .word LPUART1_IRQHandler /* LP UART1 interrupt */
+ .word 0 /* Reserved */
+ .word CRS_IRQHandler /* Clock Recovery Global Interrupt */
+ .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
+ .word 0 /* Reserved */
+ .word DTS_IRQHandler /* DTS */
+ .word 0 /* Reserved */
+ .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
+ .word OCTOSPI2_IRQHandler /* OCTOSPI2 */
+ .word OTFDEC1_IRQHandler /* OTFDEC1 */
+ .word OTFDEC2_IRQHandler /* OTFDEC2 */
+ .word GFXMMU_IRQHandler /* GFXMMU */
+ .word BDMA1_IRQHandler /* BDMA1 */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_PVM_IRQHandler
+ .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+ .weak RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+ .thumb_set RTC_TAMP_STAMP_CSS_LSE_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream0_IRQHandler
+ .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream1_IRQHandler
+ .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream2_IRQHandler
+ .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream3_IRQHandler
+ .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream4_IRQHandler
+ .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream5_IRQHandler
+ .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream6_IRQHandler
+ .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT0_IRQHandler
+ .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT0_IRQHandler
+ .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT1_IRQHandler
+ .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT1_IRQHandler
+ .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak DFSDM2_IRQHandler
+ .thumb_set DFSDM2_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_TIM12_IRQHandler
+ .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_TIM13_IRQHandler
+ .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_TIM14_IRQHandler
+ .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream7_IRQHandler
+ .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+ .weak FMC_IRQHandler
+ .thumb_set FMC_IRQHandler,Default_Handler
+
+ .weak SDMMC1_IRQHandler
+ .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream0_IRQHandler
+ .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream1_IRQHandler
+ .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream2_IRQHandler
+ .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream3_IRQHandler
+ .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream4_IRQHandler
+ .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+ .weak FDCAN_CAL_IRQHandler
+ .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT4_IRQHandler
+ .thumb_set DFSDM1_FLT4_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT5_IRQHandler
+ .thumb_set DFSDM1_FLT5_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT6_IRQHandler
+ .thumb_set DFSDM1_FLT6_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT7_IRQHandler
+ .thumb_set DFSDM1_FLT7_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream5_IRQHandler
+ .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream6_IRQHandler
+ .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream7_IRQHandler
+ .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+ .weak USART6_IRQHandler
+ .thumb_set USART6_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_OUT_IRQHandler
+ .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_IN_IRQHandler
+ .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_HS_WKUP_IRQHandler
+ .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_HS_IRQHandler
+ .thumb_set OTG_HS_IRQHandler,Default_Handler
+
+ .weak DCMI_PSSI_IRQHandler
+ .thumb_set DCMI_PSSI_IRQHandler,Default_Handler
+
+ .weak CRYP_IRQHandler
+ .thumb_set CRYP_IRQHandler,Default_Handler
+
+ .weak HASH_RNG_IRQHandler
+ .thumb_set HASH_RNG_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak UART7_IRQHandler
+ .thumb_set UART7_IRQHandler,Default_Handler
+
+ .weak UART8_IRQHandler
+ .thumb_set UART8_IRQHandler,Default_Handler
+
+ .weak SPI4_IRQHandler
+ .thumb_set SPI4_IRQHandler,Default_Handler
+
+ .weak SPI5_IRQHandler
+ .thumb_set SPI5_IRQHandler,Default_Handler
+
+ .weak SPI6_IRQHandler
+ .thumb_set SPI6_IRQHandler,Default_Handler
+
+ .weak SAI1_IRQHandler
+ .thumb_set SAI1_IRQHandler,Default_Handler
+
+ .weak LTDC_IRQHandler
+ .thumb_set LTDC_IRQHandler,Default_Handler
+
+ .weak LTDC_ER_IRQHandler
+ .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+ .weak DMA2D_IRQHandler
+ .thumb_set DMA2D_IRQHandler,Default_Handler
+
+ .weak SAI2_IRQHandler
+ .thumb_set SAI2_IRQHandler,Default_Handler
+
+ .weak OCTOSPI1_IRQHandler
+ .thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak I2C4_EV_IRQHandler
+ .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+ .weak I2C4_ER_IRQHandler
+ .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+ .weak SPDIF_RX_IRQHandler
+ .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+ .weak DMAMUX1_OVR_IRQHandler
+ .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT0_IRQHandler
+ .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT1_IRQHandler
+ .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT2_IRQHandler
+ .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT3_IRQHandler
+ .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+ .weak SWPMI1_IRQHandler
+ .thumb_set SWPMI1_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak MDIOS_WKUP_IRQHandler
+ .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
+
+ .weak MDIOS_IRQHandler
+ .thumb_set MDIOS_IRQHandler,Default_Handler
+
+ .weak JPEG_IRQHandler
+ .thumb_set JPEG_IRQHandler,Default_Handler
+
+ .weak MDMA_IRQHandler
+ .thumb_set MDMA_IRQHandler,Default_Handler
+
+ .weak SDMMC2_IRQHandler
+ .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+ .weak HSEM1_IRQHandler
+ .thumb_set HSEM1_IRQHandler,Default_Handler
+
+ .weak DAC2_IRQHandler
+ .thumb_set DAC2_IRQHandler,Default_Handler
+
+ .weak DMAMUX2_OVR_IRQHandler
+ .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel0_IRQHandler
+ .thumb_set BDMA2_Channel0_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel1_IRQHandler
+ .thumb_set BDMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel2_IRQHandler
+ .thumb_set BDMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel3_IRQHandler
+ .thumb_set BDMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel4_IRQHandler
+ .thumb_set BDMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel5_IRQHandler
+ .thumb_set BDMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel6_IRQHandler
+ .thumb_set BDMA2_Channel6_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel7_IRQHandler
+ .thumb_set BDMA2_Channel7_IRQHandler,Default_Handler
+
+ .weak COMP_IRQHandler
+ .thumb_set COMP_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak LPTIM4_IRQHandler
+ .thumb_set LPTIM4_IRQHandler,Default_Handler
+
+ .weak LPTIM5_IRQHandler
+ .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+ .weak UART9_IRQHandler
+ .thumb_set UART9_IRQHandler,Default_Handler
+
+ .weak USART10_IRQHandler
+ .thumb_set USART10_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak CRS_IRQHandler
+ .thumb_set CRS_IRQHandler,Default_Handler
+
+ .weak ECC_IRQHandler
+ .thumb_set ECC_IRQHandler,Default_Handler
+
+ .weak DTS_IRQHandler
+ .thumb_set DTS_IRQHandler,Default_Handler
+
+ .weak WAKEUP_PIN_IRQHandler
+ .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+ .weak OCTOSPI2_IRQHandler
+ .thumb_set OCTOSPI2_IRQHandler,Default_Handler
+
+ .weak OTFDEC1_IRQHandler
+ .thumb_set OTFDEC1_IRQHandler,Default_Handler
+
+ .weak OTFDEC2_IRQHandler
+ .thumb_set OTFDEC2_IRQHandler,Default_Handler
+
+ .weak GFXMMU_IRQHandler
+ .thumb_set GFXMMU_IRQHandler,Default_Handler
+
+ .weak BDMA1_IRQHandler
+ .thumb_set BDMA1_IRQHandler,Default_Handler
+
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b3xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b3xx.s new file mode 100644 index 0000000..d6ed8ea --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b3xx.s @@ -0,0 +1,751 @@ +/**
+ ******************************************************************************
+ * @file startup_stm32h7b3xx.s
+ * @author MCD Application Team
+ * @brief STM32H7B3xx Devices vector table for GCC based toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m7
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+ /* External Interrupts */
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word PVD_PVM_IRQHandler /* PVD/PVM through EXTI Line detection */
+ .word RTC_TAMP_STAMP_CSS_LSE_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_IRQHandler /* EXTI Line0 */
+ .word EXTI1_IRQHandler /* EXTI Line1 */
+ .word EXTI2_IRQHandler /* EXTI Line2 */
+ .word EXTI3_IRQHandler /* EXTI Line3 */
+ .word EXTI4_IRQHandler /* EXTI Line4 */
+ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
+ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
+ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
+ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
+ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
+ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
+ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
+ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
+ .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
+ .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
+ .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
+ .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
+ .word EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
+ .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
+ .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM4_IRQHandler /* TIM4 */
+ .word I2C1_EV_IRQHandler /* I2C1 Event */
+ .word I2C1_ER_IRQHandler /* I2C1 Error */
+ .word I2C2_EV_IRQHandler /* I2C2 Event */
+ .word I2C2_ER_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
+ .word DFSDM2_IRQHandler /* DFSDM2 Interrupt */
+ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
+ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
+ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
+ .word FMC_IRQHandler /* FMC */
+ .word SDMMC1_IRQHandler /* SDMMC1 */
+ .word TIM5_IRQHandler /* TIM5 */
+ .word SPI3_IRQHandler /* SPI3 */
+ .word UART4_IRQHandler /* UART4 */
+ .word UART5_IRQHandler /* UART5 */
+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
+ .word TIM7_IRQHandler /* TIM7 */
+ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
+ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
+ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
+ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
+ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
+ .word DFSDM1_FLT4_IRQHandler /* DFSDM Filter4 Interrupt */
+ .word DFSDM1_FLT5_IRQHandler /* DFSDM Filter5 Interrupt */
+ .word DFSDM1_FLT6_IRQHandler /* DFSDM Filter6 Interrupt */
+ .word DFSDM1_FLT7_IRQHandler /* DFSDM Filter7 Interrupt */
+ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
+ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
+ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
+ .word USART6_IRQHandler /* USART6 */
+ .word I2C3_EV_IRQHandler /* I2C3 event */
+ .word I2C3_ER_IRQHandler /* I2C3 error */
+ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
+ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
+ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
+ .word OTG_HS_IRQHandler /* USB OTG HS */
+ .word DCMI_PSSI_IRQHandler /* DCMI, PSSI */
+ .word CRYP_IRQHandler /* CRYP crypto global interrupt */
+ .word HASH_RNG_IRQHandler /* RNG, HASH */
+ .word FPU_IRQHandler /* FPU */
+ .word UART7_IRQHandler /* UART7 */
+ .word UART8_IRQHandler /* UART8 */
+ .word SPI4_IRQHandler /* SPI4 */
+ .word SPI5_IRQHandler /* SPI5 */
+ .word SPI6_IRQHandler /* SPI6 */
+ .word SAI1_IRQHandler /* SAI1 */
+ .word LTDC_IRQHandler /* LTDC */
+ .word LTDC_ER_IRQHandler /* LTDC error */
+ .word DMA2D_IRQHandler /* DMA2D */
+ .word SAI2_IRQHandler /* SAI2 */
+ .word OCTOSPI1_IRQHandler /* OCTOSPI1 */
+ .word LPTIM1_IRQHandler /* LPTIM1 */
+ .word CEC_IRQHandler /* HDMI_CEC */
+ .word I2C4_EV_IRQHandler /* I2C4 Event */
+ .word I2C4_ER_IRQHandler /* I2C4 Error */
+ .word SPDIF_RX_IRQHandler /* SPDIF_RX */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
+ .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
+ .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
+ .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
+ .word 0 /* Reserved */
+ .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
+ .word TIM15_IRQHandler /* TIM15 global Interrupt */
+ .word TIM16_IRQHandler /* TIM16 global Interrupt */
+ .word TIM17_IRQHandler /* TIM17 global Interrupt */
+ .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
+ .word MDIOS_IRQHandler /* MDIOS global Interrupt */
+ .word JPEG_IRQHandler /* JPEG global Interrupt */
+ .word MDMA_IRQHandler /* MDMA global Interrupt */
+ .word 0 /* Reserved */
+ .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
+ .word HSEM1_IRQHandler /* HSEM1 global Interrupt */
+ .word 0 /* Reserved */
+ .word DAC2_IRQHandler /* DAC2 global Interrupt */
+ .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
+ .word BDMA2_Channel0_IRQHandler /* BDMA2 Channel 0 global Interrupt */
+ .word BDMA2_Channel1_IRQHandler /* BDMA2 Channel 1 global Interrupt */
+ .word BDMA2_Channel2_IRQHandler /* BDMA2 Channel 2 global Interrupt */
+ .word BDMA2_Channel3_IRQHandler /* BDMA2 Channel 3 global Interrupt */
+ .word BDMA2_Channel4_IRQHandler /* BDMA2 Channel 4 global Interrupt */
+ .word BDMA2_Channel5_IRQHandler /* BDMA2 Channel 5 global Interrupt */
+ .word BDMA2_Channel6_IRQHandler /* BDMA2 Channel 6 global Interrupt */
+ .word BDMA2_Channel7_IRQHandler /* BDMA2 Channel 7 global Interrupt */
+ .word COMP_IRQHandler /* COMP global Interrupt */
+ .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
+ .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
+ .word UART9_IRQHandler /* UART9 global interrupt */
+ .word USART10_IRQHandler /* USART10 global interrupt */
+ .word LPUART1_IRQHandler /* LP UART1 interrupt */
+ .word 0 /* Reserved */
+ .word CRS_IRQHandler /* Clock Recovery Global Interrupt */
+ .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
+ .word 0 /* Reserved */
+ .word DTS_IRQHandler /* DTS */
+ .word 0 /* Reserved */
+ .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
+ .word OCTOSPI2_IRQHandler /* OCTOSPI2 */
+ .word OTFDEC1_IRQHandler /* OTFDEC1 */
+ .word OTFDEC2_IRQHandler /* OTFDEC2 */
+ .word GFXMMU_IRQHandler /* GFXMMU */
+ .word BDMA1_IRQHandler /* BDMA1 */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_PVM_IRQHandler
+ .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+ .weak RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+ .thumb_set RTC_TAMP_STAMP_CSS_LSE_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream0_IRQHandler
+ .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream1_IRQHandler
+ .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream2_IRQHandler
+ .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream3_IRQHandler
+ .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream4_IRQHandler
+ .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream5_IRQHandler
+ .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream6_IRQHandler
+ .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT0_IRQHandler
+ .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT0_IRQHandler
+ .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT1_IRQHandler
+ .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT1_IRQHandler
+ .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak DFSDM2_IRQHandler
+ .thumb_set DFSDM2_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_TIM12_IRQHandler
+ .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_TIM13_IRQHandler
+ .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_TIM14_IRQHandler
+ .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream7_IRQHandler
+ .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+ .weak FMC_IRQHandler
+ .thumb_set FMC_IRQHandler,Default_Handler
+
+ .weak SDMMC1_IRQHandler
+ .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream0_IRQHandler
+ .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream1_IRQHandler
+ .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream2_IRQHandler
+ .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream3_IRQHandler
+ .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream4_IRQHandler
+ .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+ .weak FDCAN_CAL_IRQHandler
+ .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT4_IRQHandler
+ .thumb_set DFSDM1_FLT4_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT5_IRQHandler
+ .thumb_set DFSDM1_FLT5_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT6_IRQHandler
+ .thumb_set DFSDM1_FLT6_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT7_IRQHandler
+ .thumb_set DFSDM1_FLT7_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream5_IRQHandler
+ .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream6_IRQHandler
+ .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream7_IRQHandler
+ .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+ .weak USART6_IRQHandler
+ .thumb_set USART6_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_OUT_IRQHandler
+ .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_IN_IRQHandler
+ .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_HS_WKUP_IRQHandler
+ .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_HS_IRQHandler
+ .thumb_set OTG_HS_IRQHandler,Default_Handler
+
+ .weak DCMI_PSSI_IRQHandler
+ .thumb_set DCMI_PSSI_IRQHandler,Default_Handler
+
+ .weak CRYP_IRQHandler
+ .thumb_set CRYP_IRQHandler,Default_Handler
+
+ .weak HASH_RNG_IRQHandler
+ .thumb_set HASH_RNG_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak UART7_IRQHandler
+ .thumb_set UART7_IRQHandler,Default_Handler
+
+ .weak UART8_IRQHandler
+ .thumb_set UART8_IRQHandler,Default_Handler
+
+ .weak SPI4_IRQHandler
+ .thumb_set SPI4_IRQHandler,Default_Handler
+
+ .weak SPI5_IRQHandler
+ .thumb_set SPI5_IRQHandler,Default_Handler
+
+ .weak SPI6_IRQHandler
+ .thumb_set SPI6_IRQHandler,Default_Handler
+
+ .weak SAI1_IRQHandler
+ .thumb_set SAI1_IRQHandler,Default_Handler
+
+ .weak LTDC_IRQHandler
+ .thumb_set LTDC_IRQHandler,Default_Handler
+
+ .weak LTDC_ER_IRQHandler
+ .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+ .weak DMA2D_IRQHandler
+ .thumb_set DMA2D_IRQHandler,Default_Handler
+
+ .weak SAI2_IRQHandler
+ .thumb_set SAI2_IRQHandler,Default_Handler
+
+ .weak OCTOSPI1_IRQHandler
+ .thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak I2C4_EV_IRQHandler
+ .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+ .weak I2C4_ER_IRQHandler
+ .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+ .weak SPDIF_RX_IRQHandler
+ .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+ .weak DMAMUX1_OVR_IRQHandler
+ .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT0_IRQHandler
+ .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT1_IRQHandler
+ .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT2_IRQHandler
+ .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT3_IRQHandler
+ .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+ .weak SWPMI1_IRQHandler
+ .thumb_set SWPMI1_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak MDIOS_WKUP_IRQHandler
+ .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
+
+ .weak MDIOS_IRQHandler
+ .thumb_set MDIOS_IRQHandler,Default_Handler
+
+ .weak JPEG_IRQHandler
+ .thumb_set JPEG_IRQHandler,Default_Handler
+
+ .weak MDMA_IRQHandler
+ .thumb_set MDMA_IRQHandler,Default_Handler
+
+ .weak SDMMC2_IRQHandler
+ .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+ .weak HSEM1_IRQHandler
+ .thumb_set HSEM1_IRQHandler,Default_Handler
+
+ .weak DAC2_IRQHandler
+ .thumb_set DAC2_IRQHandler,Default_Handler
+
+ .weak DMAMUX2_OVR_IRQHandler
+ .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel0_IRQHandler
+ .thumb_set BDMA2_Channel0_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel1_IRQHandler
+ .thumb_set BDMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel2_IRQHandler
+ .thumb_set BDMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel3_IRQHandler
+ .thumb_set BDMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel4_IRQHandler
+ .thumb_set BDMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel5_IRQHandler
+ .thumb_set BDMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel6_IRQHandler
+ .thumb_set BDMA2_Channel6_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel7_IRQHandler
+ .thumb_set BDMA2_Channel7_IRQHandler,Default_Handler
+
+ .weak COMP_IRQHandler
+ .thumb_set COMP_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak LPTIM4_IRQHandler
+ .thumb_set LPTIM4_IRQHandler,Default_Handler
+
+ .weak LPTIM5_IRQHandler
+ .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+ .weak UART9_IRQHandler
+ .thumb_set UART9_IRQHandler,Default_Handler
+
+ .weak USART10_IRQHandler
+ .thumb_set USART10_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak CRS_IRQHandler
+ .thumb_set CRS_IRQHandler,Default_Handler
+
+ .weak ECC_IRQHandler
+ .thumb_set ECC_IRQHandler,Default_Handler
+
+ .weak DTS_IRQHandler
+ .thumb_set DTS_IRQHandler,Default_Handler
+
+ .weak WAKEUP_PIN_IRQHandler
+ .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+ .weak OCTOSPI2_IRQHandler
+ .thumb_set OCTOSPI2_IRQHandler,Default_Handler
+
+ .weak OTFDEC1_IRQHandler
+ .thumb_set OTFDEC1_IRQHandler,Default_Handler
+
+ .weak OTFDEC2_IRQHandler
+ .thumb_set OTFDEC2_IRQHandler,Default_Handler
+
+ .weak GFXMMU_IRQHandler
+ .thumb_set GFXMMU_IRQHandler,Default_Handler
+
+ .weak BDMA1_IRQHandler
+ .thumb_set BDMA1_IRQHandler,Default_Handler
+
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b3xxq.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b3xxq.s new file mode 100644 index 0000000..0144db0 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h7b3xxq.s @@ -0,0 +1,751 @@ +/**
+ ******************************************************************************
+ * @file startup_stm32h7b3xxq.s
+ * @author MCD Application Team
+ * @brief STM32H7B3xx Devices vector table for GCC based toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m7
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+ /* External Interrupts */
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word PVD_PVM_IRQHandler /* PVD/PVM through EXTI Line detection */
+ .word RTC_TAMP_STAMP_CSS_LSE_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_IRQHandler /* EXTI Line0 */
+ .word EXTI1_IRQHandler /* EXTI Line1 */
+ .word EXTI2_IRQHandler /* EXTI Line2 */
+ .word EXTI3_IRQHandler /* EXTI Line3 */
+ .word EXTI4_IRQHandler /* EXTI Line4 */
+ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
+ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
+ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
+ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
+ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
+ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
+ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
+ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
+ .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
+ .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
+ .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
+ .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
+ .word EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
+ .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
+ .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM4_IRQHandler /* TIM4 */
+ .word I2C1_EV_IRQHandler /* I2C1 Event */
+ .word I2C1_ER_IRQHandler /* I2C1 Error */
+ .word I2C2_EV_IRQHandler /* I2C2 Event */
+ .word I2C2_ER_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
+ .word DFSDM2_IRQHandler /* DFSDM2 Interrupt */
+ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
+ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
+ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
+ .word FMC_IRQHandler /* FMC */
+ .word SDMMC1_IRQHandler /* SDMMC1 */
+ .word TIM5_IRQHandler /* TIM5 */
+ .word SPI3_IRQHandler /* SPI3 */
+ .word UART4_IRQHandler /* UART4 */
+ .word UART5_IRQHandler /* UART5 */
+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
+ .word TIM7_IRQHandler /* TIM7 */
+ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
+ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
+ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
+ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
+ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
+ .word DFSDM1_FLT4_IRQHandler /* DFSDM Filter4 Interrupt */
+ .word DFSDM1_FLT5_IRQHandler /* DFSDM Filter5 Interrupt */
+ .word DFSDM1_FLT6_IRQHandler /* DFSDM Filter6 Interrupt */
+ .word DFSDM1_FLT7_IRQHandler /* DFSDM Filter7 Interrupt */
+ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
+ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
+ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
+ .word USART6_IRQHandler /* USART6 */
+ .word I2C3_EV_IRQHandler /* I2C3 event */
+ .word I2C3_ER_IRQHandler /* I2C3 error */
+ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
+ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
+ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
+ .word OTG_HS_IRQHandler /* USB OTG HS */
+ .word DCMI_PSSI_IRQHandler /* DCMI, PSSI */
+ .word CRYP_IRQHandler /* CRYP crypto global interrupt */
+ .word HASH_RNG_IRQHandler /* RNG, HASH */
+ .word FPU_IRQHandler /* FPU */
+ .word UART7_IRQHandler /* UART7 */
+ .word UART8_IRQHandler /* UART8 */
+ .word SPI4_IRQHandler /* SPI4 */
+ .word SPI5_IRQHandler /* SPI5 */
+ .word SPI6_IRQHandler /* SPI6 */
+ .word SAI1_IRQHandler /* SAI1 */
+ .word LTDC_IRQHandler /* LTDC */
+ .word LTDC_ER_IRQHandler /* LTDC error */
+ .word DMA2D_IRQHandler /* DMA2D */
+ .word SAI2_IRQHandler /* SAI2 */
+ .word OCTOSPI1_IRQHandler /* OCTOSPI1 */
+ .word LPTIM1_IRQHandler /* LPTIM1 */
+ .word CEC_IRQHandler /* HDMI_CEC */
+ .word I2C4_EV_IRQHandler /* I2C4 Event */
+ .word I2C4_ER_IRQHandler /* I2C4 Error */
+ .word SPDIF_RX_IRQHandler /* SPDIF_RX */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
+ .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
+ .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
+ .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
+ .word 0 /* Reserved */
+ .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
+ .word TIM15_IRQHandler /* TIM15 global Interrupt */
+ .word TIM16_IRQHandler /* TIM16 global Interrupt */
+ .word TIM17_IRQHandler /* TIM17 global Interrupt */
+ .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
+ .word MDIOS_IRQHandler /* MDIOS global Interrupt */
+ .word JPEG_IRQHandler /* JPEG global Interrupt */
+ .word MDMA_IRQHandler /* MDMA global Interrupt */
+ .word 0 /* Reserved */
+ .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
+ .word HSEM1_IRQHandler /* HSEM1 global Interrupt */
+ .word 0 /* Reserved */
+ .word DAC2_IRQHandler /* DAC2 global Interrupt */
+ .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
+ .word BDMA2_Channel0_IRQHandler /* BDMA2 Channel 0 global Interrupt */
+ .word BDMA2_Channel1_IRQHandler /* BDMA2 Channel 1 global Interrupt */
+ .word BDMA2_Channel2_IRQHandler /* BDMA2 Channel 2 global Interrupt */
+ .word BDMA2_Channel3_IRQHandler /* BDMA2 Channel 3 global Interrupt */
+ .word BDMA2_Channel4_IRQHandler /* BDMA2 Channel 4 global Interrupt */
+ .word BDMA2_Channel5_IRQHandler /* BDMA2 Channel 5 global Interrupt */
+ .word BDMA2_Channel6_IRQHandler /* BDMA2 Channel 6 global Interrupt */
+ .word BDMA2_Channel7_IRQHandler /* BDMA2 Channel 7 global Interrupt */
+ .word COMP_IRQHandler /* COMP global Interrupt */
+ .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
+ .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
+ .word UART9_IRQHandler /* UART9 global interrupt */
+ .word USART10_IRQHandler /* USART10 global interrupt */
+ .word LPUART1_IRQHandler /* LP UART1 interrupt */
+ .word 0 /* Reserved */
+ .word CRS_IRQHandler /* Clock Recovery Global Interrupt */
+ .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
+ .word 0 /* Reserved */
+ .word DTS_IRQHandler /* DTS */
+ .word 0 /* Reserved */
+ .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
+ .word OCTOSPI2_IRQHandler /* OCTOSPI2 */
+ .word OTFDEC1_IRQHandler /* OTFDEC1 */
+ .word OTFDEC2_IRQHandler /* OTFDEC2 */
+ .word GFXMMU_IRQHandler /* GFXMMU */
+ .word BDMA1_IRQHandler /* BDMA1 */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_PVM_IRQHandler
+ .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+ .weak RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+ .thumb_set RTC_TAMP_STAMP_CSS_LSE_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream0_IRQHandler
+ .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream1_IRQHandler
+ .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream2_IRQHandler
+ .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream3_IRQHandler
+ .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream4_IRQHandler
+ .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream5_IRQHandler
+ .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream6_IRQHandler
+ .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT0_IRQHandler
+ .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT0_IRQHandler
+ .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT1_IRQHandler
+ .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT1_IRQHandler
+ .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak DFSDM2_IRQHandler
+ .thumb_set DFSDM2_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_TIM12_IRQHandler
+ .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_TIM13_IRQHandler
+ .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_TIM14_IRQHandler
+ .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream7_IRQHandler
+ .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+ .weak FMC_IRQHandler
+ .thumb_set FMC_IRQHandler,Default_Handler
+
+ .weak SDMMC1_IRQHandler
+ .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream0_IRQHandler
+ .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream1_IRQHandler
+ .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream2_IRQHandler
+ .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream3_IRQHandler
+ .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream4_IRQHandler
+ .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+ .weak FDCAN_CAL_IRQHandler
+ .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT4_IRQHandler
+ .thumb_set DFSDM1_FLT4_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT5_IRQHandler
+ .thumb_set DFSDM1_FLT5_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT6_IRQHandler
+ .thumb_set DFSDM1_FLT6_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT7_IRQHandler
+ .thumb_set DFSDM1_FLT7_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream5_IRQHandler
+ .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream6_IRQHandler
+ .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream7_IRQHandler
+ .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+ .weak USART6_IRQHandler
+ .thumb_set USART6_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_OUT_IRQHandler
+ .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_IN_IRQHandler
+ .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_HS_WKUP_IRQHandler
+ .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_HS_IRQHandler
+ .thumb_set OTG_HS_IRQHandler,Default_Handler
+
+ .weak DCMI_PSSI_IRQHandler
+ .thumb_set DCMI_PSSI_IRQHandler,Default_Handler
+
+ .weak CRYP_IRQHandler
+ .thumb_set CRYP_IRQHandler,Default_Handler
+
+ .weak HASH_RNG_IRQHandler
+ .thumb_set HASH_RNG_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak UART7_IRQHandler
+ .thumb_set UART7_IRQHandler,Default_Handler
+
+ .weak UART8_IRQHandler
+ .thumb_set UART8_IRQHandler,Default_Handler
+
+ .weak SPI4_IRQHandler
+ .thumb_set SPI4_IRQHandler,Default_Handler
+
+ .weak SPI5_IRQHandler
+ .thumb_set SPI5_IRQHandler,Default_Handler
+
+ .weak SPI6_IRQHandler
+ .thumb_set SPI6_IRQHandler,Default_Handler
+
+ .weak SAI1_IRQHandler
+ .thumb_set SAI1_IRQHandler,Default_Handler
+
+ .weak LTDC_IRQHandler
+ .thumb_set LTDC_IRQHandler,Default_Handler
+
+ .weak LTDC_ER_IRQHandler
+ .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+ .weak DMA2D_IRQHandler
+ .thumb_set DMA2D_IRQHandler,Default_Handler
+
+ .weak SAI2_IRQHandler
+ .thumb_set SAI2_IRQHandler,Default_Handler
+
+ .weak OCTOSPI1_IRQHandler
+ .thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak I2C4_EV_IRQHandler
+ .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+ .weak I2C4_ER_IRQHandler
+ .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+ .weak SPDIF_RX_IRQHandler
+ .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+ .weak DMAMUX1_OVR_IRQHandler
+ .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT0_IRQHandler
+ .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT1_IRQHandler
+ .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT2_IRQHandler
+ .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT3_IRQHandler
+ .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+ .weak SWPMI1_IRQHandler
+ .thumb_set SWPMI1_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak MDIOS_WKUP_IRQHandler
+ .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
+
+ .weak MDIOS_IRQHandler
+ .thumb_set MDIOS_IRQHandler,Default_Handler
+
+ .weak JPEG_IRQHandler
+ .thumb_set JPEG_IRQHandler,Default_Handler
+
+ .weak MDMA_IRQHandler
+ .thumb_set MDMA_IRQHandler,Default_Handler
+
+ .weak SDMMC2_IRQHandler
+ .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+ .weak HSEM1_IRQHandler
+ .thumb_set HSEM1_IRQHandler,Default_Handler
+
+ .weak DAC2_IRQHandler
+ .thumb_set DAC2_IRQHandler,Default_Handler
+
+ .weak DMAMUX2_OVR_IRQHandler
+ .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel0_IRQHandler
+ .thumb_set BDMA2_Channel0_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel1_IRQHandler
+ .thumb_set BDMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel2_IRQHandler
+ .thumb_set BDMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel3_IRQHandler
+ .thumb_set BDMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel4_IRQHandler
+ .thumb_set BDMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel5_IRQHandler
+ .thumb_set BDMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel6_IRQHandler
+ .thumb_set BDMA2_Channel6_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel7_IRQHandler
+ .thumb_set BDMA2_Channel7_IRQHandler,Default_Handler
+
+ .weak COMP_IRQHandler
+ .thumb_set COMP_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak LPTIM4_IRQHandler
+ .thumb_set LPTIM4_IRQHandler,Default_Handler
+
+ .weak LPTIM5_IRQHandler
+ .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+ .weak UART9_IRQHandler
+ .thumb_set UART9_IRQHandler,Default_Handler
+
+ .weak USART10_IRQHandler
+ .thumb_set USART10_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak CRS_IRQHandler
+ .thumb_set CRS_IRQHandler,Default_Handler
+
+ .weak ECC_IRQHandler
+ .thumb_set ECC_IRQHandler,Default_Handler
+
+ .weak DTS_IRQHandler
+ .thumb_set DTS_IRQHandler,Default_Handler
+
+ .weak WAKEUP_PIN_IRQHandler
+ .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+ .weak OCTOSPI2_IRQHandler
+ .thumb_set OCTOSPI2_IRQHandler,Default_Handler
+
+ .weak OTFDEC1_IRQHandler
+ .thumb_set OTFDEC1_IRQHandler,Default_Handler
+
+ .weak OTFDEC2_IRQHandler
+ .thumb_set OTFDEC2_IRQHandler,Default_Handler
+
+ .weak GFXMMU_IRQHandler
+ .thumb_set GFXMMU_IRQHandler,Default_Handler
+
+ .weak BDMA1_IRQHandler
+ .thumb_set BDMA1_IRQHandler,Default_Handler
+
+
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_axisram.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_axisram.icf new file mode 100644 index 0000000..a830d47 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_axisram.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x24000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2401FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24020000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_dtcmram.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_dtcmram.icf new file mode 100644 index 0000000..281b35f --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_dtcmram.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2000FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20010000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash.icf new file mode 100644 index 0000000..2127c19 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_ahbsram.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_ahbsram.icf new file mode 100644 index 0000000..026abf5 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_ahbsram.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x30007FFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_axisram.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_axisram.icf new file mode 100644 index 0000000..c73a24c --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_axisram.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_sram1.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_sram1.icf new file mode 100644 index 0000000..c73a24c --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_sram1.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_sram2.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_sram2.icf new file mode 100644 index 0000000..026abf5 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_flash_rw_sram2.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x30007FFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_sram1.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_sram1.icf new file mode 100644 index 0000000..a830d47 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xe_sram1.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x24000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2401FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24020000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_axisram.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_axisram.icf new file mode 100644 index 0000000..a830d47 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_axisram.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x24000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2401FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24020000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_dtcmram.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_dtcmram.icf new file mode 100644 index 0000000..281b35f --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_dtcmram.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2000FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20010000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash.icf new file mode 100644 index 0000000..0b0d23a --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_ahbsram.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_ahbsram.icf new file mode 100644 index 0000000..872a672 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_ahbsram.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x30007FFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_axisram.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_axisram.icf new file mode 100644 index 0000000..c70f0f6 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_axisram.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_sram1.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_sram1.icf new file mode 100644 index 0000000..c70f0f6 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_sram1.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_sram2.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_sram2.icf new file mode 100644 index 0000000..872a672 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_flash_rw_sram2.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x30007FFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_sram1.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_sram1.icf new file mode 100644 index 0000000..a830d47 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h723xx_sram1.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x24000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2401FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24020000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_axisram.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_axisram.icf new file mode 100644 index 0000000..a830d47 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_axisram.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x24000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2401FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24020000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_dtcmram.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_dtcmram.icf new file mode 100644 index 0000000..281b35f --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_dtcmram.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2000FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20010000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash.icf new file mode 100644 index 0000000..2127c19 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_ahbsram.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_ahbsram.icf new file mode 100644 index 0000000..026abf5 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_ahbsram.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x30007FFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_axisram.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_axisram.icf new file mode 100644 index 0000000..c73a24c --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_axisram.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_sram1.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_sram1.icf new file mode 100644 index 0000000..c73a24c --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_sram1.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_sram2.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_sram2.icf new file mode 100644 index 0000000..026abf5 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_flash_rw_sram2.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x30007FFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_sram1.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_sram1.icf new file mode 100644 index 0000000..a830d47 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xe_sram1.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x24000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2401FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24020000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_axisram.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_axisram.icf new file mode 100644 index 0000000..a830d47 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_axisram.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x24000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2401FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24020000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_dtcmram.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_dtcmram.icf new file mode 100644 index 0000000..281b35f --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_dtcmram.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2000FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20010000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash.icf new file mode 100644 index 0000000..0b0d23a --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_ahbsram.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_ahbsram.icf new file mode 100644 index 0000000..872a672 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_ahbsram.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x30007FFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_axisram.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_axisram.icf new file mode 100644 index 0000000..c70f0f6 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_axisram.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_sram1.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_sram1.icf new file mode 100644 index 0000000..c70f0f6 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_sram1.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_sram2.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_sram2.icf new file mode 100644 index 0000000..872a672 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_flash_rw_sram2.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x30007FFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_sram1.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_sram1.icf new file mode 100644 index 0000000..a830d47 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h725xx_sram1.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x24000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2401FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24020000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_axisram.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_axisram.icf new file mode 100644 index 0000000..a830d47 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_axisram.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x24000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2401FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24020000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_dtcmram.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_dtcmram.icf new file mode 100644 index 0000000..281b35f --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_dtcmram.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2000FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20010000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash.icf new file mode 100644 index 0000000..8922386 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_ahbsram.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_ahbsram.icf new file mode 100644 index 0000000..df56aa0 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_ahbsram.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x30007FFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_axisram.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_axisram.icf new file mode 100644 index 0000000..1d1da43 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_axisram.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_sram1.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_sram1.icf new file mode 100644 index 0000000..1d1da43 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_sram1.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_sram2.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_sram2.icf new file mode 100644 index 0000000..df56aa0 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_flash_rw_sram2.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x30007FFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_sram1.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_sram1.icf new file mode 100644 index 0000000..a830d47 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xx_sram1.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x24000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2401FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24020000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_axisram.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_axisram.icf new file mode 100644 index 0000000..a830d47 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_axisram.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x24000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2401FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24020000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_dtcmram.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_dtcmram.icf new file mode 100644 index 0000000..281b35f --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_dtcmram.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2000FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20010000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash.icf new file mode 100644 index 0000000..8922386 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_ahbsram.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_ahbsram.icf new file mode 100644 index 0000000..df56aa0 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_ahbsram.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x30007FFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_axisram.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_axisram.icf new file mode 100644 index 0000000..1d1da43 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_axisram.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_sram1.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_sram1.icf new file mode 100644 index 0000000..1d1da43 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_sram1.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_sram2.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_sram2.icf new file mode 100644 index 0000000..df56aa0 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_flash_rw_sram2.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x30007FFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_sram1.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_sram1.icf new file mode 100644 index 0000000..a830d47 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h730xxq_sram1.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x24000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2401FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24020000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_axisram.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_axisram.icf new file mode 100644 index 0000000..a830d47 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_axisram.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x24000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2401FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24020000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_dtcmram.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_dtcmram.icf new file mode 100644 index 0000000..281b35f --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_dtcmram.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2000FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20010000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash.icf new file mode 100644 index 0000000..0b0d23a --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_ahbsram.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_ahbsram.icf new file mode 100644 index 0000000..872a672 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_ahbsram.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x30007FFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_axisram.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_axisram.icf new file mode 100644 index 0000000..c70f0f6 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_axisram.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_sram1.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_sram1.icf new file mode 100644 index 0000000..c70f0f6 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_sram1.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_sram2.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_sram2.icf new file mode 100644 index 0000000..872a672 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_flash_rw_sram2.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x30007FFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_sram1.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_sram1.icf new file mode 100644 index 0000000..a830d47 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h733xx_sram1.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x24000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2401FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24020000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_axisram.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_axisram.icf new file mode 100644 index 0000000..a830d47 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_axisram.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x24000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2401FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24020000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_dtcmram.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_dtcmram.icf new file mode 100644 index 0000000..281b35f --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_dtcmram.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2000FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20010000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash.icf new file mode 100644 index 0000000..0b0d23a --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_ahbsram.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_ahbsram.icf new file mode 100644 index 0000000..872a672 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_ahbsram.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x30007FFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_axisram.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_axisram.icf new file mode 100644 index 0000000..c70f0f6 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_axisram.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_sram1.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_sram1.icf new file mode 100644 index 0000000..c70f0f6 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_sram1.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_sram2.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_sram2.icf new file mode 100644 index 0000000..872a672 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_flash_rw_sram2.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x30007FFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_sram1.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_sram1.icf new file mode 100644 index 0000000..a830d47 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h735xx_sram1.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x24000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2401FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24020000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xg_flash.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xg_flash.icf new file mode 100644 index 0000000..dc1d1d8 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xg_flash.icf @@ -0,0 +1,37 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_bank1_start__ = 0x08000000;
+define symbol __ICFEDIT_region_bank1_end__ = 0x0807FFFF;
+define symbol __ICFEDIT_region_bank2_start__ = 0x08100000;
+define symbol __ICFEDIT_region_bank2_end__ = 0x0817FFFF;
+
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_bank1_start__ to __ICFEDIT_region_bank1_end__] | mem:[ from __ICFEDIT_region_bank2_start__ to __ICFEDIT_region_bank2_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xg_flash_rw_sram1.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xg_flash_rw_sram1.icf new file mode 100644 index 0000000..d899532 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xg_flash_rw_sram1.icf @@ -0,0 +1,37 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_bank1_start__ = 0x08000000;
+define symbol __ICFEDIT_region_bank1_end__ = 0x0807FFFF;
+define symbol __ICFEDIT_region_bank2_start__ = 0x08100000;
+define symbol __ICFEDIT_region_bank2_end__ = 0x0817FFFF;
+
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2405FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_bank1_start__ to __ICFEDIT_region_bank1_end__] | mem:[ from __ICFEDIT_region_bank2_start__ to __ICFEDIT_region_bank2_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xg_flash_rw_sram2.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xg_flash_rw_sram2.icf new file mode 100644 index 0000000..1a4ae0c --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xg_flash_rw_sram2.icf @@ -0,0 +1,37 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_bank1_start__ = 0x08000000;
+define symbol __ICFEDIT_region_bank1_end__ = 0x0807FFFF;
+define symbol __ICFEDIT_region_bank2_start__ = 0x08100000;
+define symbol __ICFEDIT_region_bank2_end__ = 0x0817FFFF;
+
+define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x30007FFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_bank1_start__ to __ICFEDIT_region_bank1_end__] | mem:[ from __ICFEDIT_region_bank2_start__ to __ICFEDIT_region_bank2_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_dtcmram.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_dtcmram.icf new file mode 100644 index 0000000..281b35f --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_dtcmram.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2000FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20010000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_flash.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_flash.icf new file mode 100644 index 0000000..07eb3c6 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_flash.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_flash_rw_sram1.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_flash_rw_sram1.icf new file mode 100644 index 0000000..17e0293 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_flash_rw_sram1.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2405FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_flash_rw_sram2.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_flash_rw_sram2.icf new file mode 100644 index 0000000..f056a26 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_flash_rw_sram2.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x30007FFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_sram1.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_sram1.icf new file mode 100644 index 0000000..a1800c7 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h742xx_sram1.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x24000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2402FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24030000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2405FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xg_flash.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xg_flash.icf new file mode 100644 index 0000000..dc1d1d8 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xg_flash.icf @@ -0,0 +1,37 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_bank1_start__ = 0x08000000;
+define symbol __ICFEDIT_region_bank1_end__ = 0x0807FFFF;
+define symbol __ICFEDIT_region_bank2_start__ = 0x08100000;
+define symbol __ICFEDIT_region_bank2_end__ = 0x0817FFFF;
+
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_bank1_start__ to __ICFEDIT_region_bank1_end__] | mem:[ from __ICFEDIT_region_bank2_start__ to __ICFEDIT_region_bank2_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xg_flash_rw_sram1.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xg_flash_rw_sram1.icf new file mode 100644 index 0000000..c68b9a2 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xg_flash_rw_sram1.icf @@ -0,0 +1,37 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_bank1_start__ = 0x08000000;
+define symbol __ICFEDIT_region_bank1_end__ = 0x0807FFFF;
+define symbol __ICFEDIT_region_bank2_start__ = 0x08100000;
+define symbol __ICFEDIT_region_bank2_end__ = 0x0817FFFF;
+
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2407FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_bank1_start__ to __ICFEDIT_region_bank1_end__] | mem:[ from __ICFEDIT_region_bank2_start__ to __ICFEDIT_region_bank2_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xg_flash_rw_sram2.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xg_flash_rw_sram2.icf new file mode 100644 index 0000000..b99656e --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xg_flash_rw_sram2.icf @@ -0,0 +1,37 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_bank1_start__ = 0x08000000;
+define symbol __ICFEDIT_region_bank1_end__ = 0x0807FFFF;
+define symbol __ICFEDIT_region_bank2_start__ = 0x08100000;
+define symbol __ICFEDIT_region_bank2_end__ = 0x0817FFFF;
+
+define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x30047FFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_bank1_start__ to __ICFEDIT_region_bank1_end__] | mem:[ from __ICFEDIT_region_bank2_start__ to __ICFEDIT_region_bank2_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_dtcmram.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_dtcmram.icf new file mode 100644 index 0000000..281b35f --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_dtcmram.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2000FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20010000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash.icf new file mode 100644 index 0000000..07eb3c6 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash_rw_sram1.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash_rw_sram1.icf new file mode 100644 index 0000000..0b1fb90 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash_rw_sram1.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2407FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash_rw_sram2.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash_rw_sram2.icf new file mode 100644 index 0000000..d5b3748 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_flash_rw_sram2.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x30047FFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_sram1.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_sram1.icf new file mode 100644 index 0000000..72e32d1 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h743xx_sram1.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x24000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2403FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24040000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2407FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xg_flash_CM4.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xg_flash_CM4.icf new file mode 100644 index 0000000..93a8023 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xg_flash_CM4.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08100000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08100000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0817FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x10000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x10047FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xg_flash_CM7.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xg_flash_CM7.icf new file mode 100644 index 0000000..2127c19 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xg_flash_CM7.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_dtcmram_CM7.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_dtcmram_CM7.icf new file mode 100644 index 0000000..281b35f --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_dtcmram_CM7.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2000FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20010000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_CM4.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_CM4.icf new file mode 100644 index 0000000..2a625ef --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_CM4.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08100000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08100000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x10000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x10047FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_CM7.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_CM7.icf new file mode 100644 index 0000000..0b0d23a --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_CM7.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_rw_sram1_CM7.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_rw_sram1_CM7.icf new file mode 100644 index 0000000..9ff8611 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_rw_sram1_CM7.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2407FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_rw_sram2_CM4.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_rw_sram2_CM4.icf new file mode 100644 index 0000000..2a625ef --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_flash_rw_sram2_CM4.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08100000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08100000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x10000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x10047FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_sram1_CM7.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_sram1_CM7.icf new file mode 100644 index 0000000..72e32d1 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_sram1_CM7.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x24000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2403FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24040000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2407FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_sram2_CM4.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_sram2_CM4.icf new file mode 100644 index 0000000..7b05b4c --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h745xx_sram2_CM4.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x10000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x10000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x1001FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x10020000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x10047FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xg_flash_CM4.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xg_flash_CM4.icf new file mode 100644 index 0000000..93a8023 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xg_flash_CM4.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08100000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08100000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0817FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x10000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x10047FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xg_flash_CM7.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xg_flash_CM7.icf new file mode 100644 index 0000000..2127c19 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xg_flash_CM7.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_dtcmram_CM7.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_dtcmram_CM7.icf new file mode 100644 index 0000000..281b35f --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_dtcmram_CM7.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2000FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20010000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_CM4.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_CM4.icf new file mode 100644 index 0000000..2a625ef --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_CM4.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08100000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08100000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x10000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x10047FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_CM7.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_CM7.icf new file mode 100644 index 0000000..0b0d23a --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_CM7.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_rw_sram1_CM7.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_rw_sram1_CM7.icf new file mode 100644 index 0000000..9ff8611 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_rw_sram1_CM7.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2407FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_rw_sram2_CM4.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_rw_sram2_CM4.icf new file mode 100644 index 0000000..2a625ef --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_flash_rw_sram2_CM4.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08100000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08100000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x10000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x10047FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_sram1_CM7.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_sram1_CM7.icf new file mode 100644 index 0000000..72e32d1 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_sram1_CM7.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x24000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2403FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24040000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2407FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_sram2_CM4.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_sram2_CM4.icf new file mode 100644 index 0000000..7b05b4c --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h747xx_sram2_CM4.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x10000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x10000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x1001FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x10020000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x10047FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_dtcmram.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_dtcmram.icf new file mode 100644 index 0000000..281b35f --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_dtcmram.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2000FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20010000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash.icf new file mode 100644 index 0000000..8922386 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash_rw_sram1.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash_rw_sram1.icf new file mode 100644 index 0000000..84beffd --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash_rw_sram1.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2407FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash_rw_sram2.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash_rw_sram2.icf new file mode 100644 index 0000000..2f3ab60 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_flash_rw_sram2.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x30047FFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_sram1.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_sram1.icf new file mode 100644 index 0000000..72e32d1 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h750xx_sram1.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x24000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2403FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24040000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2407FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_dtcmram.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_dtcmram.icf new file mode 100644 index 0000000..281b35f --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_dtcmram.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2000FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20010000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash.icf new file mode 100644 index 0000000..07eb3c6 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash_rw_sram1.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash_rw_sram1.icf new file mode 100644 index 0000000..0b1fb90 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash_rw_sram1.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2407FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash_rw_sram2.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash_rw_sram2.icf new file mode 100644 index 0000000..d5b3748 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_flash_rw_sram2.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x30047FFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_sram1.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_sram1.icf new file mode 100644 index 0000000..72e32d1 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h753xx_sram1.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x24000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2403FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24040000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2407FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_dtcmram_CM7.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_dtcmram_CM7.icf new file mode 100644 index 0000000..281b35f --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_dtcmram_CM7.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2000FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20010000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_CM4.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_CM4.icf new file mode 100644 index 0000000..2a625ef --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_CM4.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08100000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08100000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x10000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x10047FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_CM7.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_CM7.icf new file mode 100644 index 0000000..0b0d23a --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_CM7.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_rw_sram1_CM7.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_rw_sram1_CM7.icf new file mode 100644 index 0000000..9ff8611 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_rw_sram1_CM7.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2407FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_rw_sram2_CM4.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_rw_sram2_CM4.icf new file mode 100644 index 0000000..2a625ef --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_flash_rw_sram2_CM4.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08100000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08100000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x10000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x10047FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_sram1_CM7.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_sram1_CM7.icf new file mode 100644 index 0000000..72e32d1 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_sram1_CM7.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x24000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2403FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24040000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2407FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_sram2_CM4.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_sram2_CM4.icf new file mode 100644 index 0000000..7b05b4c --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h755xx_sram2_CM4.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x10000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x10000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x1001FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x10020000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x10047FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_dtcmram_CM7.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_dtcmram_CM7.icf new file mode 100644 index 0000000..281b35f --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_dtcmram_CM7.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2000FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20010000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_CM4.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_CM4.icf new file mode 100644 index 0000000..2a625ef --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_CM4.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08100000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08100000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x10000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x10047FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_CM7.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_CM7.icf new file mode 100644 index 0000000..0b0d23a --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_CM7.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_rw_sram1_CM7.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_rw_sram1_CM7.icf new file mode 100644 index 0000000..9ff8611 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_rw_sram1_CM7.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2407FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_rw_sram2_CM4.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_rw_sram2_CM4.icf new file mode 100644 index 0000000..2a625ef --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_flash_rw_sram2_CM4.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08100000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08100000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x10000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x10047FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_sram1_CM7.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_sram1_CM7.icf new file mode 100644 index 0000000..72e32d1 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_sram1_CM7.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x24000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x2403FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x24040000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2407FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x0000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_sram2_CM4.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_sram2_CM4.icf new file mode 100644 index 0000000..7b05b4c --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h757xx_sram2_CM4.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x10000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x10000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x1001FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x10020000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x10047FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xg_flash.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xg_flash.icf new file mode 100644 index 0000000..c5878f2 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xg_flash.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_bank1_start__ = 0x08000000;
+define symbol __ICFEDIT_region_bank1_end__ = 0x0807FFFF;
+define symbol __ICFEDIT_region_bank2_start__ = 0x08100000;
+define symbol __ICFEDIT_region_bank2_end__ = 0x0817FFFF;
+
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_bank1_start__ to __ICFEDIT_region_bank1_end__] | mem:[ from __ICFEDIT_region_bank2_start__ to __ICFEDIT_region_bank2_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xg_flash_rw_sram1.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xg_flash_rw_sram1.icf new file mode 100644 index 0000000..ddd1e58 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xg_flash_rw_sram1.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_bank1_start__ = 0x08000000;
+define symbol __ICFEDIT_region_bank1_end__ = 0x0807FFFF;
+define symbol __ICFEDIT_region_bank2_start__ = 0x08100000;
+define symbol __ICFEDIT_region_bank2_end__ = 0x0817FFFF;
+
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x240FFFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_bank1_start__ to __ICFEDIT_region_bank1_end__] | mem:[ from __ICFEDIT_region_bank2_start__ to __ICFEDIT_region_bank2_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xg_flash_rw_sram2.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xg_flash_rw_sram2.icf new file mode 100644 index 0000000..ec12579 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xg_flash_rw_sram2.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_bank1_start__ = 0x08000000;
+define symbol __ICFEDIT_region_bank1_end__ = 0x0807FFFF;
+define symbol __ICFEDIT_region_bank2_start__ = 0x08100000;
+define symbol __ICFEDIT_region_bank2_end__ = 0x0817FFFF;
+
+define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x3001FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_bank1_start__ to __ICFEDIT_region_bank1_end__] | mem:[ from __ICFEDIT_region_bank2_start__ to __ICFEDIT_region_bank2_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xgq_flash.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xgq_flash.icf new file mode 100644 index 0000000..c5878f2 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xgq_flash.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_bank1_start__ = 0x08000000;
+define symbol __ICFEDIT_region_bank1_end__ = 0x0807FFFF;
+define symbol __ICFEDIT_region_bank2_start__ = 0x08100000;
+define symbol __ICFEDIT_region_bank2_end__ = 0x0817FFFF;
+
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_bank1_start__ to __ICFEDIT_region_bank1_end__] | mem:[ from __ICFEDIT_region_bank2_start__ to __ICFEDIT_region_bank2_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xgq_flash_rw_sram1.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xgq_flash_rw_sram1.icf new file mode 100644 index 0000000..ddd1e58 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xgq_flash_rw_sram1.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_bank1_start__ = 0x08000000;
+define symbol __ICFEDIT_region_bank1_end__ = 0x0807FFFF;
+define symbol __ICFEDIT_region_bank2_start__ = 0x08100000;
+define symbol __ICFEDIT_region_bank2_end__ = 0x0817FFFF;
+
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x240FFFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_bank1_start__ to __ICFEDIT_region_bank1_end__] | mem:[ from __ICFEDIT_region_bank2_start__ to __ICFEDIT_region_bank2_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xgq_flash_rw_sram2.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xgq_flash_rw_sram2.icf new file mode 100644 index 0000000..be4a686 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xgq_flash_rw_sram2.icf @@ -0,0 +1,35 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_bank1_start__ = 0x08000000;
+define symbol __ICFEDIT_region_bank1_end__ = 0x0807FFFF;
+define symbol __ICFEDIT_region_bank2_start__ = 0x08100000;
+define symbol __ICFEDIT_region_bank2_end__ = 0x0817FFFF;
+
+
+define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x3001FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_bank1_start__ to __ICFEDIT_region_bank1_end__] | mem:[ from __ICFEDIT_region_bank2_start__ to __ICFEDIT_region_bank2_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xx_flash.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xx_flash.icf new file mode 100644 index 0000000..a28878e --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xx_flash.icf @@ -0,0 +1,32 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
+
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xx_flash_rw_sram1.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xx_flash_rw_sram1.icf new file mode 100644 index 0000000..0a6a045 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xx_flash_rw_sram1.icf @@ -0,0 +1,32 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
+
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x240FFFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xx_flash_rw_sram2.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xx_flash_rw_sram2.icf new file mode 100644 index 0000000..92a5c52 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xx_flash_rw_sram2.icf @@ -0,0 +1,32 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
+
+define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x3001FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xxq_flash.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xxq_flash.icf new file mode 100644 index 0000000..a28878e --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xxq_flash.icf @@ -0,0 +1,32 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
+
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xxq_flash_rw_sram1.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xxq_flash_rw_sram1.icf new file mode 100644 index 0000000..0a6a045 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xxq_flash_rw_sram1.icf @@ -0,0 +1,32 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
+
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x240FFFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xxq_flash_rw_sram2.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xxq_flash_rw_sram2.icf new file mode 100644 index 0000000..92a5c52 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7a3xxq_flash_rw_sram2.icf @@ -0,0 +1,32 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
+
+define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x3001FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xx_flash.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xx_flash.icf new file mode 100644 index 0000000..925210b --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xx_flash.icf @@ -0,0 +1,32 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
+
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xx_flash_rw_sram1.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xx_flash_rw_sram1.icf new file mode 100644 index 0000000..4e7ecdb --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xx_flash_rw_sram1.icf @@ -0,0 +1,32 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
+
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x240FFFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xx_flash_rw_sram2.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xx_flash_rw_sram2.icf new file mode 100644 index 0000000..ff724e4 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xx_flash_rw_sram2.icf @@ -0,0 +1,32 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
+
+define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x3001FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xxq_flash.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xxq_flash.icf new file mode 100644 index 0000000..925210b --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xxq_flash.icf @@ -0,0 +1,32 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
+
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xxq_flash_rw_sram1.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xxq_flash_rw_sram1.icf new file mode 100644 index 0000000..4e7ecdb --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xxq_flash_rw_sram1.icf @@ -0,0 +1,32 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
+
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x240FFFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xxq_flash_rw_sram2.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xxq_flash_rw_sram2.icf new file mode 100644 index 0000000..ff724e4 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b0xxq_flash_rw_sram2.icf @@ -0,0 +1,32 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
+
+define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x3001FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xx_flash.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xx_flash.icf new file mode 100644 index 0000000..a28878e --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xx_flash.icf @@ -0,0 +1,32 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
+
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xx_flash_rw_sram1.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xx_flash_rw_sram1.icf new file mode 100644 index 0000000..0a6a045 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xx_flash_rw_sram1.icf @@ -0,0 +1,32 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
+
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x240FFFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xx_flash_rw_sram2.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xx_flash_rw_sram2.icf new file mode 100644 index 0000000..92a5c52 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xx_flash_rw_sram2.icf @@ -0,0 +1,32 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
+
+define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x3001FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xxq_flash.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xxq_flash.icf new file mode 100644 index 0000000..a28878e --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xxq_flash.icf @@ -0,0 +1,32 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
+
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xxq_flash_rw_sram1.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xxq_flash_rw_sram1.icf new file mode 100644 index 0000000..0a6a045 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xxq_flash_rw_sram1.icf @@ -0,0 +1,32 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
+
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x240FFFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xxq_flash_rw_sram2.icf b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xxq_flash_rw_sram2.icf new file mode 100644 index 0000000..92a5c52 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/linker/stm32h7b3xxq_flash_rw_sram2.icf @@ -0,0 +1,32 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
+
+define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x3001FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h723xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h723xx.s new file mode 100644 index 0000000..df0de08 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h723xx.s @@ -0,0 +1,982 @@ +;/********************************************************************************
+;* File Name : startup_stm32h723xx.s
+;* Author : MCD Application Team
+;* Description : STM32H723xx devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it)
+ DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_PSSI_IRQHandler ; DCMI, PSSI
+ DCD 0 ; Reserved
+ DCD RNG_IRQHandler ; Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD 0 ; Reserved
+ DCD OCTOSPI1_IRQHandler ; OCTOSPI1
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD 0 ; Reserved
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD 0 ; Reserved
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD 0 ; Reserved
+ DCD ADC3_IRQHandler ; ADC3 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP1_IRQHandler ; COMP1 global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
+ DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD 0 ; Reserved
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
+ DCD SAI4_IRQHandler ; SAI4 global interrupt
+ DCD DTS_IRQHandler ; Digital Temperature Sensor
+ DCD 0 ; Reserved
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+ DCD OCTOSPI2_IRQHandler ; OCTOSPI2 Interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FMAC_IRQHandler ; FMAC Interrupt
+ DCD CORDIC_IRQHandler ; CORDIC Interrupt
+ DCD UART9_IRQHandler ; UART9 Interrupt
+ DCD USART10_IRQHandler ; USART10 Interrupt
+ DCD I2C5_EV_IRQHandler ; I2C5 Event Interrupt
+ DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt
+ DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0
+ DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1
+ DCD TIM23_IRQHandler ; TIM23 global interrupt
+ DCD TIM24_IRQHandler ; TIM24 global interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_AVD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_AVD_IRQHandler
+ B PVD_AVD_IRQHandler
+
+ PUBWEAK TAMP_STAMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+ B TAMP_STAMP_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream0_IRQHandler
+ B DMA1_Stream0_IRQHandler
+
+ PUBWEAK DMA1_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream1_IRQHandler
+ B DMA1_Stream1_IRQHandler
+
+ PUBWEAK DMA1_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream2_IRQHandler
+ B DMA1_Stream2_IRQHandler
+
+ PUBWEAK DMA1_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream3_IRQHandler
+ B DMA1_Stream3_IRQHandler
+
+ PUBWEAK DMA1_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream4_IRQHandler
+ B DMA1_Stream4_IRQHandler
+
+ PUBWEAK DMA1_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream5_IRQHandler
+ B DMA1_Stream5_IRQHandler
+
+ PUBWEAK DMA1_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream6_IRQHandler
+ B DMA1_Stream6_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK FDCAN1_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+ B FDCAN1_IT0_IRQHandler
+
+ PUBWEAK FDCAN2_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT0_IRQHandler
+ B FDCAN2_IT0_IRQHandler
+
+ PUBWEAK FDCAN1_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+ B FDCAN1_IT1_IRQHandler
+
+ PUBWEAK FDCAN2_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT1_IRQHandler
+ B FDCAN2_IT1_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK TIM8_BRK_TIM12_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_TIM12_IRQHandler
+ B TIM8_BRK_TIM12_IRQHandler
+
+ PUBWEAK TIM8_UP_TIM13_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_TIM13_IRQHandler
+ B TIM8_UP_TIM13_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_TIM14_IRQHandler
+ B TIM8_TRG_COM_TIM14_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK DMA1_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream7_IRQHandler
+ B DMA1_Stream7_IRQHandler
+
+ PUBWEAK FMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+ B FMC_IRQHandler
+
+ PUBWEAK SDMMC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+ B SDMMC1_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream0_IRQHandler
+ B DMA2_Stream0_IRQHandler
+
+ PUBWEAK DMA2_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream1_IRQHandler
+ B DMA2_Stream1_IRQHandler
+
+ PUBWEAK DMA2_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream2_IRQHandler
+ B DMA2_Stream2_IRQHandler
+
+ PUBWEAK DMA2_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream3_IRQHandler
+ B DMA2_Stream3_IRQHandler
+
+ PUBWEAK DMA2_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream4_IRQHandler
+ B DMA2_Stream4_IRQHandler
+
+ PUBWEAK ETH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_IRQHandler
+ B ETH_IRQHandler
+
+ PUBWEAK ETH_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_WKUP_IRQHandler
+ B ETH_WKUP_IRQHandler
+
+ PUBWEAK FDCAN_CAL_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN_CAL_IRQHandler
+ B FDCAN_CAL_IRQHandler
+
+ PUBWEAK DMA2_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream5_IRQHandler
+ B DMA2_Stream5_IRQHandler
+
+ PUBWEAK DMA2_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream6_IRQHandler
+ B DMA2_Stream6_IRQHandler
+
+ PUBWEAK DMA2_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream7_IRQHandler
+ B DMA2_Stream7_IRQHandler
+
+ PUBWEAK USART6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler
+ B USART6_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_OUT_IRQHandler
+ B OTG_HS_EP1_OUT_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_IN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_IN_IRQHandler
+ B OTG_HS_EP1_IN_IRQHandler
+
+ PUBWEAK OTG_HS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_WKUP_IRQHandler
+ B OTG_HS_WKUP_IRQHandler
+
+ PUBWEAK OTG_HS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_IRQHandler
+ B OTG_HS_IRQHandler
+
+ PUBWEAK DCMI_PSSI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_PSSI_IRQHandler
+ B DCMI_PSSI_IRQHandler
+
+ PUBWEAK RNG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+ B RNG_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ PUBWEAK UART7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART7_IRQHandler
+ B UART7_IRQHandler
+
+ PUBWEAK UART8_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART8_IRQHandler
+ B UART8_IRQHandler
+
+ PUBWEAK SPI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+ B SPI4_IRQHandler
+
+ PUBWEAK SPI5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI5_IRQHandler
+ B SPI5_IRQHandler
+
+ PUBWEAK SPI6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI6_IRQHandler
+ B SPI6_IRQHandler
+
+ PUBWEAK SAI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+ B SAI1_IRQHandler
+
+ PUBWEAK LTDC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_IRQHandler
+ B LTDC_IRQHandler
+
+ PUBWEAK LTDC_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_ER_IRQHandler
+ B LTDC_ER_IRQHandler
+
+ PUBWEAK DMA2D_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+ B DMA2D_IRQHandler
+
+ PUBWEAK OCTOSPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI1_IRQHandler
+ B OCTOSPI1_IRQHandler
+
+ PUBWEAK LPTIM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+ B LPTIM1_IRQHandler
+
+ PUBWEAK CEC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler
+ B CEC_IRQHandler
+
+ PUBWEAK I2C4_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+ B I2C4_EV_IRQHandler
+
+ PUBWEAK I2C4_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+ B I2C4_ER_IRQHandler
+
+ PUBWEAK SPDIF_RX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPDIF_RX_IRQHandler
+ B SPDIF_RX_IRQHandler
+
+ PUBWEAK DMAMUX1_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+ B DMAMUX1_OVR_IRQHandler
+
+ PUBWEAK DFSDM1_FLT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT0_IRQHandler
+ B DFSDM1_FLT0_IRQHandler
+
+ PUBWEAK DFSDM1_FLT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+ B DFSDM1_FLT1_IRQHandler
+
+ PUBWEAK DFSDM1_FLT2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+ B DFSDM1_FLT2_IRQHandler
+
+ PUBWEAK DFSDM1_FLT3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+ B DFSDM1_FLT3_IRQHandler
+
+ PUBWEAK SWPMI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SWPMI1_IRQHandler
+ B SWPMI1_IRQHandler
+
+ PUBWEAK TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+ B TIM15_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK MDIOS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_WKUP_IRQHandler
+ B MDIOS_WKUP_IRQHandler
+
+ PUBWEAK MDIOS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_IRQHandler
+ B MDIOS_IRQHandler
+
+ PUBWEAK MDMA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDMA_IRQHandler
+ B MDMA_IRQHandler
+
+ PUBWEAK SDMMC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC2_IRQHandler
+ B SDMMC2_IRQHandler
+
+ PUBWEAK HSEM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM1_IRQHandler
+ B HSEM1_IRQHandler
+
+ PUBWEAK ADC3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC3_IRQHandler
+ B ADC3_IRQHandler
+
+ PUBWEAK DMAMUX2_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX2_OVR_IRQHandler
+ B DMAMUX2_OVR_IRQHandler
+
+ PUBWEAK BDMA_Channel0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel0_IRQHandler
+ B BDMA_Channel0_IRQHandler
+
+ PUBWEAK BDMA_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel1_IRQHandler
+ B BDMA_Channel1_IRQHandler
+
+ PUBWEAK BDMA_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel2_IRQHandler
+ B BDMA_Channel2_IRQHandler
+
+ PUBWEAK BDMA_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel3_IRQHandler
+ B BDMA_Channel3_IRQHandler
+
+ PUBWEAK BDMA_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel4_IRQHandler
+ B BDMA_Channel4_IRQHandler
+
+ PUBWEAK BDMA_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel5_IRQHandler
+ B BDMA_Channel5_IRQHandler
+
+ PUBWEAK BDMA_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel6_IRQHandler
+ B BDMA_Channel6_IRQHandler
+
+ PUBWEAK BDMA_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel7_IRQHandler
+ B BDMA_Channel7_IRQHandler
+
+ PUBWEAK COMP1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP1_IRQHandler
+ B COMP1_IRQHandler
+
+ PUBWEAK LPTIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+ B LPTIM2_IRQHandler
+
+ PUBWEAK LPTIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+ B LPTIM3_IRQHandler
+
+ PUBWEAK LPTIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM4_IRQHandler
+ B LPTIM4_IRQHandler
+
+ PUBWEAK LPTIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM5_IRQHandler
+ B LPTIM5_IRQHandler
+
+ PUBWEAK LPUART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+ B LPUART1_IRQHandler
+
+ PUBWEAK CRS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+ B CRS_IRQHandler
+
+ PUBWEAK ECC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ECC_IRQHandler
+ B ECC_IRQHandler
+
+ PUBWEAK SAI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI4_IRQHandler
+ B SAI4_IRQHandler
+
+ PUBWEAK DTS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DTS_IRQHandler
+ B DTS_IRQHandler
+
+ PUBWEAK WAKEUP_PIN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WAKEUP_PIN_IRQHandler
+ B WAKEUP_PIN_IRQHandler
+
+ PUBWEAK OCTOSPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI2_IRQHandler
+ B OCTOSPI2_IRQHandler
+
+ PUBWEAK FMAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMAC_IRQHandler
+ B FMAC_IRQHandler
+
+ PUBWEAK CORDIC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CORDIC_IRQHandler
+ B CORDIC_IRQHandler
+
+ PUBWEAK UART9_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART9_IRQHandler
+ B UART9_IRQHandler
+
+ PUBWEAK USART10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART10_IRQHandler
+ B USART10_IRQHandler
+
+ PUBWEAK I2C5_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C5_EV_IRQHandler
+ B I2C5_EV_IRQHandler
+
+ PUBWEAK I2C5_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C5_ER_IRQHandler
+ B I2C5_ER_IRQHandler
+
+ PUBWEAK FDCAN3_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN3_IT0_IRQHandler
+ B FDCAN3_IT0_IRQHandler
+
+ PUBWEAK FDCAN3_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN3_IT1_IRQHandler
+ B FDCAN3_IT1_IRQHandler
+
+ PUBWEAK TIM23_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM23_IRQHandler
+ B TIM23_IRQHandler
+
+ PUBWEAK TIM24_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM24_IRQHandler
+ B TIM24_IRQHandler
+
+ END
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h725xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h725xx.s new file mode 100644 index 0000000..8bc297b --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h725xx.s @@ -0,0 +1,982 @@ +;/********************************************************************************
+;* File Name : startup_stm32h725xx.s
+;* Author : MCD Application Team
+;* Description : STM32H725xx devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it)
+ DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_PSSI_IRQHandler ; DCMI, PSSI
+ DCD 0 ; Reserved
+ DCD RNG_IRQHandler ; Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD 0 ; Reserved
+ DCD OCTOSPI1_IRQHandler ; OCTOSPI1
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD 0 ; Reserved
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD 0 ; Reserved
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD 0 ; Reserved
+ DCD ADC3_IRQHandler ; ADC3 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP1_IRQHandler ; COMP1 global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
+ DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD 0 ; Reserved
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
+ DCD SAI4_IRQHandler ; SAI4 global interrupt
+ DCD DTS_IRQHandler ; Digital Temperature Sensor
+ DCD 0 ; Reserved
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+ DCD OCTOSPI2_IRQHandler ; OCTOSPI2 Interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FMAC_IRQHandler ; FMAC Interrupt
+ DCD CORDIC_IRQHandler ; CORDIC Interrupt
+ DCD UART9_IRQHandler ; UART9 Interrupt
+ DCD USART10_IRQHandler ; USART10 Interrupt
+ DCD I2C5_EV_IRQHandler ; I2C5 Event Interrupt
+ DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt
+ DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0
+ DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1
+ DCD TIM23_IRQHandler ; TIM23 global interrupt
+ DCD TIM24_IRQHandler ; TIM24 global interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_AVD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_AVD_IRQHandler
+ B PVD_AVD_IRQHandler
+
+ PUBWEAK TAMP_STAMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+ B TAMP_STAMP_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream0_IRQHandler
+ B DMA1_Stream0_IRQHandler
+
+ PUBWEAK DMA1_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream1_IRQHandler
+ B DMA1_Stream1_IRQHandler
+
+ PUBWEAK DMA1_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream2_IRQHandler
+ B DMA1_Stream2_IRQHandler
+
+ PUBWEAK DMA1_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream3_IRQHandler
+ B DMA1_Stream3_IRQHandler
+
+ PUBWEAK DMA1_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream4_IRQHandler
+ B DMA1_Stream4_IRQHandler
+
+ PUBWEAK DMA1_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream5_IRQHandler
+ B DMA1_Stream5_IRQHandler
+
+ PUBWEAK DMA1_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream6_IRQHandler
+ B DMA1_Stream6_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK FDCAN1_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+ B FDCAN1_IT0_IRQHandler
+
+ PUBWEAK FDCAN2_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT0_IRQHandler
+ B FDCAN2_IT0_IRQHandler
+
+ PUBWEAK FDCAN1_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+ B FDCAN1_IT1_IRQHandler
+
+ PUBWEAK FDCAN2_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT1_IRQHandler
+ B FDCAN2_IT1_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK TIM8_BRK_TIM12_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_TIM12_IRQHandler
+ B TIM8_BRK_TIM12_IRQHandler
+
+ PUBWEAK TIM8_UP_TIM13_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_TIM13_IRQHandler
+ B TIM8_UP_TIM13_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_TIM14_IRQHandler
+ B TIM8_TRG_COM_TIM14_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK DMA1_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream7_IRQHandler
+ B DMA1_Stream7_IRQHandler
+
+ PUBWEAK FMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+ B FMC_IRQHandler
+
+ PUBWEAK SDMMC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+ B SDMMC1_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream0_IRQHandler
+ B DMA2_Stream0_IRQHandler
+
+ PUBWEAK DMA2_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream1_IRQHandler
+ B DMA2_Stream1_IRQHandler
+
+ PUBWEAK DMA2_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream2_IRQHandler
+ B DMA2_Stream2_IRQHandler
+
+ PUBWEAK DMA2_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream3_IRQHandler
+ B DMA2_Stream3_IRQHandler
+
+ PUBWEAK DMA2_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream4_IRQHandler
+ B DMA2_Stream4_IRQHandler
+
+ PUBWEAK ETH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_IRQHandler
+ B ETH_IRQHandler
+
+ PUBWEAK ETH_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_WKUP_IRQHandler
+ B ETH_WKUP_IRQHandler
+
+ PUBWEAK FDCAN_CAL_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN_CAL_IRQHandler
+ B FDCAN_CAL_IRQHandler
+
+ PUBWEAK DMA2_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream5_IRQHandler
+ B DMA2_Stream5_IRQHandler
+
+ PUBWEAK DMA2_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream6_IRQHandler
+ B DMA2_Stream6_IRQHandler
+
+ PUBWEAK DMA2_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream7_IRQHandler
+ B DMA2_Stream7_IRQHandler
+
+ PUBWEAK USART6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler
+ B USART6_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_OUT_IRQHandler
+ B OTG_HS_EP1_OUT_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_IN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_IN_IRQHandler
+ B OTG_HS_EP1_IN_IRQHandler
+
+ PUBWEAK OTG_HS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_WKUP_IRQHandler
+ B OTG_HS_WKUP_IRQHandler
+
+ PUBWEAK OTG_HS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_IRQHandler
+ B OTG_HS_IRQHandler
+
+ PUBWEAK DCMI_PSSI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_PSSI_IRQHandler
+ B DCMI_PSSI_IRQHandler
+
+ PUBWEAK RNG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+ B RNG_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ PUBWEAK UART7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART7_IRQHandler
+ B UART7_IRQHandler
+
+ PUBWEAK UART8_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART8_IRQHandler
+ B UART8_IRQHandler
+
+ PUBWEAK SPI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+ B SPI4_IRQHandler
+
+ PUBWEAK SPI5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI5_IRQHandler
+ B SPI5_IRQHandler
+
+ PUBWEAK SPI6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI6_IRQHandler
+ B SPI6_IRQHandler
+
+ PUBWEAK SAI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+ B SAI1_IRQHandler
+
+ PUBWEAK LTDC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_IRQHandler
+ B LTDC_IRQHandler
+
+ PUBWEAK LTDC_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_ER_IRQHandler
+ B LTDC_ER_IRQHandler
+
+ PUBWEAK DMA2D_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+ B DMA2D_IRQHandler
+
+ PUBWEAK OCTOSPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI1_IRQHandler
+ B OCTOSPI1_IRQHandler
+
+ PUBWEAK LPTIM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+ B LPTIM1_IRQHandler
+
+ PUBWEAK CEC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler
+ B CEC_IRQHandler
+
+ PUBWEAK I2C4_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+ B I2C4_EV_IRQHandler
+
+ PUBWEAK I2C4_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+ B I2C4_ER_IRQHandler
+
+ PUBWEAK SPDIF_RX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPDIF_RX_IRQHandler
+ B SPDIF_RX_IRQHandler
+
+ PUBWEAK DMAMUX1_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+ B DMAMUX1_OVR_IRQHandler
+
+ PUBWEAK DFSDM1_FLT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT0_IRQHandler
+ B DFSDM1_FLT0_IRQHandler
+
+ PUBWEAK DFSDM1_FLT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+ B DFSDM1_FLT1_IRQHandler
+
+ PUBWEAK DFSDM1_FLT2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+ B DFSDM1_FLT2_IRQHandler
+
+ PUBWEAK DFSDM1_FLT3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+ B DFSDM1_FLT3_IRQHandler
+
+ PUBWEAK SWPMI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SWPMI1_IRQHandler
+ B SWPMI1_IRQHandler
+
+ PUBWEAK TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+ B TIM15_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK MDIOS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_WKUP_IRQHandler
+ B MDIOS_WKUP_IRQHandler
+
+ PUBWEAK MDIOS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_IRQHandler
+ B MDIOS_IRQHandler
+
+ PUBWEAK MDMA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDMA_IRQHandler
+ B MDMA_IRQHandler
+
+ PUBWEAK SDMMC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC2_IRQHandler
+ B SDMMC2_IRQHandler
+
+ PUBWEAK HSEM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM1_IRQHandler
+ B HSEM1_IRQHandler
+
+ PUBWEAK ADC3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC3_IRQHandler
+ B ADC3_IRQHandler
+
+ PUBWEAK DMAMUX2_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX2_OVR_IRQHandler
+ B DMAMUX2_OVR_IRQHandler
+
+ PUBWEAK BDMA_Channel0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel0_IRQHandler
+ B BDMA_Channel0_IRQHandler
+
+ PUBWEAK BDMA_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel1_IRQHandler
+ B BDMA_Channel1_IRQHandler
+
+ PUBWEAK BDMA_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel2_IRQHandler
+ B BDMA_Channel2_IRQHandler
+
+ PUBWEAK BDMA_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel3_IRQHandler
+ B BDMA_Channel3_IRQHandler
+
+ PUBWEAK BDMA_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel4_IRQHandler
+ B BDMA_Channel4_IRQHandler
+
+ PUBWEAK BDMA_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel5_IRQHandler
+ B BDMA_Channel5_IRQHandler
+
+ PUBWEAK BDMA_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel6_IRQHandler
+ B BDMA_Channel6_IRQHandler
+
+ PUBWEAK BDMA_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel7_IRQHandler
+ B BDMA_Channel7_IRQHandler
+
+ PUBWEAK COMP1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP1_IRQHandler
+ B COMP1_IRQHandler
+
+ PUBWEAK LPTIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+ B LPTIM2_IRQHandler
+
+ PUBWEAK LPTIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+ B LPTIM3_IRQHandler
+
+ PUBWEAK LPTIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM4_IRQHandler
+ B LPTIM4_IRQHandler
+
+ PUBWEAK LPTIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM5_IRQHandler
+ B LPTIM5_IRQHandler
+
+ PUBWEAK LPUART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+ B LPUART1_IRQHandler
+
+ PUBWEAK CRS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+ B CRS_IRQHandler
+
+ PUBWEAK ECC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ECC_IRQHandler
+ B ECC_IRQHandler
+
+ PUBWEAK SAI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI4_IRQHandler
+ B SAI4_IRQHandler
+
+ PUBWEAK DTS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DTS_IRQHandler
+ B DTS_IRQHandler
+
+ PUBWEAK WAKEUP_PIN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WAKEUP_PIN_IRQHandler
+ B WAKEUP_PIN_IRQHandler
+
+ PUBWEAK OCTOSPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI2_IRQHandler
+ B OCTOSPI2_IRQHandler
+
+ PUBWEAK FMAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMAC_IRQHandler
+ B FMAC_IRQHandler
+
+ PUBWEAK CORDIC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CORDIC_IRQHandler
+ B CORDIC_IRQHandler
+
+ PUBWEAK UART9_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART9_IRQHandler
+ B UART9_IRQHandler
+
+ PUBWEAK USART10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART10_IRQHandler
+ B USART10_IRQHandler
+
+ PUBWEAK I2C5_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C5_EV_IRQHandler
+ B I2C5_EV_IRQHandler
+
+ PUBWEAK I2C5_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C5_ER_IRQHandler
+ B I2C5_ER_IRQHandler
+
+ PUBWEAK FDCAN3_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN3_IT0_IRQHandler
+ B FDCAN3_IT0_IRQHandler
+
+ PUBWEAK FDCAN3_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN3_IT1_IRQHandler
+ B FDCAN3_IT1_IRQHandler
+
+ PUBWEAK TIM23_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM23_IRQHandler
+ B TIM23_IRQHandler
+
+ PUBWEAK TIM24_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM24_IRQHandler
+ B TIM24_IRQHandler
+
+ END
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h730xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h730xx.s new file mode 100644 index 0000000..69d1761 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h730xx.s @@ -0,0 +1,997 @@ +;/********************************************************************************
+;* File Name : startup_stm32h730xx.s
+;* Author : MCD Application Team
+;* Description : STM32H730xx devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it)
+ DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_PSSI_IRQHandler ; DCMI, PSSI
+ DCD CRYP_IRQHandler ; CRYP crypto
+ DCD HASH_RNG_IRQHandler ; Hash and Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD 0 ; Reserved
+ DCD OCTOSPI1_IRQHandler ; OCTOSPI1
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD 0 ; Reserved
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD 0 ; Reserved
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD 0 ; Reserved
+ DCD ADC3_IRQHandler ; ADC3 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP1_IRQHandler ; COMP1 global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
+ DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD 0 ; Reserved
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
+ DCD SAI4_IRQHandler ; SAI4 global interrupt
+ DCD DTS_IRQHandler ; Digital Temperature Sensor
+ DCD 0 ; Reserved
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+ DCD OCTOSPI2_IRQHandler ; OCTOSPI2 Interrupt
+ DCD OTFDEC1_IRQHandler ; OTFDEC1 Interrupt
+ DCD OTFDEC2_IRQHandler ; OTFDEC2 Interrupt
+ DCD FMAC_IRQHandler ; FMAC Interrupt
+ DCD CORDIC_IRQHandler ; CORDIC Interrupt
+ DCD UART9_IRQHandler ; UART9 Interrupt
+ DCD USART10_IRQHandler ; USART10 Interrupt
+ DCD I2C5_EV_IRQHandler ; I2C5 Event Interrupt
+ DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt
+ DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0
+ DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1
+ DCD TIM23_IRQHandler ; TIM23 global interrupt
+ DCD TIM24_IRQHandler ; TIM24 global interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_AVD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_AVD_IRQHandler
+ B PVD_AVD_IRQHandler
+
+ PUBWEAK TAMP_STAMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+ B TAMP_STAMP_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream0_IRQHandler
+ B DMA1_Stream0_IRQHandler
+
+ PUBWEAK DMA1_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream1_IRQHandler
+ B DMA1_Stream1_IRQHandler
+
+ PUBWEAK DMA1_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream2_IRQHandler
+ B DMA1_Stream2_IRQHandler
+
+ PUBWEAK DMA1_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream3_IRQHandler
+ B DMA1_Stream3_IRQHandler
+
+ PUBWEAK DMA1_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream4_IRQHandler
+ B DMA1_Stream4_IRQHandler
+
+ PUBWEAK DMA1_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream5_IRQHandler
+ B DMA1_Stream5_IRQHandler
+
+ PUBWEAK DMA1_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream6_IRQHandler
+ B DMA1_Stream6_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK FDCAN1_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+ B FDCAN1_IT0_IRQHandler
+
+ PUBWEAK FDCAN2_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT0_IRQHandler
+ B FDCAN2_IT0_IRQHandler
+
+ PUBWEAK FDCAN1_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+ B FDCAN1_IT1_IRQHandler
+
+ PUBWEAK FDCAN2_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT1_IRQHandler
+ B FDCAN2_IT1_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK TIM8_BRK_TIM12_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_TIM12_IRQHandler
+ B TIM8_BRK_TIM12_IRQHandler
+
+ PUBWEAK TIM8_UP_TIM13_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_TIM13_IRQHandler
+ B TIM8_UP_TIM13_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_TIM14_IRQHandler
+ B TIM8_TRG_COM_TIM14_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK DMA1_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream7_IRQHandler
+ B DMA1_Stream7_IRQHandler
+
+ PUBWEAK FMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+ B FMC_IRQHandler
+
+ PUBWEAK SDMMC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+ B SDMMC1_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream0_IRQHandler
+ B DMA2_Stream0_IRQHandler
+
+ PUBWEAK DMA2_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream1_IRQHandler
+ B DMA2_Stream1_IRQHandler
+
+ PUBWEAK DMA2_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream2_IRQHandler
+ B DMA2_Stream2_IRQHandler
+
+ PUBWEAK DMA2_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream3_IRQHandler
+ B DMA2_Stream3_IRQHandler
+
+ PUBWEAK DMA2_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream4_IRQHandler
+ B DMA2_Stream4_IRQHandler
+
+ PUBWEAK ETH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_IRQHandler
+ B ETH_IRQHandler
+
+ PUBWEAK ETH_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_WKUP_IRQHandler
+ B ETH_WKUP_IRQHandler
+
+ PUBWEAK FDCAN_CAL_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN_CAL_IRQHandler
+ B FDCAN_CAL_IRQHandler
+
+ PUBWEAK DMA2_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream5_IRQHandler
+ B DMA2_Stream5_IRQHandler
+
+ PUBWEAK DMA2_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream6_IRQHandler
+ B DMA2_Stream6_IRQHandler
+
+ PUBWEAK DMA2_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream7_IRQHandler
+ B DMA2_Stream7_IRQHandler
+
+ PUBWEAK USART6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler
+ B USART6_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_OUT_IRQHandler
+ B OTG_HS_EP1_OUT_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_IN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_IN_IRQHandler
+ B OTG_HS_EP1_IN_IRQHandler
+
+ PUBWEAK OTG_HS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_WKUP_IRQHandler
+ B OTG_HS_WKUP_IRQHandler
+
+ PUBWEAK OTG_HS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_IRQHandler
+ B OTG_HS_IRQHandler
+
+ PUBWEAK DCMI_PSSI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_PSSI_IRQHandler
+ B DCMI_PSSI_IRQHandler
+
+ PUBWEAK CRYP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CRYP_IRQHandler
+ B CRYP_IRQHandler
+
+ PUBWEAK HASH_RNG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HASH_RNG_IRQHandler
+ B HASH_RNG_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ PUBWEAK UART7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART7_IRQHandler
+ B UART7_IRQHandler
+
+ PUBWEAK UART8_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART8_IRQHandler
+ B UART8_IRQHandler
+
+ PUBWEAK SPI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+ B SPI4_IRQHandler
+
+ PUBWEAK SPI5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI5_IRQHandler
+ B SPI5_IRQHandler
+
+ PUBWEAK SPI6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI6_IRQHandler
+ B SPI6_IRQHandler
+
+ PUBWEAK SAI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+ B SAI1_IRQHandler
+
+ PUBWEAK LTDC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_IRQHandler
+ B LTDC_IRQHandler
+
+ PUBWEAK LTDC_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_ER_IRQHandler
+ B LTDC_ER_IRQHandler
+
+ PUBWEAK DMA2D_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+ B DMA2D_IRQHandler
+
+ PUBWEAK OCTOSPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI1_IRQHandler
+ B OCTOSPI1_IRQHandler
+
+ PUBWEAK LPTIM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+ B LPTIM1_IRQHandler
+
+ PUBWEAK CEC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler
+ B CEC_IRQHandler
+
+ PUBWEAK I2C4_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+ B I2C4_EV_IRQHandler
+
+ PUBWEAK I2C4_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+ B I2C4_ER_IRQHandler
+
+ PUBWEAK SPDIF_RX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPDIF_RX_IRQHandler
+ B SPDIF_RX_IRQHandler
+
+ PUBWEAK DMAMUX1_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+ B DMAMUX1_OVR_IRQHandler
+
+ PUBWEAK DFSDM1_FLT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT0_IRQHandler
+ B DFSDM1_FLT0_IRQHandler
+
+ PUBWEAK DFSDM1_FLT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+ B DFSDM1_FLT1_IRQHandler
+
+ PUBWEAK DFSDM1_FLT2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+ B DFSDM1_FLT2_IRQHandler
+
+ PUBWEAK DFSDM1_FLT3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+ B DFSDM1_FLT3_IRQHandler
+
+ PUBWEAK SWPMI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SWPMI1_IRQHandler
+ B SWPMI1_IRQHandler
+
+ PUBWEAK TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+ B TIM15_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK MDIOS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_WKUP_IRQHandler
+ B MDIOS_WKUP_IRQHandler
+
+ PUBWEAK MDIOS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_IRQHandler
+ B MDIOS_IRQHandler
+
+ PUBWEAK MDMA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDMA_IRQHandler
+ B MDMA_IRQHandler
+
+ PUBWEAK SDMMC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC2_IRQHandler
+ B SDMMC2_IRQHandler
+
+ PUBWEAK HSEM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM1_IRQHandler
+ B HSEM1_IRQHandler
+
+ PUBWEAK ADC3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC3_IRQHandler
+ B ADC3_IRQHandler
+
+ PUBWEAK DMAMUX2_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX2_OVR_IRQHandler
+ B DMAMUX2_OVR_IRQHandler
+
+ PUBWEAK BDMA_Channel0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel0_IRQHandler
+ B BDMA_Channel0_IRQHandler
+
+ PUBWEAK BDMA_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel1_IRQHandler
+ B BDMA_Channel1_IRQHandler
+
+ PUBWEAK BDMA_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel2_IRQHandler
+ B BDMA_Channel2_IRQHandler
+
+ PUBWEAK BDMA_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel3_IRQHandler
+ B BDMA_Channel3_IRQHandler
+
+ PUBWEAK BDMA_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel4_IRQHandler
+ B BDMA_Channel4_IRQHandler
+
+ PUBWEAK BDMA_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel5_IRQHandler
+ B BDMA_Channel5_IRQHandler
+
+ PUBWEAK BDMA_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel6_IRQHandler
+ B BDMA_Channel6_IRQHandler
+
+ PUBWEAK BDMA_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel7_IRQHandler
+ B BDMA_Channel7_IRQHandler
+
+ PUBWEAK COMP1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP1_IRQHandler
+ B COMP1_IRQHandler
+
+ PUBWEAK LPTIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+ B LPTIM2_IRQHandler
+
+ PUBWEAK LPTIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+ B LPTIM3_IRQHandler
+
+ PUBWEAK LPTIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM4_IRQHandler
+ B LPTIM4_IRQHandler
+
+ PUBWEAK LPTIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM5_IRQHandler
+ B LPTIM5_IRQHandler
+
+ PUBWEAK LPUART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+ B LPUART1_IRQHandler
+
+ PUBWEAK CRS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+ B CRS_IRQHandler
+
+ PUBWEAK ECC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ECC_IRQHandler
+ B ECC_IRQHandler
+
+ PUBWEAK SAI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI4_IRQHandler
+ B SAI4_IRQHandler
+
+ PUBWEAK DTS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DTS_IRQHandler
+ B DTS_IRQHandler
+
+ PUBWEAK WAKEUP_PIN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WAKEUP_PIN_IRQHandler
+ B WAKEUP_PIN_IRQHandler
+
+ PUBWEAK OCTOSPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI2_IRQHandler
+ B OCTOSPI2_IRQHandler
+
+ PUBWEAK OTFDEC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTFDEC1_IRQHandler
+ B OTFDEC1_IRQHandler
+
+ PUBWEAK OTFDEC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTFDEC2_IRQHandler
+ B OTFDEC2_IRQHandler
+
+ PUBWEAK FMAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMAC_IRQHandler
+ B FMAC_IRQHandler
+
+ PUBWEAK CORDIC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CORDIC_IRQHandler
+ B CORDIC_IRQHandler
+
+ PUBWEAK UART9_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART9_IRQHandler
+ B UART9_IRQHandler
+
+ PUBWEAK USART10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART10_IRQHandler
+ B USART10_IRQHandler
+
+ PUBWEAK I2C5_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C5_EV_IRQHandler
+ B I2C5_EV_IRQHandler
+
+ PUBWEAK I2C5_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C5_ER_IRQHandler
+ B I2C5_ER_IRQHandler
+
+ PUBWEAK FDCAN3_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN3_IT0_IRQHandler
+ B FDCAN3_IT0_IRQHandler
+
+ PUBWEAK FDCAN3_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN3_IT1_IRQHandler
+ B FDCAN3_IT1_IRQHandler
+
+ PUBWEAK TIM23_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM23_IRQHandler
+ B TIM23_IRQHandler
+
+ PUBWEAK TIM24_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM24_IRQHandler
+ B TIM24_IRQHandler
+
+ END
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h730xxq.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h730xxq.s new file mode 100644 index 0000000..fc5cbca --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h730xxq.s @@ -0,0 +1,997 @@ +;/********************************************************************************
+;* File Name : startup_stm32h730xxq.s
+;* Author : MCD Application Team
+;* Description : STM32H730xxQ devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it)
+ DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_PSSI_IRQHandler ; DCMI, PSSI
+ DCD CRYP_IRQHandler ; CRYP crypto
+ DCD HASH_RNG_IRQHandler ; Hash and Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD 0 ; Reserved
+ DCD OCTOSPI1_IRQHandler ; OCTOSPI1
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD 0 ; Reserved
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD 0 ; Reserved
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD 0 ; Reserved
+ DCD ADC3_IRQHandler ; ADC3 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP1_IRQHandler ; COMP1 global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
+ DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD 0 ; Reserved
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
+ DCD SAI4_IRQHandler ; SAI4 global interrupt
+ DCD DTS_IRQHandler ; Digital Temperature Sensor
+ DCD 0 ; Reserved
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+ DCD OCTOSPI2_IRQHandler ; OCTOSPI2 Interrupt
+ DCD OTFDEC1_IRQHandler ; OTFDEC1 Interrupt
+ DCD OTFDEC2_IRQHandler ; OTFDEC2 Interrupt
+ DCD FMAC_IRQHandler ; FMAC Interrupt
+ DCD CORDIC_IRQHandler ; CORDIC Interrupt
+ DCD UART9_IRQHandler ; UART9 Interrupt
+ DCD USART10_IRQHandler ; USART10 Interrupt
+ DCD I2C5_EV_IRQHandler ; I2C5 Event Interrupt
+ DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt
+ DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0
+ DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1
+ DCD TIM23_IRQHandler ; TIM23 global interrupt
+ DCD TIM24_IRQHandler ; TIM24 global interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_AVD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_AVD_IRQHandler
+ B PVD_AVD_IRQHandler
+
+ PUBWEAK TAMP_STAMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+ B TAMP_STAMP_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream0_IRQHandler
+ B DMA1_Stream0_IRQHandler
+
+ PUBWEAK DMA1_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream1_IRQHandler
+ B DMA1_Stream1_IRQHandler
+
+ PUBWEAK DMA1_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream2_IRQHandler
+ B DMA1_Stream2_IRQHandler
+
+ PUBWEAK DMA1_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream3_IRQHandler
+ B DMA1_Stream3_IRQHandler
+
+ PUBWEAK DMA1_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream4_IRQHandler
+ B DMA1_Stream4_IRQHandler
+
+ PUBWEAK DMA1_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream5_IRQHandler
+ B DMA1_Stream5_IRQHandler
+
+ PUBWEAK DMA1_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream6_IRQHandler
+ B DMA1_Stream6_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK FDCAN1_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+ B FDCAN1_IT0_IRQHandler
+
+ PUBWEAK FDCAN2_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT0_IRQHandler
+ B FDCAN2_IT0_IRQHandler
+
+ PUBWEAK FDCAN1_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+ B FDCAN1_IT1_IRQHandler
+
+ PUBWEAK FDCAN2_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT1_IRQHandler
+ B FDCAN2_IT1_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK TIM8_BRK_TIM12_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_TIM12_IRQHandler
+ B TIM8_BRK_TIM12_IRQHandler
+
+ PUBWEAK TIM8_UP_TIM13_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_TIM13_IRQHandler
+ B TIM8_UP_TIM13_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_TIM14_IRQHandler
+ B TIM8_TRG_COM_TIM14_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK DMA1_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream7_IRQHandler
+ B DMA1_Stream7_IRQHandler
+
+ PUBWEAK FMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+ B FMC_IRQHandler
+
+ PUBWEAK SDMMC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+ B SDMMC1_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream0_IRQHandler
+ B DMA2_Stream0_IRQHandler
+
+ PUBWEAK DMA2_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream1_IRQHandler
+ B DMA2_Stream1_IRQHandler
+
+ PUBWEAK DMA2_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream2_IRQHandler
+ B DMA2_Stream2_IRQHandler
+
+ PUBWEAK DMA2_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream3_IRQHandler
+ B DMA2_Stream3_IRQHandler
+
+ PUBWEAK DMA2_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream4_IRQHandler
+ B DMA2_Stream4_IRQHandler
+
+ PUBWEAK ETH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_IRQHandler
+ B ETH_IRQHandler
+
+ PUBWEAK ETH_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_WKUP_IRQHandler
+ B ETH_WKUP_IRQHandler
+
+ PUBWEAK FDCAN_CAL_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN_CAL_IRQHandler
+ B FDCAN_CAL_IRQHandler
+
+ PUBWEAK DMA2_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream5_IRQHandler
+ B DMA2_Stream5_IRQHandler
+
+ PUBWEAK DMA2_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream6_IRQHandler
+ B DMA2_Stream6_IRQHandler
+
+ PUBWEAK DMA2_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream7_IRQHandler
+ B DMA2_Stream7_IRQHandler
+
+ PUBWEAK USART6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler
+ B USART6_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_OUT_IRQHandler
+ B OTG_HS_EP1_OUT_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_IN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_IN_IRQHandler
+ B OTG_HS_EP1_IN_IRQHandler
+
+ PUBWEAK OTG_HS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_WKUP_IRQHandler
+ B OTG_HS_WKUP_IRQHandler
+
+ PUBWEAK OTG_HS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_IRQHandler
+ B OTG_HS_IRQHandler
+
+ PUBWEAK DCMI_PSSI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_PSSI_IRQHandler
+ B DCMI_PSSI_IRQHandler
+
+ PUBWEAK CRYP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CRYP_IRQHandler
+ B CRYP_IRQHandler
+
+ PUBWEAK HASH_RNG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HASH_RNG_IRQHandler
+ B HASH_RNG_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ PUBWEAK UART7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART7_IRQHandler
+ B UART7_IRQHandler
+
+ PUBWEAK UART8_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART8_IRQHandler
+ B UART8_IRQHandler
+
+ PUBWEAK SPI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+ B SPI4_IRQHandler
+
+ PUBWEAK SPI5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI5_IRQHandler
+ B SPI5_IRQHandler
+
+ PUBWEAK SPI6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI6_IRQHandler
+ B SPI6_IRQHandler
+
+ PUBWEAK SAI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+ B SAI1_IRQHandler
+
+ PUBWEAK LTDC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_IRQHandler
+ B LTDC_IRQHandler
+
+ PUBWEAK LTDC_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_ER_IRQHandler
+ B LTDC_ER_IRQHandler
+
+ PUBWEAK DMA2D_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+ B DMA2D_IRQHandler
+
+ PUBWEAK OCTOSPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI1_IRQHandler
+ B OCTOSPI1_IRQHandler
+
+ PUBWEAK LPTIM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+ B LPTIM1_IRQHandler
+
+ PUBWEAK CEC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler
+ B CEC_IRQHandler
+
+ PUBWEAK I2C4_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+ B I2C4_EV_IRQHandler
+
+ PUBWEAK I2C4_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+ B I2C4_ER_IRQHandler
+
+ PUBWEAK SPDIF_RX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPDIF_RX_IRQHandler
+ B SPDIF_RX_IRQHandler
+
+ PUBWEAK DMAMUX1_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+ B DMAMUX1_OVR_IRQHandler
+
+ PUBWEAK DFSDM1_FLT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT0_IRQHandler
+ B DFSDM1_FLT0_IRQHandler
+
+ PUBWEAK DFSDM1_FLT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+ B DFSDM1_FLT1_IRQHandler
+
+ PUBWEAK DFSDM1_FLT2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+ B DFSDM1_FLT2_IRQHandler
+
+ PUBWEAK DFSDM1_FLT3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+ B DFSDM1_FLT3_IRQHandler
+
+ PUBWEAK SWPMI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SWPMI1_IRQHandler
+ B SWPMI1_IRQHandler
+
+ PUBWEAK TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+ B TIM15_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK MDIOS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_WKUP_IRQHandler
+ B MDIOS_WKUP_IRQHandler
+
+ PUBWEAK MDIOS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_IRQHandler
+ B MDIOS_IRQHandler
+
+ PUBWEAK MDMA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDMA_IRQHandler
+ B MDMA_IRQHandler
+
+ PUBWEAK SDMMC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC2_IRQHandler
+ B SDMMC2_IRQHandler
+
+ PUBWEAK HSEM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM1_IRQHandler
+ B HSEM1_IRQHandler
+
+ PUBWEAK ADC3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC3_IRQHandler
+ B ADC3_IRQHandler
+
+ PUBWEAK DMAMUX2_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX2_OVR_IRQHandler
+ B DMAMUX2_OVR_IRQHandler
+
+ PUBWEAK BDMA_Channel0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel0_IRQHandler
+ B BDMA_Channel0_IRQHandler
+
+ PUBWEAK BDMA_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel1_IRQHandler
+ B BDMA_Channel1_IRQHandler
+
+ PUBWEAK BDMA_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel2_IRQHandler
+ B BDMA_Channel2_IRQHandler
+
+ PUBWEAK BDMA_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel3_IRQHandler
+ B BDMA_Channel3_IRQHandler
+
+ PUBWEAK BDMA_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel4_IRQHandler
+ B BDMA_Channel4_IRQHandler
+
+ PUBWEAK BDMA_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel5_IRQHandler
+ B BDMA_Channel5_IRQHandler
+
+ PUBWEAK BDMA_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel6_IRQHandler
+ B BDMA_Channel6_IRQHandler
+
+ PUBWEAK BDMA_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel7_IRQHandler
+ B BDMA_Channel7_IRQHandler
+
+ PUBWEAK COMP1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP1_IRQHandler
+ B COMP1_IRQHandler
+
+ PUBWEAK LPTIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+ B LPTIM2_IRQHandler
+
+ PUBWEAK LPTIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+ B LPTIM3_IRQHandler
+
+ PUBWEAK LPTIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM4_IRQHandler
+ B LPTIM4_IRQHandler
+
+ PUBWEAK LPTIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM5_IRQHandler
+ B LPTIM5_IRQHandler
+
+ PUBWEAK LPUART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+ B LPUART1_IRQHandler
+
+ PUBWEAK CRS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+ B CRS_IRQHandler
+
+ PUBWEAK ECC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ECC_IRQHandler
+ B ECC_IRQHandler
+
+ PUBWEAK SAI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI4_IRQHandler
+ B SAI4_IRQHandler
+
+ PUBWEAK DTS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DTS_IRQHandler
+ B DTS_IRQHandler
+
+ PUBWEAK WAKEUP_PIN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WAKEUP_PIN_IRQHandler
+ B WAKEUP_PIN_IRQHandler
+
+ PUBWEAK OCTOSPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI2_IRQHandler
+ B OCTOSPI2_IRQHandler
+
+ PUBWEAK OTFDEC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTFDEC1_IRQHandler
+ B OTFDEC1_IRQHandler
+
+ PUBWEAK OTFDEC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTFDEC2_IRQHandler
+ B OTFDEC2_IRQHandler
+
+ PUBWEAK FMAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMAC_IRQHandler
+ B FMAC_IRQHandler
+
+ PUBWEAK CORDIC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CORDIC_IRQHandler
+ B CORDIC_IRQHandler
+
+ PUBWEAK UART9_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART9_IRQHandler
+ B UART9_IRQHandler
+
+ PUBWEAK USART10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART10_IRQHandler
+ B USART10_IRQHandler
+
+ PUBWEAK I2C5_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C5_EV_IRQHandler
+ B I2C5_EV_IRQHandler
+
+ PUBWEAK I2C5_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C5_ER_IRQHandler
+ B I2C5_ER_IRQHandler
+
+ PUBWEAK FDCAN3_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN3_IT0_IRQHandler
+ B FDCAN3_IT0_IRQHandler
+
+ PUBWEAK FDCAN3_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN3_IT1_IRQHandler
+ B FDCAN3_IT1_IRQHandler
+
+ PUBWEAK TIM23_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM23_IRQHandler
+ B TIM23_IRQHandler
+
+ PUBWEAK TIM24_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM24_IRQHandler
+ B TIM24_IRQHandler
+
+ END
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h733xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h733xx.s new file mode 100644 index 0000000..eefbc94 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h733xx.s @@ -0,0 +1,997 @@ +;/********************************************************************************
+;* File Name : startup_stm32h733xx.s
+;* Author : MCD Application Team
+;* Description : STM32H733xx devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it)
+ DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_PSSI_IRQHandler ; DCMI, PSSI
+ DCD CRYP_IRQHandler ; CRYP crypto
+ DCD HASH_RNG_IRQHandler ; Hash and Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD 0 ; Reserved
+ DCD OCTOSPI1_IRQHandler ; OCTOSPI1
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD 0 ; Reserved
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD 0 ; Reserved
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD 0 ; Reserved
+ DCD ADC3_IRQHandler ; ADC3 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP1_IRQHandler ; COMP1 global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
+ DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD 0 ; Reserved
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
+ DCD SAI4_IRQHandler ; SAI4 global interrupt
+ DCD DTS_IRQHandler ; Digital Temperature Sensor
+ DCD 0 ; Reserved
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+ DCD OCTOSPI2_IRQHandler ; OCTOSPI2 Interrupt
+ DCD OTFDEC1_IRQHandler ; OTFDEC1 Interrupt
+ DCD OTFDEC2_IRQHandler ; OTFDEC2 Interrupt
+ DCD FMAC_IRQHandler ; FMAC Interrupt
+ DCD CORDIC_IRQHandler ; CORDIC Interrupt
+ DCD UART9_IRQHandler ; UART9 Interrupt
+ DCD USART10_IRQHandler ; USART10 Interrupt
+ DCD I2C5_EV_IRQHandler ; I2C5 Event Interrupt
+ DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt
+ DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0
+ DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1
+ DCD TIM23_IRQHandler ; TIM23 global interrupt
+ DCD TIM24_IRQHandler ; TIM24 global interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_AVD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_AVD_IRQHandler
+ B PVD_AVD_IRQHandler
+
+ PUBWEAK TAMP_STAMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+ B TAMP_STAMP_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream0_IRQHandler
+ B DMA1_Stream0_IRQHandler
+
+ PUBWEAK DMA1_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream1_IRQHandler
+ B DMA1_Stream1_IRQHandler
+
+ PUBWEAK DMA1_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream2_IRQHandler
+ B DMA1_Stream2_IRQHandler
+
+ PUBWEAK DMA1_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream3_IRQHandler
+ B DMA1_Stream3_IRQHandler
+
+ PUBWEAK DMA1_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream4_IRQHandler
+ B DMA1_Stream4_IRQHandler
+
+ PUBWEAK DMA1_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream5_IRQHandler
+ B DMA1_Stream5_IRQHandler
+
+ PUBWEAK DMA1_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream6_IRQHandler
+ B DMA1_Stream6_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK FDCAN1_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+ B FDCAN1_IT0_IRQHandler
+
+ PUBWEAK FDCAN2_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT0_IRQHandler
+ B FDCAN2_IT0_IRQHandler
+
+ PUBWEAK FDCAN1_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+ B FDCAN1_IT1_IRQHandler
+
+ PUBWEAK FDCAN2_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT1_IRQHandler
+ B FDCAN2_IT1_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK TIM8_BRK_TIM12_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_TIM12_IRQHandler
+ B TIM8_BRK_TIM12_IRQHandler
+
+ PUBWEAK TIM8_UP_TIM13_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_TIM13_IRQHandler
+ B TIM8_UP_TIM13_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_TIM14_IRQHandler
+ B TIM8_TRG_COM_TIM14_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK DMA1_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream7_IRQHandler
+ B DMA1_Stream7_IRQHandler
+
+ PUBWEAK FMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+ B FMC_IRQHandler
+
+ PUBWEAK SDMMC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+ B SDMMC1_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream0_IRQHandler
+ B DMA2_Stream0_IRQHandler
+
+ PUBWEAK DMA2_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream1_IRQHandler
+ B DMA2_Stream1_IRQHandler
+
+ PUBWEAK DMA2_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream2_IRQHandler
+ B DMA2_Stream2_IRQHandler
+
+ PUBWEAK DMA2_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream3_IRQHandler
+ B DMA2_Stream3_IRQHandler
+
+ PUBWEAK DMA2_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream4_IRQHandler
+ B DMA2_Stream4_IRQHandler
+
+ PUBWEAK ETH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_IRQHandler
+ B ETH_IRQHandler
+
+ PUBWEAK ETH_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_WKUP_IRQHandler
+ B ETH_WKUP_IRQHandler
+
+ PUBWEAK FDCAN_CAL_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN_CAL_IRQHandler
+ B FDCAN_CAL_IRQHandler
+
+ PUBWEAK DMA2_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream5_IRQHandler
+ B DMA2_Stream5_IRQHandler
+
+ PUBWEAK DMA2_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream6_IRQHandler
+ B DMA2_Stream6_IRQHandler
+
+ PUBWEAK DMA2_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream7_IRQHandler
+ B DMA2_Stream7_IRQHandler
+
+ PUBWEAK USART6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler
+ B USART6_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_OUT_IRQHandler
+ B OTG_HS_EP1_OUT_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_IN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_IN_IRQHandler
+ B OTG_HS_EP1_IN_IRQHandler
+
+ PUBWEAK OTG_HS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_WKUP_IRQHandler
+ B OTG_HS_WKUP_IRQHandler
+
+ PUBWEAK OTG_HS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_IRQHandler
+ B OTG_HS_IRQHandler
+
+ PUBWEAK DCMI_PSSI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_PSSI_IRQHandler
+ B DCMI_PSSI_IRQHandler
+
+ PUBWEAK CRYP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CRYP_IRQHandler
+ B CRYP_IRQHandler
+
+ PUBWEAK HASH_RNG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HASH_RNG_IRQHandler
+ B HASH_RNG_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ PUBWEAK UART7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART7_IRQHandler
+ B UART7_IRQHandler
+
+ PUBWEAK UART8_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART8_IRQHandler
+ B UART8_IRQHandler
+
+ PUBWEAK SPI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+ B SPI4_IRQHandler
+
+ PUBWEAK SPI5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI5_IRQHandler
+ B SPI5_IRQHandler
+
+ PUBWEAK SPI6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI6_IRQHandler
+ B SPI6_IRQHandler
+
+ PUBWEAK SAI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+ B SAI1_IRQHandler
+
+ PUBWEAK LTDC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_IRQHandler
+ B LTDC_IRQHandler
+
+ PUBWEAK LTDC_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_ER_IRQHandler
+ B LTDC_ER_IRQHandler
+
+ PUBWEAK DMA2D_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+ B DMA2D_IRQHandler
+
+ PUBWEAK OCTOSPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI1_IRQHandler
+ B OCTOSPI1_IRQHandler
+
+ PUBWEAK LPTIM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+ B LPTIM1_IRQHandler
+
+ PUBWEAK CEC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler
+ B CEC_IRQHandler
+
+ PUBWEAK I2C4_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+ B I2C4_EV_IRQHandler
+
+ PUBWEAK I2C4_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+ B I2C4_ER_IRQHandler
+
+ PUBWEAK SPDIF_RX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPDIF_RX_IRQHandler
+ B SPDIF_RX_IRQHandler
+
+ PUBWEAK DMAMUX1_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+ B DMAMUX1_OVR_IRQHandler
+
+ PUBWEAK DFSDM1_FLT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT0_IRQHandler
+ B DFSDM1_FLT0_IRQHandler
+
+ PUBWEAK DFSDM1_FLT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+ B DFSDM1_FLT1_IRQHandler
+
+ PUBWEAK DFSDM1_FLT2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+ B DFSDM1_FLT2_IRQHandler
+
+ PUBWEAK DFSDM1_FLT3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+ B DFSDM1_FLT3_IRQHandler
+
+ PUBWEAK SWPMI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SWPMI1_IRQHandler
+ B SWPMI1_IRQHandler
+
+ PUBWEAK TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+ B TIM15_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK MDIOS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_WKUP_IRQHandler
+ B MDIOS_WKUP_IRQHandler
+
+ PUBWEAK MDIOS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_IRQHandler
+ B MDIOS_IRQHandler
+
+ PUBWEAK MDMA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDMA_IRQHandler
+ B MDMA_IRQHandler
+
+ PUBWEAK SDMMC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC2_IRQHandler
+ B SDMMC2_IRQHandler
+
+ PUBWEAK HSEM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM1_IRQHandler
+ B HSEM1_IRQHandler
+
+ PUBWEAK ADC3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC3_IRQHandler
+ B ADC3_IRQHandler
+
+ PUBWEAK DMAMUX2_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX2_OVR_IRQHandler
+ B DMAMUX2_OVR_IRQHandler
+
+ PUBWEAK BDMA_Channel0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel0_IRQHandler
+ B BDMA_Channel0_IRQHandler
+
+ PUBWEAK BDMA_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel1_IRQHandler
+ B BDMA_Channel1_IRQHandler
+
+ PUBWEAK BDMA_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel2_IRQHandler
+ B BDMA_Channel2_IRQHandler
+
+ PUBWEAK BDMA_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel3_IRQHandler
+ B BDMA_Channel3_IRQHandler
+
+ PUBWEAK BDMA_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel4_IRQHandler
+ B BDMA_Channel4_IRQHandler
+
+ PUBWEAK BDMA_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel5_IRQHandler
+ B BDMA_Channel5_IRQHandler
+
+ PUBWEAK BDMA_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel6_IRQHandler
+ B BDMA_Channel6_IRQHandler
+
+ PUBWEAK BDMA_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel7_IRQHandler
+ B BDMA_Channel7_IRQHandler
+
+ PUBWEAK COMP1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP1_IRQHandler
+ B COMP1_IRQHandler
+
+ PUBWEAK LPTIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+ B LPTIM2_IRQHandler
+
+ PUBWEAK LPTIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+ B LPTIM3_IRQHandler
+
+ PUBWEAK LPTIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM4_IRQHandler
+ B LPTIM4_IRQHandler
+
+ PUBWEAK LPTIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM5_IRQHandler
+ B LPTIM5_IRQHandler
+
+ PUBWEAK LPUART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+ B LPUART1_IRQHandler
+
+ PUBWEAK CRS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+ B CRS_IRQHandler
+
+ PUBWEAK ECC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ECC_IRQHandler
+ B ECC_IRQHandler
+
+ PUBWEAK SAI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI4_IRQHandler
+ B SAI4_IRQHandler
+
+ PUBWEAK DTS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DTS_IRQHandler
+ B DTS_IRQHandler
+
+ PUBWEAK WAKEUP_PIN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WAKEUP_PIN_IRQHandler
+ B WAKEUP_PIN_IRQHandler
+
+ PUBWEAK OCTOSPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI2_IRQHandler
+ B OCTOSPI2_IRQHandler
+
+ PUBWEAK OTFDEC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTFDEC1_IRQHandler
+ B OTFDEC1_IRQHandler
+
+ PUBWEAK OTFDEC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTFDEC2_IRQHandler
+ B OTFDEC2_IRQHandler
+
+ PUBWEAK FMAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMAC_IRQHandler
+ B FMAC_IRQHandler
+
+ PUBWEAK CORDIC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CORDIC_IRQHandler
+ B CORDIC_IRQHandler
+
+ PUBWEAK UART9_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART9_IRQHandler
+ B UART9_IRQHandler
+
+ PUBWEAK USART10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART10_IRQHandler
+ B USART10_IRQHandler
+
+ PUBWEAK I2C5_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C5_EV_IRQHandler
+ B I2C5_EV_IRQHandler
+
+ PUBWEAK I2C5_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C5_ER_IRQHandler
+ B I2C5_ER_IRQHandler
+
+ PUBWEAK FDCAN3_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN3_IT0_IRQHandler
+ B FDCAN3_IT0_IRQHandler
+
+ PUBWEAK FDCAN3_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN3_IT1_IRQHandler
+ B FDCAN3_IT1_IRQHandler
+
+ PUBWEAK TIM23_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM23_IRQHandler
+ B TIM23_IRQHandler
+
+ PUBWEAK TIM24_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM24_IRQHandler
+ B TIM24_IRQHandler
+
+ END
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h735xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h735xx.s new file mode 100644 index 0000000..7e35492 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h735xx.s @@ -0,0 +1,997 @@ +;/********************************************************************************
+;* File Name : startup_stm32h735xx.s
+;* Author : MCD Application Team
+;* Description : STM32H735xx devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it)
+ DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_PSSI_IRQHandler ; DCMI, PSSI
+ DCD CRYP_IRQHandler ; CRYP crypto
+ DCD HASH_RNG_IRQHandler ; Hash and Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD 0 ; Reserved
+ DCD OCTOSPI1_IRQHandler ; OCTOSPI1
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD 0 ; Reserved
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD 0 ; Reserved
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD 0 ; Reserved
+ DCD ADC3_IRQHandler ; ADC3 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP1_IRQHandler ; COMP1 global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
+ DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD 0 ; Reserved
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
+ DCD SAI4_IRQHandler ; SAI4 global interrupt
+ DCD DTS_IRQHandler ; Digital Temperature Sensor
+ DCD 0 ; Reserved
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+ DCD OCTOSPI2_IRQHandler ; OCTOSPI2 Interrupt
+ DCD OTFDEC1_IRQHandler ; OTFDEC1 Interrupt
+ DCD OTFDEC2_IRQHandler ; OTFDEC2 Interrupt
+ DCD FMAC_IRQHandler ; FMAC Interrupt
+ DCD CORDIC_IRQHandler ; CORDIC Interrupt
+ DCD UART9_IRQHandler ; UART9 Interrupt
+ DCD USART10_IRQHandler ; USART10 Interrupt
+ DCD I2C5_EV_IRQHandler ; I2C5 Event Interrupt
+ DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt
+ DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0
+ DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1
+ DCD TIM23_IRQHandler ; TIM23 global interrupt
+ DCD TIM24_IRQHandler ; TIM24 global interrupt
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_AVD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_AVD_IRQHandler
+ B PVD_AVD_IRQHandler
+
+ PUBWEAK TAMP_STAMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+ B TAMP_STAMP_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream0_IRQHandler
+ B DMA1_Stream0_IRQHandler
+
+ PUBWEAK DMA1_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream1_IRQHandler
+ B DMA1_Stream1_IRQHandler
+
+ PUBWEAK DMA1_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream2_IRQHandler
+ B DMA1_Stream2_IRQHandler
+
+ PUBWEAK DMA1_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream3_IRQHandler
+ B DMA1_Stream3_IRQHandler
+
+ PUBWEAK DMA1_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream4_IRQHandler
+ B DMA1_Stream4_IRQHandler
+
+ PUBWEAK DMA1_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream5_IRQHandler
+ B DMA1_Stream5_IRQHandler
+
+ PUBWEAK DMA1_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream6_IRQHandler
+ B DMA1_Stream6_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK FDCAN1_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+ B FDCAN1_IT0_IRQHandler
+
+ PUBWEAK FDCAN2_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT0_IRQHandler
+ B FDCAN2_IT0_IRQHandler
+
+ PUBWEAK FDCAN1_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+ B FDCAN1_IT1_IRQHandler
+
+ PUBWEAK FDCAN2_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT1_IRQHandler
+ B FDCAN2_IT1_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK TIM8_BRK_TIM12_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_TIM12_IRQHandler
+ B TIM8_BRK_TIM12_IRQHandler
+
+ PUBWEAK TIM8_UP_TIM13_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_TIM13_IRQHandler
+ B TIM8_UP_TIM13_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_TIM14_IRQHandler
+ B TIM8_TRG_COM_TIM14_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK DMA1_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream7_IRQHandler
+ B DMA1_Stream7_IRQHandler
+
+ PUBWEAK FMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+ B FMC_IRQHandler
+
+ PUBWEAK SDMMC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+ B SDMMC1_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream0_IRQHandler
+ B DMA2_Stream0_IRQHandler
+
+ PUBWEAK DMA2_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream1_IRQHandler
+ B DMA2_Stream1_IRQHandler
+
+ PUBWEAK DMA2_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream2_IRQHandler
+ B DMA2_Stream2_IRQHandler
+
+ PUBWEAK DMA2_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream3_IRQHandler
+ B DMA2_Stream3_IRQHandler
+
+ PUBWEAK DMA2_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream4_IRQHandler
+ B DMA2_Stream4_IRQHandler
+
+ PUBWEAK ETH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_IRQHandler
+ B ETH_IRQHandler
+
+ PUBWEAK ETH_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_WKUP_IRQHandler
+ B ETH_WKUP_IRQHandler
+
+ PUBWEAK FDCAN_CAL_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN_CAL_IRQHandler
+ B FDCAN_CAL_IRQHandler
+
+ PUBWEAK DMA2_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream5_IRQHandler
+ B DMA2_Stream5_IRQHandler
+
+ PUBWEAK DMA2_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream6_IRQHandler
+ B DMA2_Stream6_IRQHandler
+
+ PUBWEAK DMA2_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream7_IRQHandler
+ B DMA2_Stream7_IRQHandler
+
+ PUBWEAK USART6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler
+ B USART6_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_OUT_IRQHandler
+ B OTG_HS_EP1_OUT_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_IN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_IN_IRQHandler
+ B OTG_HS_EP1_IN_IRQHandler
+
+ PUBWEAK OTG_HS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_WKUP_IRQHandler
+ B OTG_HS_WKUP_IRQHandler
+
+ PUBWEAK OTG_HS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_IRQHandler
+ B OTG_HS_IRQHandler
+
+ PUBWEAK DCMI_PSSI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_PSSI_IRQHandler
+ B DCMI_PSSI_IRQHandler
+
+ PUBWEAK CRYP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CRYP_IRQHandler
+ B CRYP_IRQHandler
+
+ PUBWEAK HASH_RNG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HASH_RNG_IRQHandler
+ B HASH_RNG_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ PUBWEAK UART7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART7_IRQHandler
+ B UART7_IRQHandler
+
+ PUBWEAK UART8_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART8_IRQHandler
+ B UART8_IRQHandler
+
+ PUBWEAK SPI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+ B SPI4_IRQHandler
+
+ PUBWEAK SPI5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI5_IRQHandler
+ B SPI5_IRQHandler
+
+ PUBWEAK SPI6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI6_IRQHandler
+ B SPI6_IRQHandler
+
+ PUBWEAK SAI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+ B SAI1_IRQHandler
+
+ PUBWEAK LTDC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_IRQHandler
+ B LTDC_IRQHandler
+
+ PUBWEAK LTDC_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_ER_IRQHandler
+ B LTDC_ER_IRQHandler
+
+ PUBWEAK DMA2D_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+ B DMA2D_IRQHandler
+
+ PUBWEAK OCTOSPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI1_IRQHandler
+ B OCTOSPI1_IRQHandler
+
+ PUBWEAK LPTIM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+ B LPTIM1_IRQHandler
+
+ PUBWEAK CEC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler
+ B CEC_IRQHandler
+
+ PUBWEAK I2C4_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+ B I2C4_EV_IRQHandler
+
+ PUBWEAK I2C4_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+ B I2C4_ER_IRQHandler
+
+ PUBWEAK SPDIF_RX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPDIF_RX_IRQHandler
+ B SPDIF_RX_IRQHandler
+
+ PUBWEAK DMAMUX1_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+ B DMAMUX1_OVR_IRQHandler
+
+ PUBWEAK DFSDM1_FLT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT0_IRQHandler
+ B DFSDM1_FLT0_IRQHandler
+
+ PUBWEAK DFSDM1_FLT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+ B DFSDM1_FLT1_IRQHandler
+
+ PUBWEAK DFSDM1_FLT2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+ B DFSDM1_FLT2_IRQHandler
+
+ PUBWEAK DFSDM1_FLT3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+ B DFSDM1_FLT3_IRQHandler
+
+ PUBWEAK SWPMI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SWPMI1_IRQHandler
+ B SWPMI1_IRQHandler
+
+ PUBWEAK TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+ B TIM15_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK MDIOS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_WKUP_IRQHandler
+ B MDIOS_WKUP_IRQHandler
+
+ PUBWEAK MDIOS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_IRQHandler
+ B MDIOS_IRQHandler
+
+ PUBWEAK MDMA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDMA_IRQHandler
+ B MDMA_IRQHandler
+
+ PUBWEAK SDMMC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC2_IRQHandler
+ B SDMMC2_IRQHandler
+
+ PUBWEAK HSEM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM1_IRQHandler
+ B HSEM1_IRQHandler
+
+ PUBWEAK ADC3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC3_IRQHandler
+ B ADC3_IRQHandler
+
+ PUBWEAK DMAMUX2_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX2_OVR_IRQHandler
+ B DMAMUX2_OVR_IRQHandler
+
+ PUBWEAK BDMA_Channel0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel0_IRQHandler
+ B BDMA_Channel0_IRQHandler
+
+ PUBWEAK BDMA_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel1_IRQHandler
+ B BDMA_Channel1_IRQHandler
+
+ PUBWEAK BDMA_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel2_IRQHandler
+ B BDMA_Channel2_IRQHandler
+
+ PUBWEAK BDMA_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel3_IRQHandler
+ B BDMA_Channel3_IRQHandler
+
+ PUBWEAK BDMA_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel4_IRQHandler
+ B BDMA_Channel4_IRQHandler
+
+ PUBWEAK BDMA_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel5_IRQHandler
+ B BDMA_Channel5_IRQHandler
+
+ PUBWEAK BDMA_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel6_IRQHandler
+ B BDMA_Channel6_IRQHandler
+
+ PUBWEAK BDMA_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel7_IRQHandler
+ B BDMA_Channel7_IRQHandler
+
+ PUBWEAK COMP1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP1_IRQHandler
+ B COMP1_IRQHandler
+
+ PUBWEAK LPTIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+ B LPTIM2_IRQHandler
+
+ PUBWEAK LPTIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+ B LPTIM3_IRQHandler
+
+ PUBWEAK LPTIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM4_IRQHandler
+ B LPTIM4_IRQHandler
+
+ PUBWEAK LPTIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM5_IRQHandler
+ B LPTIM5_IRQHandler
+
+ PUBWEAK LPUART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+ B LPUART1_IRQHandler
+
+ PUBWEAK CRS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+ B CRS_IRQHandler
+
+ PUBWEAK ECC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ECC_IRQHandler
+ B ECC_IRQHandler
+
+ PUBWEAK SAI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI4_IRQHandler
+ B SAI4_IRQHandler
+
+ PUBWEAK DTS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DTS_IRQHandler
+ B DTS_IRQHandler
+
+ PUBWEAK WAKEUP_PIN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WAKEUP_PIN_IRQHandler
+ B WAKEUP_PIN_IRQHandler
+
+ PUBWEAK OCTOSPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI2_IRQHandler
+ B OCTOSPI2_IRQHandler
+
+ PUBWEAK OTFDEC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTFDEC1_IRQHandler
+ B OTFDEC1_IRQHandler
+
+ PUBWEAK OTFDEC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTFDEC2_IRQHandler
+ B OTFDEC2_IRQHandler
+
+ PUBWEAK FMAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMAC_IRQHandler
+ B FMAC_IRQHandler
+
+ PUBWEAK CORDIC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CORDIC_IRQHandler
+ B CORDIC_IRQHandler
+
+ PUBWEAK UART9_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART9_IRQHandler
+ B UART9_IRQHandler
+
+ PUBWEAK USART10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART10_IRQHandler
+ B USART10_IRQHandler
+
+ PUBWEAK I2C5_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C5_EV_IRQHandler
+ B I2C5_EV_IRQHandler
+
+ PUBWEAK I2C5_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C5_ER_IRQHandler
+ B I2C5_ER_IRQHandler
+
+ PUBWEAK FDCAN3_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN3_IT0_IRQHandler
+ B FDCAN3_IT0_IRQHandler
+
+ PUBWEAK FDCAN3_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN3_IT1_IRQHandler
+ B FDCAN3_IT1_IRQHandler
+
+ PUBWEAK TIM23_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM23_IRQHandler
+ B TIM23_IRQHandler
+
+ PUBWEAK TIM24_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM24_IRQHandler
+ B TIM24_IRQHandler
+
+ END
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h742xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h742xx.s new file mode 100644 index 0000000..e071fa5 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h742xx.s @@ -0,0 +1,962 @@ +;/********************************************************************************
+;* File Name : startup_stm32h742xx.s
+;* Author : MCD Application Team
+;* Description : STM32H742xx devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it)
+ DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_IRQHandler ; DCMI
+ DCD 0 ; Reserved
+ DCD RNG_IRQHandler ; Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD QUADSPI_IRQHandler ; QUADSPI
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
+ DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
+ DCD OTG_FS_IRQHandler ; USB OTG FS
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
+ DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
+ DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
+ DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
+ DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
+ DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
+ DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD SAI3_IRQHandler ; SAI3 global Interrupt
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD 0 ; Reserved
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD 0 ; Reserved
+ DCD ADC3_IRQHandler ; ADC3 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP1_IRQHandler ; COMP1 global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
+ DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD 0 ; Reserved
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
+ DCD SAI4_IRQHandler ; SAI4 global interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_AVD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_AVD_IRQHandler
+ B PVD_AVD_IRQHandler
+
+ PUBWEAK TAMP_STAMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+ B TAMP_STAMP_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream0_IRQHandler
+ B DMA1_Stream0_IRQHandler
+
+ PUBWEAK DMA1_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream1_IRQHandler
+ B DMA1_Stream1_IRQHandler
+
+ PUBWEAK DMA1_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream2_IRQHandler
+ B DMA1_Stream2_IRQHandler
+
+ PUBWEAK DMA1_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream3_IRQHandler
+ B DMA1_Stream3_IRQHandler
+
+ PUBWEAK DMA1_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream4_IRQHandler
+ B DMA1_Stream4_IRQHandler
+
+ PUBWEAK DMA1_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream5_IRQHandler
+ B DMA1_Stream5_IRQHandler
+
+ PUBWEAK DMA1_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream6_IRQHandler
+ B DMA1_Stream6_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK FDCAN1_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+ B FDCAN1_IT0_IRQHandler
+
+ PUBWEAK FDCAN2_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT0_IRQHandler
+ B FDCAN2_IT0_IRQHandler
+
+ PUBWEAK FDCAN1_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+ B FDCAN1_IT1_IRQHandler
+
+ PUBWEAK FDCAN2_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT1_IRQHandler
+ B FDCAN2_IT1_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK TIM8_BRK_TIM12_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_TIM12_IRQHandler
+ B TIM8_BRK_TIM12_IRQHandler
+
+ PUBWEAK TIM8_UP_TIM13_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_TIM13_IRQHandler
+ B TIM8_UP_TIM13_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_TIM14_IRQHandler
+ B TIM8_TRG_COM_TIM14_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK DMA1_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream7_IRQHandler
+ B DMA1_Stream7_IRQHandler
+
+ PUBWEAK FMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+ B FMC_IRQHandler
+
+ PUBWEAK SDMMC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+ B SDMMC1_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream0_IRQHandler
+ B DMA2_Stream0_IRQHandler
+
+ PUBWEAK DMA2_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream1_IRQHandler
+ B DMA2_Stream1_IRQHandler
+
+ PUBWEAK DMA2_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream2_IRQHandler
+ B DMA2_Stream2_IRQHandler
+
+ PUBWEAK DMA2_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream3_IRQHandler
+ B DMA2_Stream3_IRQHandler
+
+ PUBWEAK DMA2_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream4_IRQHandler
+ B DMA2_Stream4_IRQHandler
+
+ PUBWEAK ETH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_IRQHandler
+ B ETH_IRQHandler
+
+ PUBWEAK ETH_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_WKUP_IRQHandler
+ B ETH_WKUP_IRQHandler
+
+ PUBWEAK FDCAN_CAL_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN_CAL_IRQHandler
+ B FDCAN_CAL_IRQHandler
+
+ PUBWEAK DMA2_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream5_IRQHandler
+ B DMA2_Stream5_IRQHandler
+
+ PUBWEAK DMA2_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream6_IRQHandler
+ B DMA2_Stream6_IRQHandler
+
+ PUBWEAK DMA2_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream7_IRQHandler
+ B DMA2_Stream7_IRQHandler
+
+ PUBWEAK USART6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler
+ B USART6_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_OUT_IRQHandler
+ B OTG_HS_EP1_OUT_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_IN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_IN_IRQHandler
+ B OTG_HS_EP1_IN_IRQHandler
+
+ PUBWEAK OTG_HS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_WKUP_IRQHandler
+ B OTG_HS_WKUP_IRQHandler
+
+ PUBWEAK OTG_HS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_IRQHandler
+ B OTG_HS_IRQHandler
+
+ PUBWEAK DCMI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_IRQHandler
+ B DCMI_IRQHandler
+
+ PUBWEAK RNG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+ B RNG_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ PUBWEAK UART7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART7_IRQHandler
+ B UART7_IRQHandler
+
+ PUBWEAK UART8_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART8_IRQHandler
+ B UART8_IRQHandler
+
+ PUBWEAK SPI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+ B SPI4_IRQHandler
+
+ PUBWEAK SPI5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI5_IRQHandler
+ B SPI5_IRQHandler
+
+ PUBWEAK SPI6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI6_IRQHandler
+ B SPI6_IRQHandler
+
+ PUBWEAK SAI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+ B SAI1_IRQHandler
+
+ PUBWEAK DMA2D_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+ B DMA2D_IRQHandler
+
+ PUBWEAK SAI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+ B SAI2_IRQHandler
+
+ PUBWEAK QUADSPI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+ B QUADSPI_IRQHandler
+
+ PUBWEAK LPTIM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+ B LPTIM1_IRQHandler
+
+ PUBWEAK CEC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler
+ B CEC_IRQHandler
+
+ PUBWEAK I2C4_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+ B I2C4_EV_IRQHandler
+
+ PUBWEAK I2C4_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+ B I2C4_ER_IRQHandler
+
+ PUBWEAK SPDIF_RX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPDIF_RX_IRQHandler
+ B SPDIF_RX_IRQHandler
+
+ PUBWEAK OTG_FS_EP1_OUT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_EP1_OUT_IRQHandler
+ B OTG_FS_EP1_OUT_IRQHandler
+
+ PUBWEAK OTG_FS_EP1_IN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_EP1_IN_IRQHandler
+ B OTG_FS_EP1_IN_IRQHandler
+
+ PUBWEAK OTG_FS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_WKUP_IRQHandler
+ B OTG_FS_WKUP_IRQHandler
+
+ PUBWEAK OTG_FS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_IRQHandler
+ B OTG_FS_IRQHandler
+
+ PUBWEAK DMAMUX1_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+ B DMAMUX1_OVR_IRQHandler
+
+ PUBWEAK HRTIM1_Master_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_Master_IRQHandler
+ B HRTIM1_Master_IRQHandler
+
+ PUBWEAK HRTIM1_TIMA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMA_IRQHandler
+ B HRTIM1_TIMA_IRQHandler
+
+ PUBWEAK HRTIM1_TIMB_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMB_IRQHandler
+ B HRTIM1_TIMB_IRQHandler
+
+ PUBWEAK HRTIM1_TIMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMC_IRQHandler
+ B HRTIM1_TIMC_IRQHandler
+
+ PUBWEAK HRTIM1_TIMD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMD_IRQHandler
+ B HRTIM1_TIMD_IRQHandler
+
+ PUBWEAK HRTIM1_TIME_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIME_IRQHandler
+ B HRTIM1_TIME_IRQHandler
+
+ PUBWEAK HRTIM1_FLT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_FLT_IRQHandler
+ B HRTIM1_FLT_IRQHandler
+
+ PUBWEAK DFSDM1_FLT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT0_IRQHandler
+ B DFSDM1_FLT0_IRQHandler
+
+ PUBWEAK DFSDM1_FLT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+ B DFSDM1_FLT1_IRQHandler
+
+ PUBWEAK DFSDM1_FLT2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+ B DFSDM1_FLT2_IRQHandler
+
+ PUBWEAK DFSDM1_FLT3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+ B DFSDM1_FLT3_IRQHandler
+
+ PUBWEAK SAI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI3_IRQHandler
+ B SAI3_IRQHandler
+
+ PUBWEAK SWPMI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SWPMI1_IRQHandler
+ B SWPMI1_IRQHandler
+
+ PUBWEAK TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+ B TIM15_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK MDIOS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_WKUP_IRQHandler
+ B MDIOS_WKUP_IRQHandler
+
+ PUBWEAK MDIOS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_IRQHandler
+ B MDIOS_IRQHandler
+
+ PUBWEAK MDMA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDMA_IRQHandler
+ B MDMA_IRQHandler
+
+ PUBWEAK SDMMC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC2_IRQHandler
+ B SDMMC2_IRQHandler
+
+ PUBWEAK HSEM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM1_IRQHandler
+ B HSEM1_IRQHandler
+
+ PUBWEAK ADC3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC3_IRQHandler
+ B ADC3_IRQHandler
+
+ PUBWEAK DMAMUX2_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX2_OVR_IRQHandler
+ B DMAMUX2_OVR_IRQHandler
+
+ PUBWEAK BDMA_Channel0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel0_IRQHandler
+ B BDMA_Channel0_IRQHandler
+
+ PUBWEAK BDMA_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel1_IRQHandler
+ B BDMA_Channel1_IRQHandler
+
+ PUBWEAK BDMA_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel2_IRQHandler
+ B BDMA_Channel2_IRQHandler
+
+ PUBWEAK BDMA_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel3_IRQHandler
+ B BDMA_Channel3_IRQHandler
+
+ PUBWEAK BDMA_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel4_IRQHandler
+ B BDMA_Channel4_IRQHandler
+
+ PUBWEAK BDMA_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel5_IRQHandler
+ B BDMA_Channel5_IRQHandler
+
+ PUBWEAK BDMA_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel6_IRQHandler
+ B BDMA_Channel6_IRQHandler
+
+ PUBWEAK BDMA_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel7_IRQHandler
+ B BDMA_Channel7_IRQHandler
+
+ PUBWEAK COMP1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP1_IRQHandler
+ B COMP1_IRQHandler
+
+ PUBWEAK LPTIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+ B LPTIM2_IRQHandler
+
+ PUBWEAK LPTIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+ B LPTIM3_IRQHandler
+
+ PUBWEAK LPTIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM4_IRQHandler
+ B LPTIM4_IRQHandler
+
+ PUBWEAK LPTIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM5_IRQHandler
+ B LPTIM5_IRQHandler
+
+ PUBWEAK LPUART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+ B LPUART1_IRQHandler
+
+ PUBWEAK CRS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+ B CRS_IRQHandler
+
+ PUBWEAK ECC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ECC_IRQHandler
+ B ECC_IRQHandler
+
+ PUBWEAK SAI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI4_IRQHandler
+ B SAI4_IRQHandler
+
+ PUBWEAK WAKEUP_PIN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WAKEUP_PIN_IRQHandler
+ B WAKEUP_PIN_IRQHandler
+ END
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h743xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h743xx.s new file mode 100644 index 0000000..5856cbb --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h743xx.s @@ -0,0 +1,977 @@ +;/********************************************************************************
+;* File Name : startup_stm32h743xx.s
+;* Author : MCD Application Team
+;* Description : STM32H743xx devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it)
+ DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_IRQHandler ; DCMI
+ DCD 0 ; Reserved
+ DCD RNG_IRQHandler ; Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD QUADSPI_IRQHandler ; QUADSPI
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
+ DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
+ DCD OTG_FS_IRQHandler ; USB OTG FS
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
+ DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
+ DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
+ DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
+ DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
+ DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
+ DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD SAI3_IRQHandler ; SAI3 global Interrupt
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD JPEG_IRQHandler ; JPEG global Interrupt
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD 0 ; Reserved
+ DCD ADC3_IRQHandler ; ADC3 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP1_IRQHandler ; COMP1 global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
+ DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD 0 ; Reserved
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
+ DCD SAI4_IRQHandler ; SAI4 global interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_AVD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_AVD_IRQHandler
+ B PVD_AVD_IRQHandler
+
+ PUBWEAK TAMP_STAMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+ B TAMP_STAMP_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream0_IRQHandler
+ B DMA1_Stream0_IRQHandler
+
+ PUBWEAK DMA1_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream1_IRQHandler
+ B DMA1_Stream1_IRQHandler
+
+ PUBWEAK DMA1_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream2_IRQHandler
+ B DMA1_Stream2_IRQHandler
+
+ PUBWEAK DMA1_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream3_IRQHandler
+ B DMA1_Stream3_IRQHandler
+
+ PUBWEAK DMA1_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream4_IRQHandler
+ B DMA1_Stream4_IRQHandler
+
+ PUBWEAK DMA1_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream5_IRQHandler
+ B DMA1_Stream5_IRQHandler
+
+ PUBWEAK DMA1_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream6_IRQHandler
+ B DMA1_Stream6_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK FDCAN1_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+ B FDCAN1_IT0_IRQHandler
+
+ PUBWEAK FDCAN2_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT0_IRQHandler
+ B FDCAN2_IT0_IRQHandler
+
+ PUBWEAK FDCAN1_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+ B FDCAN1_IT1_IRQHandler
+
+ PUBWEAK FDCAN2_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT1_IRQHandler
+ B FDCAN2_IT1_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK TIM8_BRK_TIM12_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_TIM12_IRQHandler
+ B TIM8_BRK_TIM12_IRQHandler
+
+ PUBWEAK TIM8_UP_TIM13_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_TIM13_IRQHandler
+ B TIM8_UP_TIM13_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_TIM14_IRQHandler
+ B TIM8_TRG_COM_TIM14_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK DMA1_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream7_IRQHandler
+ B DMA1_Stream7_IRQHandler
+
+ PUBWEAK FMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+ B FMC_IRQHandler
+
+ PUBWEAK SDMMC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+ B SDMMC1_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream0_IRQHandler
+ B DMA2_Stream0_IRQHandler
+
+ PUBWEAK DMA2_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream1_IRQHandler
+ B DMA2_Stream1_IRQHandler
+
+ PUBWEAK DMA2_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream2_IRQHandler
+ B DMA2_Stream2_IRQHandler
+
+ PUBWEAK DMA2_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream3_IRQHandler
+ B DMA2_Stream3_IRQHandler
+
+ PUBWEAK DMA2_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream4_IRQHandler
+ B DMA2_Stream4_IRQHandler
+
+ PUBWEAK ETH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_IRQHandler
+ B ETH_IRQHandler
+
+ PUBWEAK ETH_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_WKUP_IRQHandler
+ B ETH_WKUP_IRQHandler
+
+ PUBWEAK FDCAN_CAL_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN_CAL_IRQHandler
+ B FDCAN_CAL_IRQHandler
+
+ PUBWEAK DMA2_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream5_IRQHandler
+ B DMA2_Stream5_IRQHandler
+
+ PUBWEAK DMA2_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream6_IRQHandler
+ B DMA2_Stream6_IRQHandler
+
+ PUBWEAK DMA2_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream7_IRQHandler
+ B DMA2_Stream7_IRQHandler
+
+ PUBWEAK USART6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler
+ B USART6_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_OUT_IRQHandler
+ B OTG_HS_EP1_OUT_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_IN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_IN_IRQHandler
+ B OTG_HS_EP1_IN_IRQHandler
+
+ PUBWEAK OTG_HS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_WKUP_IRQHandler
+ B OTG_HS_WKUP_IRQHandler
+
+ PUBWEAK OTG_HS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_IRQHandler
+ B OTG_HS_IRQHandler
+
+ PUBWEAK DCMI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_IRQHandler
+ B DCMI_IRQHandler
+
+ PUBWEAK RNG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+ B RNG_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ PUBWEAK UART7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART7_IRQHandler
+ B UART7_IRQHandler
+
+ PUBWEAK UART8_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART8_IRQHandler
+ B UART8_IRQHandler
+
+ PUBWEAK SPI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+ B SPI4_IRQHandler
+
+ PUBWEAK SPI5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI5_IRQHandler
+ B SPI5_IRQHandler
+
+ PUBWEAK SPI6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI6_IRQHandler
+ B SPI6_IRQHandler
+
+ PUBWEAK SAI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+ B SAI1_IRQHandler
+
+ PUBWEAK LTDC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_IRQHandler
+ B LTDC_IRQHandler
+
+ PUBWEAK LTDC_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_ER_IRQHandler
+ B LTDC_ER_IRQHandler
+
+ PUBWEAK DMA2D_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+ B DMA2D_IRQHandler
+
+ PUBWEAK SAI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+ B SAI2_IRQHandler
+
+ PUBWEAK QUADSPI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+ B QUADSPI_IRQHandler
+
+ PUBWEAK LPTIM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+ B LPTIM1_IRQHandler
+
+ PUBWEAK CEC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler
+ B CEC_IRQHandler
+
+ PUBWEAK I2C4_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+ B I2C4_EV_IRQHandler
+
+ PUBWEAK I2C4_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+ B I2C4_ER_IRQHandler
+
+ PUBWEAK SPDIF_RX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPDIF_RX_IRQHandler
+ B SPDIF_RX_IRQHandler
+
+ PUBWEAK OTG_FS_EP1_OUT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_EP1_OUT_IRQHandler
+ B OTG_FS_EP1_OUT_IRQHandler
+
+ PUBWEAK OTG_FS_EP1_IN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_EP1_IN_IRQHandler
+ B OTG_FS_EP1_IN_IRQHandler
+
+ PUBWEAK OTG_FS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_WKUP_IRQHandler
+ B OTG_FS_WKUP_IRQHandler
+
+ PUBWEAK OTG_FS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_IRQHandler
+ B OTG_FS_IRQHandler
+
+ PUBWEAK DMAMUX1_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+ B DMAMUX1_OVR_IRQHandler
+
+ PUBWEAK HRTIM1_Master_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_Master_IRQHandler
+ B HRTIM1_Master_IRQHandler
+
+ PUBWEAK HRTIM1_TIMA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMA_IRQHandler
+ B HRTIM1_TIMA_IRQHandler
+
+ PUBWEAK HRTIM1_TIMB_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMB_IRQHandler
+ B HRTIM1_TIMB_IRQHandler
+
+ PUBWEAK HRTIM1_TIMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMC_IRQHandler
+ B HRTIM1_TIMC_IRQHandler
+
+ PUBWEAK HRTIM1_TIMD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMD_IRQHandler
+ B HRTIM1_TIMD_IRQHandler
+
+ PUBWEAK HRTIM1_TIME_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIME_IRQHandler
+ B HRTIM1_TIME_IRQHandler
+
+ PUBWEAK HRTIM1_FLT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_FLT_IRQHandler
+ B HRTIM1_FLT_IRQHandler
+
+ PUBWEAK DFSDM1_FLT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT0_IRQHandler
+ B DFSDM1_FLT0_IRQHandler
+
+ PUBWEAK DFSDM1_FLT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+ B DFSDM1_FLT1_IRQHandler
+
+ PUBWEAK DFSDM1_FLT2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+ B DFSDM1_FLT2_IRQHandler
+
+ PUBWEAK DFSDM1_FLT3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+ B DFSDM1_FLT3_IRQHandler
+
+ PUBWEAK SAI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI3_IRQHandler
+ B SAI3_IRQHandler
+
+ PUBWEAK SWPMI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SWPMI1_IRQHandler
+ B SWPMI1_IRQHandler
+
+ PUBWEAK TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+ B TIM15_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK MDIOS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_WKUP_IRQHandler
+ B MDIOS_WKUP_IRQHandler
+
+ PUBWEAK MDIOS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_IRQHandler
+ B MDIOS_IRQHandler
+
+ PUBWEAK JPEG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+JPEG_IRQHandler
+ B JPEG_IRQHandler
+
+ PUBWEAK MDMA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDMA_IRQHandler
+ B MDMA_IRQHandler
+
+ PUBWEAK SDMMC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC2_IRQHandler
+ B SDMMC2_IRQHandler
+
+ PUBWEAK HSEM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM1_IRQHandler
+ B HSEM1_IRQHandler
+
+ PUBWEAK ADC3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC3_IRQHandler
+ B ADC3_IRQHandler
+
+ PUBWEAK DMAMUX2_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX2_OVR_IRQHandler
+ B DMAMUX2_OVR_IRQHandler
+
+ PUBWEAK BDMA_Channel0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel0_IRQHandler
+ B BDMA_Channel0_IRQHandler
+
+ PUBWEAK BDMA_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel1_IRQHandler
+ B BDMA_Channel1_IRQHandler
+
+ PUBWEAK BDMA_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel2_IRQHandler
+ B BDMA_Channel2_IRQHandler
+
+ PUBWEAK BDMA_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel3_IRQHandler
+ B BDMA_Channel3_IRQHandler
+
+ PUBWEAK BDMA_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel4_IRQHandler
+ B BDMA_Channel4_IRQHandler
+
+ PUBWEAK BDMA_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel5_IRQHandler
+ B BDMA_Channel5_IRQHandler
+
+ PUBWEAK BDMA_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel6_IRQHandler
+ B BDMA_Channel6_IRQHandler
+
+ PUBWEAK BDMA_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel7_IRQHandler
+ B BDMA_Channel7_IRQHandler
+
+ PUBWEAK COMP1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP1_IRQHandler
+ B COMP1_IRQHandler
+
+ PUBWEAK LPTIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+ B LPTIM2_IRQHandler
+
+ PUBWEAK LPTIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+ B LPTIM3_IRQHandler
+
+ PUBWEAK LPTIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM4_IRQHandler
+ B LPTIM4_IRQHandler
+
+ PUBWEAK LPTIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM5_IRQHandler
+ B LPTIM5_IRQHandler
+
+ PUBWEAK LPUART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+ B LPUART1_IRQHandler
+
+ PUBWEAK CRS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+ B CRS_IRQHandler
+
+ PUBWEAK ECC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ECC_IRQHandler
+ B ECC_IRQHandler
+
+ PUBWEAK SAI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI4_IRQHandler
+ B SAI4_IRQHandler
+
+ PUBWEAK WAKEUP_PIN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WAKEUP_PIN_IRQHandler
+ B WAKEUP_PIN_IRQHandler
+ END
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h745xg.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h745xg.s new file mode 100644 index 0000000..dda099e --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h745xg.s @@ -0,0 +1,1002 @@ +;/********************************************************************************
+;* File Name : startup_stm32h745xg.s
+;* Author : MCD Application Team
+;* Description : STM32H745xg devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)
+ DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4
+ DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_IRQHandler ; DCMI
+ DCD 0 ; Reserved
+ DCD RNG_IRQHandler ; Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD QUADSPI_IRQHandler ; QUADSPI
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
+ DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
+ DCD OTG_FS_IRQHandler ; USB OTG FS
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
+ DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
+ DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
+ DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
+ DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
+ DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
+ DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD SAI3_IRQHandler ; SAI3 global Interrupt
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD JPEG_IRQHandler ; JPEG global Interrupt
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD HSEM2_IRQHandler ; HSEM2 global Interrupt
+ DCD ADC3_IRQHandler ; ADC3 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP1_IRQHandler ; COMP1 global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
+ DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it)
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
+ DCD SAI4_IRQHandler ; SAI4 global interrupt
+ DCD 0 ; Reserved
+ DCD HOLD_CORE_IRQHandler ; Hold core interrupt
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_AVD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_AVD_IRQHandler
+ B PVD_AVD_IRQHandler
+
+ PUBWEAK TAMP_STAMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+ B TAMP_STAMP_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream0_IRQHandler
+ B DMA1_Stream0_IRQHandler
+
+ PUBWEAK DMA1_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream1_IRQHandler
+ B DMA1_Stream1_IRQHandler
+
+ PUBWEAK DMA1_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream2_IRQHandler
+ B DMA1_Stream2_IRQHandler
+
+ PUBWEAK DMA1_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream3_IRQHandler
+ B DMA1_Stream3_IRQHandler
+
+ PUBWEAK DMA1_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream4_IRQHandler
+ B DMA1_Stream4_IRQHandler
+
+ PUBWEAK DMA1_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream5_IRQHandler
+ B DMA1_Stream5_IRQHandler
+
+ PUBWEAK DMA1_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream6_IRQHandler
+ B DMA1_Stream6_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK FDCAN1_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+ B FDCAN1_IT0_IRQHandler
+
+ PUBWEAK FDCAN2_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT0_IRQHandler
+ B FDCAN2_IT0_IRQHandler
+
+ PUBWEAK FDCAN1_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+ B FDCAN1_IT1_IRQHandler
+
+ PUBWEAK FDCAN2_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT1_IRQHandler
+ B FDCAN2_IT1_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK TIM8_BRK_TIM12_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_TIM12_IRQHandler
+ B TIM8_BRK_TIM12_IRQHandler
+
+ PUBWEAK TIM8_UP_TIM13_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_TIM13_IRQHandler
+ B TIM8_UP_TIM13_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_TIM14_IRQHandler
+ B TIM8_TRG_COM_TIM14_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK DMA1_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream7_IRQHandler
+ B DMA1_Stream7_IRQHandler
+
+ PUBWEAK FMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+ B FMC_IRQHandler
+
+ PUBWEAK SDMMC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+ B SDMMC1_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream0_IRQHandler
+ B DMA2_Stream0_IRQHandler
+
+ PUBWEAK DMA2_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream1_IRQHandler
+ B DMA2_Stream1_IRQHandler
+
+ PUBWEAK DMA2_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream2_IRQHandler
+ B DMA2_Stream2_IRQHandler
+
+ PUBWEAK DMA2_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream3_IRQHandler
+ B DMA2_Stream3_IRQHandler
+
+ PUBWEAK DMA2_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream4_IRQHandler
+ B DMA2_Stream4_IRQHandler
+
+ PUBWEAK ETH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_IRQHandler
+ B ETH_IRQHandler
+
+ PUBWEAK ETH_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_WKUP_IRQHandler
+ B ETH_WKUP_IRQHandler
+
+ PUBWEAK FDCAN_CAL_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN_CAL_IRQHandler
+ B FDCAN_CAL_IRQHandler
+
+ PUBWEAK CM7_SEV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CM7_SEV_IRQHandler
+ B CM7_SEV_IRQHandler
+
+ PUBWEAK CM4_SEV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CM4_SEV_IRQHandler
+ B CM4_SEV_IRQHandler
+
+ PUBWEAK DMA2_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream5_IRQHandler
+ B DMA2_Stream5_IRQHandler
+
+ PUBWEAK DMA2_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream6_IRQHandler
+ B DMA2_Stream6_IRQHandler
+
+ PUBWEAK DMA2_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream7_IRQHandler
+ B DMA2_Stream7_IRQHandler
+
+ PUBWEAK USART6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler
+ B USART6_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_OUT_IRQHandler
+ B OTG_HS_EP1_OUT_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_IN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_IN_IRQHandler
+ B OTG_HS_EP1_IN_IRQHandler
+
+ PUBWEAK OTG_HS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_WKUP_IRQHandler
+ B OTG_HS_WKUP_IRQHandler
+
+ PUBWEAK OTG_HS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_IRQHandler
+ B OTG_HS_IRQHandler
+
+ PUBWEAK DCMI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_IRQHandler
+ B DCMI_IRQHandler
+
+ PUBWEAK RNG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+ B RNG_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ PUBWEAK UART7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART7_IRQHandler
+ B UART7_IRQHandler
+
+ PUBWEAK UART8_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART8_IRQHandler
+ B UART8_IRQHandler
+
+ PUBWEAK SPI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+ B SPI4_IRQHandler
+
+ PUBWEAK SPI5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI5_IRQHandler
+ B SPI5_IRQHandler
+
+ PUBWEAK SPI6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI6_IRQHandler
+ B SPI6_IRQHandler
+
+ PUBWEAK SAI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+ B SAI1_IRQHandler
+
+ PUBWEAK LTDC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_IRQHandler
+ B LTDC_IRQHandler
+
+ PUBWEAK LTDC_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_ER_IRQHandler
+ B LTDC_ER_IRQHandler
+
+ PUBWEAK DMA2D_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+ B DMA2D_IRQHandler
+
+ PUBWEAK SAI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+ B SAI2_IRQHandler
+
+ PUBWEAK QUADSPI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+ B QUADSPI_IRQHandler
+
+ PUBWEAK LPTIM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+ B LPTIM1_IRQHandler
+
+ PUBWEAK CEC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler
+ B CEC_IRQHandler
+
+ PUBWEAK I2C4_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+ B I2C4_EV_IRQHandler
+
+ PUBWEAK I2C4_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+ B I2C4_ER_IRQHandler
+
+ PUBWEAK SPDIF_RX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPDIF_RX_IRQHandler
+ B SPDIF_RX_IRQHandler
+
+ PUBWEAK OTG_FS_EP1_OUT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_EP1_OUT_IRQHandler
+ B OTG_FS_EP1_OUT_IRQHandler
+
+ PUBWEAK OTG_FS_EP1_IN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_EP1_IN_IRQHandler
+ B OTG_FS_EP1_IN_IRQHandler
+
+ PUBWEAK OTG_FS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_WKUP_IRQHandler
+ B OTG_FS_WKUP_IRQHandler
+
+ PUBWEAK OTG_FS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_IRQHandler
+ B OTG_FS_IRQHandler
+
+ PUBWEAK DMAMUX1_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+ B DMAMUX1_OVR_IRQHandler
+
+ PUBWEAK HRTIM1_Master_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_Master_IRQHandler
+ B HRTIM1_Master_IRQHandler
+
+ PUBWEAK HRTIM1_TIMA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMA_IRQHandler
+ B HRTIM1_TIMA_IRQHandler
+
+ PUBWEAK HRTIM1_TIMB_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMB_IRQHandler
+ B HRTIM1_TIMB_IRQHandler
+
+ PUBWEAK HRTIM1_TIMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMC_IRQHandler
+ B HRTIM1_TIMC_IRQHandler
+
+ PUBWEAK HRTIM1_TIMD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMD_IRQHandler
+ B HRTIM1_TIMD_IRQHandler
+
+ PUBWEAK HRTIM1_TIME_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIME_IRQHandler
+ B HRTIM1_TIME_IRQHandler
+
+ PUBWEAK HRTIM1_FLT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_FLT_IRQHandler
+ B HRTIM1_FLT_IRQHandler
+
+ PUBWEAK DFSDM1_FLT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT0_IRQHandler
+ B DFSDM1_FLT0_IRQHandler
+
+ PUBWEAK DFSDM1_FLT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+ B DFSDM1_FLT1_IRQHandler
+
+ PUBWEAK DFSDM1_FLT2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+ B DFSDM1_FLT2_IRQHandler
+
+ PUBWEAK DFSDM1_FLT3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+ B DFSDM1_FLT3_IRQHandler
+
+ PUBWEAK SAI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI3_IRQHandler
+ B SAI3_IRQHandler
+
+ PUBWEAK SWPMI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SWPMI1_IRQHandler
+ B SWPMI1_IRQHandler
+
+ PUBWEAK TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+ B TIM15_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK MDIOS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_WKUP_IRQHandler
+ B MDIOS_WKUP_IRQHandler
+
+ PUBWEAK MDIOS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_IRQHandler
+ B MDIOS_IRQHandler
+
+ PUBWEAK JPEG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+JPEG_IRQHandler
+ B JPEG_IRQHandler
+
+ PUBWEAK MDMA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDMA_IRQHandler
+ B MDMA_IRQHandler
+
+ PUBWEAK SDMMC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC2_IRQHandler
+ B SDMMC2_IRQHandler
+
+ PUBWEAK HSEM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM1_IRQHandler
+ B HSEM1_IRQHandler
+
+ PUBWEAK HSEM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM2_IRQHandler
+ B HSEM2_IRQHandler
+
+ PUBWEAK ADC3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC3_IRQHandler
+ B ADC3_IRQHandler
+
+ PUBWEAK DMAMUX2_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX2_OVR_IRQHandler
+ B DMAMUX2_OVR_IRQHandler
+
+ PUBWEAK BDMA_Channel0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel0_IRQHandler
+ B BDMA_Channel0_IRQHandler
+
+ PUBWEAK BDMA_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel1_IRQHandler
+ B BDMA_Channel1_IRQHandler
+
+ PUBWEAK BDMA_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel2_IRQHandler
+ B BDMA_Channel2_IRQHandler
+
+ PUBWEAK BDMA_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel3_IRQHandler
+ B BDMA_Channel3_IRQHandler
+
+ PUBWEAK BDMA_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel4_IRQHandler
+ B BDMA_Channel4_IRQHandler
+
+ PUBWEAK BDMA_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel5_IRQHandler
+ B BDMA_Channel5_IRQHandler
+
+ PUBWEAK BDMA_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel6_IRQHandler
+ B BDMA_Channel6_IRQHandler
+
+ PUBWEAK BDMA_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel7_IRQHandler
+ B BDMA_Channel7_IRQHandler
+
+ PUBWEAK COMP1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP1_IRQHandler
+ B COMP1_IRQHandler
+
+ PUBWEAK LPTIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+ B LPTIM2_IRQHandler
+
+ PUBWEAK LPTIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+ B LPTIM3_IRQHandler
+
+ PUBWEAK LPTIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM4_IRQHandler
+ B LPTIM4_IRQHandler
+
+ PUBWEAK LPTIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM5_IRQHandler
+ B LPTIM5_IRQHandler
+
+ PUBWEAK LPUART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+ B LPUART1_IRQHandler
+
+ PUBWEAK WWDG_RST_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_RST_IRQHandler
+ B WWDG_RST_IRQHandler
+
+ PUBWEAK CRS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+ B CRS_IRQHandler
+
+ PUBWEAK ECC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ECC_IRQHandler
+ B ECC_IRQHandler
+
+ PUBWEAK SAI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI4_IRQHandler
+ B SAI4_IRQHandler
+
+ PUBWEAK HOLD_CORE_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HOLD_CORE_IRQHandler
+ B HOLD_CORE_IRQHandler
+
+ PUBWEAK WAKEUP_PIN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WAKEUP_PIN_IRQHandler
+ B WAKEUP_PIN_IRQHandler
+ END
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h745xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h745xx.s new file mode 100644 index 0000000..2051bd1 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h745xx.s @@ -0,0 +1,1002 @@ +;/********************************************************************************
+;* File Name : startup_stm32h745xx.s
+;* Author : MCD Application Team
+;* Description : STM32H745xx devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)
+ DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4
+ DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_IRQHandler ; DCMI
+ DCD 0 ; Reserved
+ DCD RNG_IRQHandler ; Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD QUADSPI_IRQHandler ; QUADSPI
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
+ DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
+ DCD OTG_FS_IRQHandler ; USB OTG FS
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
+ DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
+ DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
+ DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
+ DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
+ DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
+ DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD SAI3_IRQHandler ; SAI3 global Interrupt
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD JPEG_IRQHandler ; JPEG global Interrupt
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD HSEM2_IRQHandler ; HSEM2 global Interrupt
+ DCD ADC3_IRQHandler ; ADC3 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP1_IRQHandler ; COMP1 global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
+ DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it)
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
+ DCD SAI4_IRQHandler ; SAI4 global interrupt
+ DCD 0 ; Reserved
+ DCD HOLD_CORE_IRQHandler ; Hold core interrupt
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_AVD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_AVD_IRQHandler
+ B PVD_AVD_IRQHandler
+
+ PUBWEAK TAMP_STAMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+ B TAMP_STAMP_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream0_IRQHandler
+ B DMA1_Stream0_IRQHandler
+
+ PUBWEAK DMA1_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream1_IRQHandler
+ B DMA1_Stream1_IRQHandler
+
+ PUBWEAK DMA1_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream2_IRQHandler
+ B DMA1_Stream2_IRQHandler
+
+ PUBWEAK DMA1_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream3_IRQHandler
+ B DMA1_Stream3_IRQHandler
+
+ PUBWEAK DMA1_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream4_IRQHandler
+ B DMA1_Stream4_IRQHandler
+
+ PUBWEAK DMA1_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream5_IRQHandler
+ B DMA1_Stream5_IRQHandler
+
+ PUBWEAK DMA1_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream6_IRQHandler
+ B DMA1_Stream6_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK FDCAN1_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+ B FDCAN1_IT0_IRQHandler
+
+ PUBWEAK FDCAN2_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT0_IRQHandler
+ B FDCAN2_IT0_IRQHandler
+
+ PUBWEAK FDCAN1_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+ B FDCAN1_IT1_IRQHandler
+
+ PUBWEAK FDCAN2_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT1_IRQHandler
+ B FDCAN2_IT1_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK TIM8_BRK_TIM12_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_TIM12_IRQHandler
+ B TIM8_BRK_TIM12_IRQHandler
+
+ PUBWEAK TIM8_UP_TIM13_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_TIM13_IRQHandler
+ B TIM8_UP_TIM13_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_TIM14_IRQHandler
+ B TIM8_TRG_COM_TIM14_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK DMA1_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream7_IRQHandler
+ B DMA1_Stream7_IRQHandler
+
+ PUBWEAK FMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+ B FMC_IRQHandler
+
+ PUBWEAK SDMMC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+ B SDMMC1_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream0_IRQHandler
+ B DMA2_Stream0_IRQHandler
+
+ PUBWEAK DMA2_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream1_IRQHandler
+ B DMA2_Stream1_IRQHandler
+
+ PUBWEAK DMA2_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream2_IRQHandler
+ B DMA2_Stream2_IRQHandler
+
+ PUBWEAK DMA2_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream3_IRQHandler
+ B DMA2_Stream3_IRQHandler
+
+ PUBWEAK DMA2_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream4_IRQHandler
+ B DMA2_Stream4_IRQHandler
+
+ PUBWEAK ETH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_IRQHandler
+ B ETH_IRQHandler
+
+ PUBWEAK ETH_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_WKUP_IRQHandler
+ B ETH_WKUP_IRQHandler
+
+ PUBWEAK FDCAN_CAL_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN_CAL_IRQHandler
+ B FDCAN_CAL_IRQHandler
+
+ PUBWEAK CM7_SEV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CM7_SEV_IRQHandler
+ B CM7_SEV_IRQHandler
+
+ PUBWEAK CM4_SEV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CM4_SEV_IRQHandler
+ B CM4_SEV_IRQHandler
+
+ PUBWEAK DMA2_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream5_IRQHandler
+ B DMA2_Stream5_IRQHandler
+
+ PUBWEAK DMA2_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream6_IRQHandler
+ B DMA2_Stream6_IRQHandler
+
+ PUBWEAK DMA2_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream7_IRQHandler
+ B DMA2_Stream7_IRQHandler
+
+ PUBWEAK USART6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler
+ B USART6_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_OUT_IRQHandler
+ B OTG_HS_EP1_OUT_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_IN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_IN_IRQHandler
+ B OTG_HS_EP1_IN_IRQHandler
+
+ PUBWEAK OTG_HS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_WKUP_IRQHandler
+ B OTG_HS_WKUP_IRQHandler
+
+ PUBWEAK OTG_HS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_IRQHandler
+ B OTG_HS_IRQHandler
+
+ PUBWEAK DCMI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_IRQHandler
+ B DCMI_IRQHandler
+
+ PUBWEAK RNG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+ B RNG_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ PUBWEAK UART7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART7_IRQHandler
+ B UART7_IRQHandler
+
+ PUBWEAK UART8_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART8_IRQHandler
+ B UART8_IRQHandler
+
+ PUBWEAK SPI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+ B SPI4_IRQHandler
+
+ PUBWEAK SPI5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI5_IRQHandler
+ B SPI5_IRQHandler
+
+ PUBWEAK SPI6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI6_IRQHandler
+ B SPI6_IRQHandler
+
+ PUBWEAK SAI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+ B SAI1_IRQHandler
+
+ PUBWEAK LTDC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_IRQHandler
+ B LTDC_IRQHandler
+
+ PUBWEAK LTDC_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_ER_IRQHandler
+ B LTDC_ER_IRQHandler
+
+ PUBWEAK DMA2D_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+ B DMA2D_IRQHandler
+
+ PUBWEAK SAI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+ B SAI2_IRQHandler
+
+ PUBWEAK QUADSPI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+ B QUADSPI_IRQHandler
+
+ PUBWEAK LPTIM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+ B LPTIM1_IRQHandler
+
+ PUBWEAK CEC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler
+ B CEC_IRQHandler
+
+ PUBWEAK I2C4_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+ B I2C4_EV_IRQHandler
+
+ PUBWEAK I2C4_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+ B I2C4_ER_IRQHandler
+
+ PUBWEAK SPDIF_RX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPDIF_RX_IRQHandler
+ B SPDIF_RX_IRQHandler
+
+ PUBWEAK OTG_FS_EP1_OUT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_EP1_OUT_IRQHandler
+ B OTG_FS_EP1_OUT_IRQHandler
+
+ PUBWEAK OTG_FS_EP1_IN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_EP1_IN_IRQHandler
+ B OTG_FS_EP1_IN_IRQHandler
+
+ PUBWEAK OTG_FS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_WKUP_IRQHandler
+ B OTG_FS_WKUP_IRQHandler
+
+ PUBWEAK OTG_FS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_IRQHandler
+ B OTG_FS_IRQHandler
+
+ PUBWEAK DMAMUX1_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+ B DMAMUX1_OVR_IRQHandler
+
+ PUBWEAK HRTIM1_Master_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_Master_IRQHandler
+ B HRTIM1_Master_IRQHandler
+
+ PUBWEAK HRTIM1_TIMA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMA_IRQHandler
+ B HRTIM1_TIMA_IRQHandler
+
+ PUBWEAK HRTIM1_TIMB_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMB_IRQHandler
+ B HRTIM1_TIMB_IRQHandler
+
+ PUBWEAK HRTIM1_TIMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMC_IRQHandler
+ B HRTIM1_TIMC_IRQHandler
+
+ PUBWEAK HRTIM1_TIMD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMD_IRQHandler
+ B HRTIM1_TIMD_IRQHandler
+
+ PUBWEAK HRTIM1_TIME_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIME_IRQHandler
+ B HRTIM1_TIME_IRQHandler
+
+ PUBWEAK HRTIM1_FLT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_FLT_IRQHandler
+ B HRTIM1_FLT_IRQHandler
+
+ PUBWEAK DFSDM1_FLT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT0_IRQHandler
+ B DFSDM1_FLT0_IRQHandler
+
+ PUBWEAK DFSDM1_FLT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+ B DFSDM1_FLT1_IRQHandler
+
+ PUBWEAK DFSDM1_FLT2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+ B DFSDM1_FLT2_IRQHandler
+
+ PUBWEAK DFSDM1_FLT3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+ B DFSDM1_FLT3_IRQHandler
+
+ PUBWEAK SAI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI3_IRQHandler
+ B SAI3_IRQHandler
+
+ PUBWEAK SWPMI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SWPMI1_IRQHandler
+ B SWPMI1_IRQHandler
+
+ PUBWEAK TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+ B TIM15_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK MDIOS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_WKUP_IRQHandler
+ B MDIOS_WKUP_IRQHandler
+
+ PUBWEAK MDIOS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_IRQHandler
+ B MDIOS_IRQHandler
+
+ PUBWEAK JPEG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+JPEG_IRQHandler
+ B JPEG_IRQHandler
+
+ PUBWEAK MDMA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDMA_IRQHandler
+ B MDMA_IRQHandler
+
+ PUBWEAK SDMMC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC2_IRQHandler
+ B SDMMC2_IRQHandler
+
+ PUBWEAK HSEM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM1_IRQHandler
+ B HSEM1_IRQHandler
+
+ PUBWEAK HSEM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM2_IRQHandler
+ B HSEM2_IRQHandler
+
+ PUBWEAK ADC3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC3_IRQHandler
+ B ADC3_IRQHandler
+
+ PUBWEAK DMAMUX2_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX2_OVR_IRQHandler
+ B DMAMUX2_OVR_IRQHandler
+
+ PUBWEAK BDMA_Channel0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel0_IRQHandler
+ B BDMA_Channel0_IRQHandler
+
+ PUBWEAK BDMA_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel1_IRQHandler
+ B BDMA_Channel1_IRQHandler
+
+ PUBWEAK BDMA_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel2_IRQHandler
+ B BDMA_Channel2_IRQHandler
+
+ PUBWEAK BDMA_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel3_IRQHandler
+ B BDMA_Channel3_IRQHandler
+
+ PUBWEAK BDMA_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel4_IRQHandler
+ B BDMA_Channel4_IRQHandler
+
+ PUBWEAK BDMA_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel5_IRQHandler
+ B BDMA_Channel5_IRQHandler
+
+ PUBWEAK BDMA_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel6_IRQHandler
+ B BDMA_Channel6_IRQHandler
+
+ PUBWEAK BDMA_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel7_IRQHandler
+ B BDMA_Channel7_IRQHandler
+
+ PUBWEAK COMP1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP1_IRQHandler
+ B COMP1_IRQHandler
+
+ PUBWEAK LPTIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+ B LPTIM2_IRQHandler
+
+ PUBWEAK LPTIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+ B LPTIM3_IRQHandler
+
+ PUBWEAK LPTIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM4_IRQHandler
+ B LPTIM4_IRQHandler
+
+ PUBWEAK LPTIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM5_IRQHandler
+ B LPTIM5_IRQHandler
+
+ PUBWEAK LPUART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+ B LPUART1_IRQHandler
+
+ PUBWEAK WWDG_RST_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_RST_IRQHandler
+ B WWDG_RST_IRQHandler
+
+ PUBWEAK CRS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+ B CRS_IRQHandler
+
+ PUBWEAK ECC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ECC_IRQHandler
+ B ECC_IRQHandler
+
+ PUBWEAK SAI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI4_IRQHandler
+ B SAI4_IRQHandler
+
+ PUBWEAK HOLD_CORE_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HOLD_CORE_IRQHandler
+ B HOLD_CORE_IRQHandler
+
+ PUBWEAK WAKEUP_PIN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WAKEUP_PIN_IRQHandler
+ B WAKEUP_PIN_IRQHandler
+ END
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h747xg.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h747xg.s new file mode 100644 index 0000000..e817249 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h747xg.s @@ -0,0 +1,1007 @@ +;/********************************************************************************
+;* File Name : startup_stm32h747xg.s
+;* Author : MCD Application Team
+;* Description : STM32H747xG devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)
+ DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4
+ DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_IRQHandler ; DCMI
+ DCD 0 ; Reserved
+ DCD RNG_IRQHandler ; Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD QUADSPI_IRQHandler ; QUADSPI
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
+ DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
+ DCD OTG_FS_IRQHandler ; USB OTG FS
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
+ DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
+ DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
+ DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
+ DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
+ DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
+ DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD SAI3_IRQHandler ; SAI3 global Interrupt
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD JPEG_IRQHandler ; JPEG global Interrupt
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD DSI_IRQHandler ; DSI global Interrupt
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD HSEM2_IRQHandler ; HSEM2 global Interrupt
+ DCD ADC3_IRQHandler ; ADC3 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP1_IRQHandler ; COMP1 global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
+ DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it)
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
+ DCD SAI4_IRQHandler ; SAI4 global interrupt
+ DCD 0 ; Reserved
+ DCD HOLD_CORE_IRQHandler ; Hold core interrupt
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_AVD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_AVD_IRQHandler
+ B PVD_AVD_IRQHandler
+
+ PUBWEAK TAMP_STAMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+ B TAMP_STAMP_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream0_IRQHandler
+ B DMA1_Stream0_IRQHandler
+
+ PUBWEAK DMA1_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream1_IRQHandler
+ B DMA1_Stream1_IRQHandler
+
+ PUBWEAK DMA1_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream2_IRQHandler
+ B DMA1_Stream2_IRQHandler
+
+ PUBWEAK DMA1_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream3_IRQHandler
+ B DMA1_Stream3_IRQHandler
+
+ PUBWEAK DMA1_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream4_IRQHandler
+ B DMA1_Stream4_IRQHandler
+
+ PUBWEAK DMA1_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream5_IRQHandler
+ B DMA1_Stream5_IRQHandler
+
+ PUBWEAK DMA1_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream6_IRQHandler
+ B DMA1_Stream6_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK FDCAN1_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+ B FDCAN1_IT0_IRQHandler
+
+ PUBWEAK FDCAN2_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT0_IRQHandler
+ B FDCAN2_IT0_IRQHandler
+
+ PUBWEAK FDCAN1_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+ B FDCAN1_IT1_IRQHandler
+
+ PUBWEAK FDCAN2_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT1_IRQHandler
+ B FDCAN2_IT1_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK TIM8_BRK_TIM12_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_TIM12_IRQHandler
+ B TIM8_BRK_TIM12_IRQHandler
+
+ PUBWEAK TIM8_UP_TIM13_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_TIM13_IRQHandler
+ B TIM8_UP_TIM13_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_TIM14_IRQHandler
+ B TIM8_TRG_COM_TIM14_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK DMA1_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream7_IRQHandler
+ B DMA1_Stream7_IRQHandler
+
+ PUBWEAK FMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+ B FMC_IRQHandler
+
+ PUBWEAK SDMMC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+ B SDMMC1_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream0_IRQHandler
+ B DMA2_Stream0_IRQHandler
+
+ PUBWEAK DMA2_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream1_IRQHandler
+ B DMA2_Stream1_IRQHandler
+
+ PUBWEAK DMA2_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream2_IRQHandler
+ B DMA2_Stream2_IRQHandler
+
+ PUBWEAK DMA2_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream3_IRQHandler
+ B DMA2_Stream3_IRQHandler
+
+ PUBWEAK DMA2_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream4_IRQHandler
+ B DMA2_Stream4_IRQHandler
+
+ PUBWEAK ETH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_IRQHandler
+ B ETH_IRQHandler
+
+ PUBWEAK ETH_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_WKUP_IRQHandler
+ B ETH_WKUP_IRQHandler
+
+ PUBWEAK FDCAN_CAL_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN_CAL_IRQHandler
+ B FDCAN_CAL_IRQHandler
+
+ PUBWEAK CM7_SEV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CM7_SEV_IRQHandler
+ B CM7_SEV_IRQHandler
+
+ PUBWEAK CM4_SEV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CM4_SEV_IRQHandler
+ B CM4_SEV_IRQHandler
+
+ PUBWEAK DMA2_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream5_IRQHandler
+ B DMA2_Stream5_IRQHandler
+
+ PUBWEAK DMA2_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream6_IRQHandler
+ B DMA2_Stream6_IRQHandler
+
+ PUBWEAK DMA2_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream7_IRQHandler
+ B DMA2_Stream7_IRQHandler
+
+ PUBWEAK USART6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler
+ B USART6_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_OUT_IRQHandler
+ B OTG_HS_EP1_OUT_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_IN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_IN_IRQHandler
+ B OTG_HS_EP1_IN_IRQHandler
+
+ PUBWEAK OTG_HS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_WKUP_IRQHandler
+ B OTG_HS_WKUP_IRQHandler
+
+ PUBWEAK OTG_HS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_IRQHandler
+ B OTG_HS_IRQHandler
+
+ PUBWEAK DCMI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_IRQHandler
+ B DCMI_IRQHandler
+
+ PUBWEAK RNG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+ B RNG_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ PUBWEAK UART7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART7_IRQHandler
+ B UART7_IRQHandler
+
+ PUBWEAK UART8_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART8_IRQHandler
+ B UART8_IRQHandler
+
+ PUBWEAK SPI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+ B SPI4_IRQHandler
+
+ PUBWEAK SPI5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI5_IRQHandler
+ B SPI5_IRQHandler
+
+ PUBWEAK SPI6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI6_IRQHandler
+ B SPI6_IRQHandler
+
+ PUBWEAK SAI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+ B SAI1_IRQHandler
+
+ PUBWEAK LTDC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_IRQHandler
+ B LTDC_IRQHandler
+
+ PUBWEAK LTDC_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_ER_IRQHandler
+ B LTDC_ER_IRQHandler
+
+ PUBWEAK DMA2D_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+ B DMA2D_IRQHandler
+
+ PUBWEAK SAI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+ B SAI2_IRQHandler
+
+ PUBWEAK QUADSPI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+ B QUADSPI_IRQHandler
+
+ PUBWEAK LPTIM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+ B LPTIM1_IRQHandler
+
+ PUBWEAK CEC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler
+ B CEC_IRQHandler
+
+ PUBWEAK I2C4_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+ B I2C4_EV_IRQHandler
+
+ PUBWEAK I2C4_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+ B I2C4_ER_IRQHandler
+
+ PUBWEAK SPDIF_RX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPDIF_RX_IRQHandler
+ B SPDIF_RX_IRQHandler
+
+ PUBWEAK OTG_FS_EP1_OUT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_EP1_OUT_IRQHandler
+ B OTG_FS_EP1_OUT_IRQHandler
+
+ PUBWEAK OTG_FS_EP1_IN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_EP1_IN_IRQHandler
+ B OTG_FS_EP1_IN_IRQHandler
+
+ PUBWEAK OTG_FS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_WKUP_IRQHandler
+ B OTG_FS_WKUP_IRQHandler
+
+ PUBWEAK OTG_FS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_IRQHandler
+ B OTG_FS_IRQHandler
+
+ PUBWEAK DMAMUX1_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+ B DMAMUX1_OVR_IRQHandler
+
+ PUBWEAK HRTIM1_Master_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_Master_IRQHandler
+ B HRTIM1_Master_IRQHandler
+
+ PUBWEAK HRTIM1_TIMA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMA_IRQHandler
+ B HRTIM1_TIMA_IRQHandler
+
+ PUBWEAK HRTIM1_TIMB_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMB_IRQHandler
+ B HRTIM1_TIMB_IRQHandler
+
+ PUBWEAK HRTIM1_TIMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMC_IRQHandler
+ B HRTIM1_TIMC_IRQHandler
+
+ PUBWEAK HRTIM1_TIMD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMD_IRQHandler
+ B HRTIM1_TIMD_IRQHandler
+
+ PUBWEAK HRTIM1_TIME_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIME_IRQHandler
+ B HRTIM1_TIME_IRQHandler
+
+ PUBWEAK HRTIM1_FLT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_FLT_IRQHandler
+ B HRTIM1_FLT_IRQHandler
+
+ PUBWEAK DFSDM1_FLT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT0_IRQHandler
+ B DFSDM1_FLT0_IRQHandler
+
+ PUBWEAK DFSDM1_FLT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+ B DFSDM1_FLT1_IRQHandler
+
+ PUBWEAK DFSDM1_FLT2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+ B DFSDM1_FLT2_IRQHandler
+
+ PUBWEAK DFSDM1_FLT3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+ B DFSDM1_FLT3_IRQHandler
+
+ PUBWEAK SAI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI3_IRQHandler
+ B SAI3_IRQHandler
+
+ PUBWEAK SWPMI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SWPMI1_IRQHandler
+ B SWPMI1_IRQHandler
+
+ PUBWEAK TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+ B TIM15_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK MDIOS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_WKUP_IRQHandler
+ B MDIOS_WKUP_IRQHandler
+
+ PUBWEAK MDIOS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_IRQHandler
+ B MDIOS_IRQHandler
+
+ PUBWEAK JPEG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+JPEG_IRQHandler
+ B JPEG_IRQHandler
+
+ PUBWEAK MDMA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDMA_IRQHandler
+ B MDMA_IRQHandler
+
+ PUBWEAK DSI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DSI_IRQHandler
+ B DSI_IRQHandler
+
+ PUBWEAK SDMMC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC2_IRQHandler
+ B SDMMC2_IRQHandler
+
+ PUBWEAK HSEM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM1_IRQHandler
+ B HSEM1_IRQHandler
+
+ PUBWEAK HSEM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM2_IRQHandler
+ B HSEM2_IRQHandler
+
+ PUBWEAK ADC3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC3_IRQHandler
+ B ADC3_IRQHandler
+
+ PUBWEAK DMAMUX2_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX2_OVR_IRQHandler
+ B DMAMUX2_OVR_IRQHandler
+
+ PUBWEAK BDMA_Channel0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel0_IRQHandler
+ B BDMA_Channel0_IRQHandler
+
+ PUBWEAK BDMA_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel1_IRQHandler
+ B BDMA_Channel1_IRQHandler
+
+ PUBWEAK BDMA_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel2_IRQHandler
+ B BDMA_Channel2_IRQHandler
+
+ PUBWEAK BDMA_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel3_IRQHandler
+ B BDMA_Channel3_IRQHandler
+
+ PUBWEAK BDMA_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel4_IRQHandler
+ B BDMA_Channel4_IRQHandler
+
+ PUBWEAK BDMA_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel5_IRQHandler
+ B BDMA_Channel5_IRQHandler
+
+ PUBWEAK BDMA_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel6_IRQHandler
+ B BDMA_Channel6_IRQHandler
+
+ PUBWEAK BDMA_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel7_IRQHandler
+ B BDMA_Channel7_IRQHandler
+
+ PUBWEAK COMP1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP1_IRQHandler
+ B COMP1_IRQHandler
+
+ PUBWEAK LPTIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+ B LPTIM2_IRQHandler
+
+ PUBWEAK LPTIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+ B LPTIM3_IRQHandler
+
+ PUBWEAK LPTIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM4_IRQHandler
+ B LPTIM4_IRQHandler
+
+ PUBWEAK LPTIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM5_IRQHandler
+ B LPTIM5_IRQHandler
+
+ PUBWEAK LPUART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+ B LPUART1_IRQHandler
+
+ PUBWEAK WWDG_RST_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_RST_IRQHandler
+ B WWDG_RST_IRQHandler
+
+ PUBWEAK CRS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+ B CRS_IRQHandler
+
+ PUBWEAK ECC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ECC_IRQHandler
+ B ECC_IRQHandler
+
+ PUBWEAK SAI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI4_IRQHandler
+ B SAI4_IRQHandler
+
+ PUBWEAK HOLD_CORE_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HOLD_CORE_IRQHandler
+ B HOLD_CORE_IRQHandler
+
+ PUBWEAK WAKEUP_PIN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WAKEUP_PIN_IRQHandler
+ B WAKEUP_PIN_IRQHandler
+ END
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h747xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h747xx.s new file mode 100644 index 0000000..07fbb19 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h747xx.s @@ -0,0 +1,1007 @@ +;/********************************************************************************
+;* File Name : startup_stm32h747xx.s
+;* Author : MCD Application Team
+;* Description : STM32H747xx devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)
+ DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4
+ DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_IRQHandler ; DCMI
+ DCD 0 ; Reserved
+ DCD RNG_IRQHandler ; Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD QUADSPI_IRQHandler ; QUADSPI
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
+ DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
+ DCD OTG_FS_IRQHandler ; USB OTG FS
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
+ DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
+ DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
+ DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
+ DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
+ DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
+ DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD SAI3_IRQHandler ; SAI3 global Interrupt
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD JPEG_IRQHandler ; JPEG global Interrupt
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD DSI_IRQHandler ; DSI global Interrupt
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD HSEM2_IRQHandler ; HSEM2 global Interrupt
+ DCD ADC3_IRQHandler ; ADC3 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP1_IRQHandler ; COMP1 global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
+ DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it)
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
+ DCD SAI4_IRQHandler ; SAI4 global interrupt
+ DCD 0 ; Reserved
+ DCD HOLD_CORE_IRQHandler ; Hold core interrupt
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_AVD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_AVD_IRQHandler
+ B PVD_AVD_IRQHandler
+
+ PUBWEAK TAMP_STAMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+ B TAMP_STAMP_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream0_IRQHandler
+ B DMA1_Stream0_IRQHandler
+
+ PUBWEAK DMA1_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream1_IRQHandler
+ B DMA1_Stream1_IRQHandler
+
+ PUBWEAK DMA1_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream2_IRQHandler
+ B DMA1_Stream2_IRQHandler
+
+ PUBWEAK DMA1_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream3_IRQHandler
+ B DMA1_Stream3_IRQHandler
+
+ PUBWEAK DMA1_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream4_IRQHandler
+ B DMA1_Stream4_IRQHandler
+
+ PUBWEAK DMA1_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream5_IRQHandler
+ B DMA1_Stream5_IRQHandler
+
+ PUBWEAK DMA1_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream6_IRQHandler
+ B DMA1_Stream6_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK FDCAN1_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+ B FDCAN1_IT0_IRQHandler
+
+ PUBWEAK FDCAN2_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT0_IRQHandler
+ B FDCAN2_IT0_IRQHandler
+
+ PUBWEAK FDCAN1_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+ B FDCAN1_IT1_IRQHandler
+
+ PUBWEAK FDCAN2_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT1_IRQHandler
+ B FDCAN2_IT1_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK TIM8_BRK_TIM12_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_TIM12_IRQHandler
+ B TIM8_BRK_TIM12_IRQHandler
+
+ PUBWEAK TIM8_UP_TIM13_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_TIM13_IRQHandler
+ B TIM8_UP_TIM13_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_TIM14_IRQHandler
+ B TIM8_TRG_COM_TIM14_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK DMA1_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream7_IRQHandler
+ B DMA1_Stream7_IRQHandler
+
+ PUBWEAK FMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+ B FMC_IRQHandler
+
+ PUBWEAK SDMMC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+ B SDMMC1_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream0_IRQHandler
+ B DMA2_Stream0_IRQHandler
+
+ PUBWEAK DMA2_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream1_IRQHandler
+ B DMA2_Stream1_IRQHandler
+
+ PUBWEAK DMA2_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream2_IRQHandler
+ B DMA2_Stream2_IRQHandler
+
+ PUBWEAK DMA2_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream3_IRQHandler
+ B DMA2_Stream3_IRQHandler
+
+ PUBWEAK DMA2_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream4_IRQHandler
+ B DMA2_Stream4_IRQHandler
+
+ PUBWEAK ETH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_IRQHandler
+ B ETH_IRQHandler
+
+ PUBWEAK ETH_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_WKUP_IRQHandler
+ B ETH_WKUP_IRQHandler
+
+ PUBWEAK FDCAN_CAL_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN_CAL_IRQHandler
+ B FDCAN_CAL_IRQHandler
+
+ PUBWEAK CM7_SEV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CM7_SEV_IRQHandler
+ B CM7_SEV_IRQHandler
+
+ PUBWEAK CM4_SEV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CM4_SEV_IRQHandler
+ B CM4_SEV_IRQHandler
+
+ PUBWEAK DMA2_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream5_IRQHandler
+ B DMA2_Stream5_IRQHandler
+
+ PUBWEAK DMA2_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream6_IRQHandler
+ B DMA2_Stream6_IRQHandler
+
+ PUBWEAK DMA2_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream7_IRQHandler
+ B DMA2_Stream7_IRQHandler
+
+ PUBWEAK USART6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler
+ B USART6_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_OUT_IRQHandler
+ B OTG_HS_EP1_OUT_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_IN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_IN_IRQHandler
+ B OTG_HS_EP1_IN_IRQHandler
+
+ PUBWEAK OTG_HS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_WKUP_IRQHandler
+ B OTG_HS_WKUP_IRQHandler
+
+ PUBWEAK OTG_HS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_IRQHandler
+ B OTG_HS_IRQHandler
+
+ PUBWEAK DCMI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_IRQHandler
+ B DCMI_IRQHandler
+
+ PUBWEAK RNG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+ B RNG_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ PUBWEAK UART7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART7_IRQHandler
+ B UART7_IRQHandler
+
+ PUBWEAK UART8_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART8_IRQHandler
+ B UART8_IRQHandler
+
+ PUBWEAK SPI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+ B SPI4_IRQHandler
+
+ PUBWEAK SPI5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI5_IRQHandler
+ B SPI5_IRQHandler
+
+ PUBWEAK SPI6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI6_IRQHandler
+ B SPI6_IRQHandler
+
+ PUBWEAK SAI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+ B SAI1_IRQHandler
+
+ PUBWEAK LTDC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_IRQHandler
+ B LTDC_IRQHandler
+
+ PUBWEAK LTDC_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_ER_IRQHandler
+ B LTDC_ER_IRQHandler
+
+ PUBWEAK DMA2D_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+ B DMA2D_IRQHandler
+
+ PUBWEAK SAI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+ B SAI2_IRQHandler
+
+ PUBWEAK QUADSPI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+ B QUADSPI_IRQHandler
+
+ PUBWEAK LPTIM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+ B LPTIM1_IRQHandler
+
+ PUBWEAK CEC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler
+ B CEC_IRQHandler
+
+ PUBWEAK I2C4_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+ B I2C4_EV_IRQHandler
+
+ PUBWEAK I2C4_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+ B I2C4_ER_IRQHandler
+
+ PUBWEAK SPDIF_RX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPDIF_RX_IRQHandler
+ B SPDIF_RX_IRQHandler
+
+ PUBWEAK OTG_FS_EP1_OUT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_EP1_OUT_IRQHandler
+ B OTG_FS_EP1_OUT_IRQHandler
+
+ PUBWEAK OTG_FS_EP1_IN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_EP1_IN_IRQHandler
+ B OTG_FS_EP1_IN_IRQHandler
+
+ PUBWEAK OTG_FS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_WKUP_IRQHandler
+ B OTG_FS_WKUP_IRQHandler
+
+ PUBWEAK OTG_FS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_IRQHandler
+ B OTG_FS_IRQHandler
+
+ PUBWEAK DMAMUX1_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+ B DMAMUX1_OVR_IRQHandler
+
+ PUBWEAK HRTIM1_Master_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_Master_IRQHandler
+ B HRTIM1_Master_IRQHandler
+
+ PUBWEAK HRTIM1_TIMA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMA_IRQHandler
+ B HRTIM1_TIMA_IRQHandler
+
+ PUBWEAK HRTIM1_TIMB_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMB_IRQHandler
+ B HRTIM1_TIMB_IRQHandler
+
+ PUBWEAK HRTIM1_TIMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMC_IRQHandler
+ B HRTIM1_TIMC_IRQHandler
+
+ PUBWEAK HRTIM1_TIMD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMD_IRQHandler
+ B HRTIM1_TIMD_IRQHandler
+
+ PUBWEAK HRTIM1_TIME_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIME_IRQHandler
+ B HRTIM1_TIME_IRQHandler
+
+ PUBWEAK HRTIM1_FLT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_FLT_IRQHandler
+ B HRTIM1_FLT_IRQHandler
+
+ PUBWEAK DFSDM1_FLT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT0_IRQHandler
+ B DFSDM1_FLT0_IRQHandler
+
+ PUBWEAK DFSDM1_FLT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+ B DFSDM1_FLT1_IRQHandler
+
+ PUBWEAK DFSDM1_FLT2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+ B DFSDM1_FLT2_IRQHandler
+
+ PUBWEAK DFSDM1_FLT3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+ B DFSDM1_FLT3_IRQHandler
+
+ PUBWEAK SAI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI3_IRQHandler
+ B SAI3_IRQHandler
+
+ PUBWEAK SWPMI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SWPMI1_IRQHandler
+ B SWPMI1_IRQHandler
+
+ PUBWEAK TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+ B TIM15_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK MDIOS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_WKUP_IRQHandler
+ B MDIOS_WKUP_IRQHandler
+
+ PUBWEAK MDIOS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_IRQHandler
+ B MDIOS_IRQHandler
+
+ PUBWEAK JPEG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+JPEG_IRQHandler
+ B JPEG_IRQHandler
+
+ PUBWEAK MDMA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDMA_IRQHandler
+ B MDMA_IRQHandler
+
+ PUBWEAK DSI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DSI_IRQHandler
+ B DSI_IRQHandler
+
+ PUBWEAK SDMMC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC2_IRQHandler
+ B SDMMC2_IRQHandler
+
+ PUBWEAK HSEM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM1_IRQHandler
+ B HSEM1_IRQHandler
+
+ PUBWEAK HSEM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM2_IRQHandler
+ B HSEM2_IRQHandler
+
+ PUBWEAK ADC3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC3_IRQHandler
+ B ADC3_IRQHandler
+
+ PUBWEAK DMAMUX2_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX2_OVR_IRQHandler
+ B DMAMUX2_OVR_IRQHandler
+
+ PUBWEAK BDMA_Channel0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel0_IRQHandler
+ B BDMA_Channel0_IRQHandler
+
+ PUBWEAK BDMA_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel1_IRQHandler
+ B BDMA_Channel1_IRQHandler
+
+ PUBWEAK BDMA_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel2_IRQHandler
+ B BDMA_Channel2_IRQHandler
+
+ PUBWEAK BDMA_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel3_IRQHandler
+ B BDMA_Channel3_IRQHandler
+
+ PUBWEAK BDMA_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel4_IRQHandler
+ B BDMA_Channel4_IRQHandler
+
+ PUBWEAK BDMA_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel5_IRQHandler
+ B BDMA_Channel5_IRQHandler
+
+ PUBWEAK BDMA_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel6_IRQHandler
+ B BDMA_Channel6_IRQHandler
+
+ PUBWEAK BDMA_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel7_IRQHandler
+ B BDMA_Channel7_IRQHandler
+
+ PUBWEAK COMP1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP1_IRQHandler
+ B COMP1_IRQHandler
+
+ PUBWEAK LPTIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+ B LPTIM2_IRQHandler
+
+ PUBWEAK LPTIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+ B LPTIM3_IRQHandler
+
+ PUBWEAK LPTIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM4_IRQHandler
+ B LPTIM4_IRQHandler
+
+ PUBWEAK LPTIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM5_IRQHandler
+ B LPTIM5_IRQHandler
+
+ PUBWEAK LPUART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+ B LPUART1_IRQHandler
+
+ PUBWEAK WWDG_RST_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_RST_IRQHandler
+ B WWDG_RST_IRQHandler
+
+ PUBWEAK CRS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+ B CRS_IRQHandler
+
+ PUBWEAK ECC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ECC_IRQHandler
+ B ECC_IRQHandler
+
+ PUBWEAK SAI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI4_IRQHandler
+ B SAI4_IRQHandler
+
+ PUBWEAK HOLD_CORE_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HOLD_CORE_IRQHandler
+ B HOLD_CORE_IRQHandler
+
+ PUBWEAK WAKEUP_PIN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WAKEUP_PIN_IRQHandler
+ B WAKEUP_PIN_IRQHandler
+ END
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h750xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h750xx.s new file mode 100644 index 0000000..08f62a3 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h750xx.s @@ -0,0 +1,982 @@ +;/********************************************************************************
+;* File Name : startup_stm32h750xx.s
+;* Author : MCD Application Team
+;* Description : STM32H750xx devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2018 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it)
+ DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_IRQHandler ; DCMI
+ DCD CRYP_IRQHandler ; CRYP crypto
+ DCD HASH_RNG_IRQHandler ; Hash and Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD QUADSPI_IRQHandler ; QUADSPI
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
+ DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
+ DCD OTG_FS_IRQHandler ; USB OTG FS
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
+ DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
+ DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
+ DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
+ DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
+ DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
+ DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD SAI3_IRQHandler ; SAI3 global Interrupt
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD JPEG_IRQHandler ; JPEG global Interrupt
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD 0 ; Reserved
+ DCD ADC3_IRQHandler ; ADC3 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP1_IRQHandler ; COMP1 global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
+ DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD 0 ; Reserved
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
+ DCD SAI4_IRQHandler ; SAI4 global interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_AVD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_AVD_IRQHandler
+ B PVD_AVD_IRQHandler
+
+ PUBWEAK TAMP_STAMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+ B TAMP_STAMP_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream0_IRQHandler
+ B DMA1_Stream0_IRQHandler
+
+ PUBWEAK DMA1_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream1_IRQHandler
+ B DMA1_Stream1_IRQHandler
+
+ PUBWEAK DMA1_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream2_IRQHandler
+ B DMA1_Stream2_IRQHandler
+
+ PUBWEAK DMA1_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream3_IRQHandler
+ B DMA1_Stream3_IRQHandler
+
+ PUBWEAK DMA1_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream4_IRQHandler
+ B DMA1_Stream4_IRQHandler
+
+ PUBWEAK DMA1_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream5_IRQHandler
+ B DMA1_Stream5_IRQHandler
+
+ PUBWEAK DMA1_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream6_IRQHandler
+ B DMA1_Stream6_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK FDCAN1_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+ B FDCAN1_IT0_IRQHandler
+
+ PUBWEAK FDCAN2_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT0_IRQHandler
+ B FDCAN2_IT0_IRQHandler
+
+ PUBWEAK FDCAN1_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+ B FDCAN1_IT1_IRQHandler
+
+ PUBWEAK FDCAN2_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT1_IRQHandler
+ B FDCAN2_IT1_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK TIM8_BRK_TIM12_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_TIM12_IRQHandler
+ B TIM8_BRK_TIM12_IRQHandler
+
+ PUBWEAK TIM8_UP_TIM13_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_TIM13_IRQHandler
+ B TIM8_UP_TIM13_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_TIM14_IRQHandler
+ B TIM8_TRG_COM_TIM14_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK DMA1_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream7_IRQHandler
+ B DMA1_Stream7_IRQHandler
+
+ PUBWEAK FMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+ B FMC_IRQHandler
+
+ PUBWEAK SDMMC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+ B SDMMC1_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream0_IRQHandler
+ B DMA2_Stream0_IRQHandler
+
+ PUBWEAK DMA2_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream1_IRQHandler
+ B DMA2_Stream1_IRQHandler
+
+ PUBWEAK DMA2_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream2_IRQHandler
+ B DMA2_Stream2_IRQHandler
+
+ PUBWEAK DMA2_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream3_IRQHandler
+ B DMA2_Stream3_IRQHandler
+
+ PUBWEAK DMA2_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream4_IRQHandler
+ B DMA2_Stream4_IRQHandler
+
+ PUBWEAK ETH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_IRQHandler
+ B ETH_IRQHandler
+
+ PUBWEAK ETH_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_WKUP_IRQHandler
+ B ETH_WKUP_IRQHandler
+
+ PUBWEAK FDCAN_CAL_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN_CAL_IRQHandler
+ B FDCAN_CAL_IRQHandler
+
+ PUBWEAK DMA2_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream5_IRQHandler
+ B DMA2_Stream5_IRQHandler
+
+ PUBWEAK DMA2_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream6_IRQHandler
+ B DMA2_Stream6_IRQHandler
+
+ PUBWEAK DMA2_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream7_IRQHandler
+ B DMA2_Stream7_IRQHandler
+
+ PUBWEAK USART6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler
+ B USART6_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_OUT_IRQHandler
+ B OTG_HS_EP1_OUT_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_IN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_IN_IRQHandler
+ B OTG_HS_EP1_IN_IRQHandler
+
+ PUBWEAK OTG_HS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_WKUP_IRQHandler
+ B OTG_HS_WKUP_IRQHandler
+
+ PUBWEAK OTG_HS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_IRQHandler
+ B OTG_HS_IRQHandler
+
+ PUBWEAK DCMI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_IRQHandler
+ B DCMI_IRQHandler
+
+ PUBWEAK CRYP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CRYP_IRQHandler
+ B CRYP_IRQHandler
+
+ PUBWEAK HASH_RNG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HASH_RNG_IRQHandler
+ B HASH_RNG_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ PUBWEAK UART7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART7_IRQHandler
+ B UART7_IRQHandler
+
+ PUBWEAK UART8_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART8_IRQHandler
+ B UART8_IRQHandler
+
+ PUBWEAK SPI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+ B SPI4_IRQHandler
+
+ PUBWEAK SPI5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI5_IRQHandler
+ B SPI5_IRQHandler
+
+ PUBWEAK SPI6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI6_IRQHandler
+ B SPI6_IRQHandler
+
+ PUBWEAK SAI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+ B SAI1_IRQHandler
+
+ PUBWEAK LTDC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_IRQHandler
+ B LTDC_IRQHandler
+
+ PUBWEAK LTDC_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_ER_IRQHandler
+ B LTDC_ER_IRQHandler
+
+ PUBWEAK DMA2D_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+ B DMA2D_IRQHandler
+
+ PUBWEAK SAI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+ B SAI2_IRQHandler
+
+ PUBWEAK QUADSPI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+ B QUADSPI_IRQHandler
+
+ PUBWEAK LPTIM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+ B LPTIM1_IRQHandler
+
+ PUBWEAK CEC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler
+ B CEC_IRQHandler
+
+ PUBWEAK I2C4_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+ B I2C4_EV_IRQHandler
+
+ PUBWEAK I2C4_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+ B I2C4_ER_IRQHandler
+
+ PUBWEAK SPDIF_RX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPDIF_RX_IRQHandler
+ B SPDIF_RX_IRQHandler
+
+ PUBWEAK OTG_FS_EP1_OUT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_EP1_OUT_IRQHandler
+ B OTG_FS_EP1_OUT_IRQHandler
+
+ PUBWEAK OTG_FS_EP1_IN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_EP1_IN_IRQHandler
+ B OTG_FS_EP1_IN_IRQHandler
+
+ PUBWEAK OTG_FS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_WKUP_IRQHandler
+ B OTG_FS_WKUP_IRQHandler
+
+ PUBWEAK OTG_FS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_IRQHandler
+ B OTG_FS_IRQHandler
+
+ PUBWEAK DMAMUX1_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+ B DMAMUX1_OVR_IRQHandler
+
+ PUBWEAK HRTIM1_Master_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_Master_IRQHandler
+ B HRTIM1_Master_IRQHandler
+
+ PUBWEAK HRTIM1_TIMA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMA_IRQHandler
+ B HRTIM1_TIMA_IRQHandler
+
+ PUBWEAK HRTIM1_TIMB_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMB_IRQHandler
+ B HRTIM1_TIMB_IRQHandler
+
+ PUBWEAK HRTIM1_TIMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMC_IRQHandler
+ B HRTIM1_TIMC_IRQHandler
+
+ PUBWEAK HRTIM1_TIMD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMD_IRQHandler
+ B HRTIM1_TIMD_IRQHandler
+
+ PUBWEAK HRTIM1_TIME_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIME_IRQHandler
+ B HRTIM1_TIME_IRQHandler
+
+ PUBWEAK HRTIM1_FLT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_FLT_IRQHandler
+ B HRTIM1_FLT_IRQHandler
+
+ PUBWEAK DFSDM1_FLT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT0_IRQHandler
+ B DFSDM1_FLT0_IRQHandler
+
+ PUBWEAK DFSDM1_FLT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+ B DFSDM1_FLT1_IRQHandler
+
+ PUBWEAK DFSDM1_FLT2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+ B DFSDM1_FLT2_IRQHandler
+
+ PUBWEAK DFSDM1_FLT3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+ B DFSDM1_FLT3_IRQHandler
+
+ PUBWEAK SAI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI3_IRQHandler
+ B SAI3_IRQHandler
+
+ PUBWEAK SWPMI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SWPMI1_IRQHandler
+ B SWPMI1_IRQHandler
+
+ PUBWEAK TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+ B TIM15_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK MDIOS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_WKUP_IRQHandler
+ B MDIOS_WKUP_IRQHandler
+
+ PUBWEAK MDIOS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_IRQHandler
+ B MDIOS_IRQHandler
+
+ PUBWEAK JPEG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+JPEG_IRQHandler
+ B JPEG_IRQHandler
+
+ PUBWEAK MDMA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDMA_IRQHandler
+ B MDMA_IRQHandler
+
+ PUBWEAK SDMMC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC2_IRQHandler
+ B SDMMC2_IRQHandler
+
+ PUBWEAK HSEM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM1_IRQHandler
+ B HSEM1_IRQHandler
+
+ PUBWEAK ADC3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC3_IRQHandler
+ B ADC3_IRQHandler
+
+ PUBWEAK DMAMUX2_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX2_OVR_IRQHandler
+ B DMAMUX2_OVR_IRQHandler
+
+ PUBWEAK BDMA_Channel0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel0_IRQHandler
+ B BDMA_Channel0_IRQHandler
+
+ PUBWEAK BDMA_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel1_IRQHandler
+ B BDMA_Channel1_IRQHandler
+
+ PUBWEAK BDMA_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel2_IRQHandler
+ B BDMA_Channel2_IRQHandler
+
+ PUBWEAK BDMA_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel3_IRQHandler
+ B BDMA_Channel3_IRQHandler
+
+ PUBWEAK BDMA_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel4_IRQHandler
+ B BDMA_Channel4_IRQHandler
+
+ PUBWEAK BDMA_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel5_IRQHandler
+ B BDMA_Channel5_IRQHandler
+
+ PUBWEAK BDMA_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel6_IRQHandler
+ B BDMA_Channel6_IRQHandler
+
+ PUBWEAK BDMA_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel7_IRQHandler
+ B BDMA_Channel7_IRQHandler
+
+ PUBWEAK COMP1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP1_IRQHandler
+ B COMP1_IRQHandler
+
+ PUBWEAK LPTIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+ B LPTIM2_IRQHandler
+
+ PUBWEAK LPTIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+ B LPTIM3_IRQHandler
+
+ PUBWEAK LPTIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM4_IRQHandler
+ B LPTIM4_IRQHandler
+
+ PUBWEAK LPTIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM5_IRQHandler
+ B LPTIM5_IRQHandler
+
+ PUBWEAK LPUART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+ B LPUART1_IRQHandler
+
+ PUBWEAK CRS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+ B CRS_IRQHandler
+
+ PUBWEAK ECC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ECC_IRQHandler
+ B ECC_IRQHandler
+
+ PUBWEAK SAI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI4_IRQHandler
+ B SAI4_IRQHandler
+
+ PUBWEAK WAKEUP_PIN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WAKEUP_PIN_IRQHandler
+ B WAKEUP_PIN_IRQHandler
+ END
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h753xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h753xx.s new file mode 100644 index 0000000..ef5bb33 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h753xx.s @@ -0,0 +1,982 @@ +;/********************************************************************************
+;* File Name : startup_stm32h753xx.s
+;* Author : MCD Application Team
+;* Description : STM32H753xx devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it)
+ DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_IRQHandler ; DCMI
+ DCD CRYP_IRQHandler ; CRYP crypto
+ DCD HASH_RNG_IRQHandler ; Hash and Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD QUADSPI_IRQHandler ; QUADSPI
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
+ DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
+ DCD OTG_FS_IRQHandler ; USB OTG FS
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
+ DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
+ DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
+ DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
+ DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
+ DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
+ DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD SAI3_IRQHandler ; SAI3 global Interrupt
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD JPEG_IRQHandler ; JPEG global Interrupt
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD 0 ; Reserved
+ DCD ADC3_IRQHandler ; ADC3 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP1_IRQHandler ; COMP1 global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
+ DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD 0 ; Reserved
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
+ DCD SAI4_IRQHandler ; SAI4 global interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_AVD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_AVD_IRQHandler
+ B PVD_AVD_IRQHandler
+
+ PUBWEAK TAMP_STAMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+ B TAMP_STAMP_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream0_IRQHandler
+ B DMA1_Stream0_IRQHandler
+
+ PUBWEAK DMA1_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream1_IRQHandler
+ B DMA1_Stream1_IRQHandler
+
+ PUBWEAK DMA1_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream2_IRQHandler
+ B DMA1_Stream2_IRQHandler
+
+ PUBWEAK DMA1_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream3_IRQHandler
+ B DMA1_Stream3_IRQHandler
+
+ PUBWEAK DMA1_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream4_IRQHandler
+ B DMA1_Stream4_IRQHandler
+
+ PUBWEAK DMA1_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream5_IRQHandler
+ B DMA1_Stream5_IRQHandler
+
+ PUBWEAK DMA1_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream6_IRQHandler
+ B DMA1_Stream6_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK FDCAN1_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+ B FDCAN1_IT0_IRQHandler
+
+ PUBWEAK FDCAN2_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT0_IRQHandler
+ B FDCAN2_IT0_IRQHandler
+
+ PUBWEAK FDCAN1_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+ B FDCAN1_IT1_IRQHandler
+
+ PUBWEAK FDCAN2_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT1_IRQHandler
+ B FDCAN2_IT1_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK TIM8_BRK_TIM12_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_TIM12_IRQHandler
+ B TIM8_BRK_TIM12_IRQHandler
+
+ PUBWEAK TIM8_UP_TIM13_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_TIM13_IRQHandler
+ B TIM8_UP_TIM13_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_TIM14_IRQHandler
+ B TIM8_TRG_COM_TIM14_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK DMA1_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream7_IRQHandler
+ B DMA1_Stream7_IRQHandler
+
+ PUBWEAK FMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+ B FMC_IRQHandler
+
+ PUBWEAK SDMMC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+ B SDMMC1_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream0_IRQHandler
+ B DMA2_Stream0_IRQHandler
+
+ PUBWEAK DMA2_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream1_IRQHandler
+ B DMA2_Stream1_IRQHandler
+
+ PUBWEAK DMA2_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream2_IRQHandler
+ B DMA2_Stream2_IRQHandler
+
+ PUBWEAK DMA2_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream3_IRQHandler
+ B DMA2_Stream3_IRQHandler
+
+ PUBWEAK DMA2_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream4_IRQHandler
+ B DMA2_Stream4_IRQHandler
+
+ PUBWEAK ETH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_IRQHandler
+ B ETH_IRQHandler
+
+ PUBWEAK ETH_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_WKUP_IRQHandler
+ B ETH_WKUP_IRQHandler
+
+ PUBWEAK FDCAN_CAL_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN_CAL_IRQHandler
+ B FDCAN_CAL_IRQHandler
+
+ PUBWEAK DMA2_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream5_IRQHandler
+ B DMA2_Stream5_IRQHandler
+
+ PUBWEAK DMA2_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream6_IRQHandler
+ B DMA2_Stream6_IRQHandler
+
+ PUBWEAK DMA2_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream7_IRQHandler
+ B DMA2_Stream7_IRQHandler
+
+ PUBWEAK USART6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler
+ B USART6_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_OUT_IRQHandler
+ B OTG_HS_EP1_OUT_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_IN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_IN_IRQHandler
+ B OTG_HS_EP1_IN_IRQHandler
+
+ PUBWEAK OTG_HS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_WKUP_IRQHandler
+ B OTG_HS_WKUP_IRQHandler
+
+ PUBWEAK OTG_HS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_IRQHandler
+ B OTG_HS_IRQHandler
+
+ PUBWEAK DCMI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_IRQHandler
+ B DCMI_IRQHandler
+
+ PUBWEAK CRYP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CRYP_IRQHandler
+ B CRYP_IRQHandler
+
+ PUBWEAK HASH_RNG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HASH_RNG_IRQHandler
+ B HASH_RNG_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ PUBWEAK UART7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART7_IRQHandler
+ B UART7_IRQHandler
+
+ PUBWEAK UART8_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART8_IRQHandler
+ B UART8_IRQHandler
+
+ PUBWEAK SPI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+ B SPI4_IRQHandler
+
+ PUBWEAK SPI5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI5_IRQHandler
+ B SPI5_IRQHandler
+
+ PUBWEAK SPI6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI6_IRQHandler
+ B SPI6_IRQHandler
+
+ PUBWEAK SAI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+ B SAI1_IRQHandler
+
+ PUBWEAK LTDC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_IRQHandler
+ B LTDC_IRQHandler
+
+ PUBWEAK LTDC_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_ER_IRQHandler
+ B LTDC_ER_IRQHandler
+
+ PUBWEAK DMA2D_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+ B DMA2D_IRQHandler
+
+ PUBWEAK SAI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+ B SAI2_IRQHandler
+
+ PUBWEAK QUADSPI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+ B QUADSPI_IRQHandler
+
+ PUBWEAK LPTIM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+ B LPTIM1_IRQHandler
+
+ PUBWEAK CEC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler
+ B CEC_IRQHandler
+
+ PUBWEAK I2C4_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+ B I2C4_EV_IRQHandler
+
+ PUBWEAK I2C4_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+ B I2C4_ER_IRQHandler
+
+ PUBWEAK SPDIF_RX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPDIF_RX_IRQHandler
+ B SPDIF_RX_IRQHandler
+
+ PUBWEAK OTG_FS_EP1_OUT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_EP1_OUT_IRQHandler
+ B OTG_FS_EP1_OUT_IRQHandler
+
+ PUBWEAK OTG_FS_EP1_IN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_EP1_IN_IRQHandler
+ B OTG_FS_EP1_IN_IRQHandler
+
+ PUBWEAK OTG_FS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_WKUP_IRQHandler
+ B OTG_FS_WKUP_IRQHandler
+
+ PUBWEAK OTG_FS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_IRQHandler
+ B OTG_FS_IRQHandler
+
+ PUBWEAK DMAMUX1_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+ B DMAMUX1_OVR_IRQHandler
+
+ PUBWEAK HRTIM1_Master_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_Master_IRQHandler
+ B HRTIM1_Master_IRQHandler
+
+ PUBWEAK HRTIM1_TIMA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMA_IRQHandler
+ B HRTIM1_TIMA_IRQHandler
+
+ PUBWEAK HRTIM1_TIMB_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMB_IRQHandler
+ B HRTIM1_TIMB_IRQHandler
+
+ PUBWEAK HRTIM1_TIMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMC_IRQHandler
+ B HRTIM1_TIMC_IRQHandler
+
+ PUBWEAK HRTIM1_TIMD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMD_IRQHandler
+ B HRTIM1_TIMD_IRQHandler
+
+ PUBWEAK HRTIM1_TIME_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIME_IRQHandler
+ B HRTIM1_TIME_IRQHandler
+
+ PUBWEAK HRTIM1_FLT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_FLT_IRQHandler
+ B HRTIM1_FLT_IRQHandler
+
+ PUBWEAK DFSDM1_FLT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT0_IRQHandler
+ B DFSDM1_FLT0_IRQHandler
+
+ PUBWEAK DFSDM1_FLT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+ B DFSDM1_FLT1_IRQHandler
+
+ PUBWEAK DFSDM1_FLT2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+ B DFSDM1_FLT2_IRQHandler
+
+ PUBWEAK DFSDM1_FLT3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+ B DFSDM1_FLT3_IRQHandler
+
+ PUBWEAK SAI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI3_IRQHandler
+ B SAI3_IRQHandler
+
+ PUBWEAK SWPMI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SWPMI1_IRQHandler
+ B SWPMI1_IRQHandler
+
+ PUBWEAK TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+ B TIM15_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK MDIOS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_WKUP_IRQHandler
+ B MDIOS_WKUP_IRQHandler
+
+ PUBWEAK MDIOS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_IRQHandler
+ B MDIOS_IRQHandler
+
+ PUBWEAK JPEG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+JPEG_IRQHandler
+ B JPEG_IRQHandler
+
+ PUBWEAK MDMA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDMA_IRQHandler
+ B MDMA_IRQHandler
+
+ PUBWEAK SDMMC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC2_IRQHandler
+ B SDMMC2_IRQHandler
+
+ PUBWEAK HSEM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM1_IRQHandler
+ B HSEM1_IRQHandler
+
+ PUBWEAK ADC3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC3_IRQHandler
+ B ADC3_IRQHandler
+
+ PUBWEAK DMAMUX2_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX2_OVR_IRQHandler
+ B DMAMUX2_OVR_IRQHandler
+
+ PUBWEAK BDMA_Channel0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel0_IRQHandler
+ B BDMA_Channel0_IRQHandler
+
+ PUBWEAK BDMA_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel1_IRQHandler
+ B BDMA_Channel1_IRQHandler
+
+ PUBWEAK BDMA_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel2_IRQHandler
+ B BDMA_Channel2_IRQHandler
+
+ PUBWEAK BDMA_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel3_IRQHandler
+ B BDMA_Channel3_IRQHandler
+
+ PUBWEAK BDMA_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel4_IRQHandler
+ B BDMA_Channel4_IRQHandler
+
+ PUBWEAK BDMA_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel5_IRQHandler
+ B BDMA_Channel5_IRQHandler
+
+ PUBWEAK BDMA_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel6_IRQHandler
+ B BDMA_Channel6_IRQHandler
+
+ PUBWEAK BDMA_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel7_IRQHandler
+ B BDMA_Channel7_IRQHandler
+
+ PUBWEAK COMP1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP1_IRQHandler
+ B COMP1_IRQHandler
+
+ PUBWEAK LPTIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+ B LPTIM2_IRQHandler
+
+ PUBWEAK LPTIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+ B LPTIM3_IRQHandler
+
+ PUBWEAK LPTIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM4_IRQHandler
+ B LPTIM4_IRQHandler
+
+ PUBWEAK LPTIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM5_IRQHandler
+ B LPTIM5_IRQHandler
+
+ PUBWEAK LPUART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+ B LPUART1_IRQHandler
+
+ PUBWEAK CRS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+ B CRS_IRQHandler
+
+ PUBWEAK ECC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ECC_IRQHandler
+ B ECC_IRQHandler
+
+ PUBWEAK SAI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI4_IRQHandler
+ B SAI4_IRQHandler
+
+ PUBWEAK WAKEUP_PIN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WAKEUP_PIN_IRQHandler
+ B WAKEUP_PIN_IRQHandler
+ END
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h755xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h755xx.s new file mode 100644 index 0000000..c8453b9 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h755xx.s @@ -0,0 +1,1007 @@ +;/********************************************************************************
+;* File Name : startup_stm32h755xx.s
+;* Author : MCD Application Team
+;* Description : STM32H755xx devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)
+ DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4
+ DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_IRQHandler ; DCMI
+ DCD CRYP_IRQHandler ; CRYP crypto
+ DCD HASH_RNG_IRQHandler ; Hash and Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD QUADSPI_IRQHandler ; QUADSPI
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
+ DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
+ DCD OTG_FS_IRQHandler ; USB OTG FS
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
+ DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
+ DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
+ DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
+ DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
+ DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
+ DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD SAI3_IRQHandler ; SAI3 global Interrupt
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD JPEG_IRQHandler ; JPEG global Interrupt
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD HSEM2_IRQHandler ; HSEM2 global Interrupt
+ DCD ADC3_IRQHandler ; ADC3 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP1_IRQHandler ; COMP1 global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
+ DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it)
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
+ DCD SAI4_IRQHandler ; SAI4 global interrupt
+ DCD 0 ; Reserved
+ DCD HOLD_CORE_IRQHandler ; Hold core interrupt
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_AVD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_AVD_IRQHandler
+ B PVD_AVD_IRQHandler
+
+ PUBWEAK TAMP_STAMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+ B TAMP_STAMP_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream0_IRQHandler
+ B DMA1_Stream0_IRQHandler
+
+ PUBWEAK DMA1_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream1_IRQHandler
+ B DMA1_Stream1_IRQHandler
+
+ PUBWEAK DMA1_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream2_IRQHandler
+ B DMA1_Stream2_IRQHandler
+
+ PUBWEAK DMA1_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream3_IRQHandler
+ B DMA1_Stream3_IRQHandler
+
+ PUBWEAK DMA1_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream4_IRQHandler
+ B DMA1_Stream4_IRQHandler
+
+ PUBWEAK DMA1_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream5_IRQHandler
+ B DMA1_Stream5_IRQHandler
+
+ PUBWEAK DMA1_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream6_IRQHandler
+ B DMA1_Stream6_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK FDCAN1_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+ B FDCAN1_IT0_IRQHandler
+
+ PUBWEAK FDCAN2_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT0_IRQHandler
+ B FDCAN2_IT0_IRQHandler
+
+ PUBWEAK FDCAN1_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+ B FDCAN1_IT1_IRQHandler
+
+ PUBWEAK FDCAN2_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT1_IRQHandler
+ B FDCAN2_IT1_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK TIM8_BRK_TIM12_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_TIM12_IRQHandler
+ B TIM8_BRK_TIM12_IRQHandler
+
+ PUBWEAK TIM8_UP_TIM13_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_TIM13_IRQHandler
+ B TIM8_UP_TIM13_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_TIM14_IRQHandler
+ B TIM8_TRG_COM_TIM14_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK DMA1_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream7_IRQHandler
+ B DMA1_Stream7_IRQHandler
+
+ PUBWEAK FMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+ B FMC_IRQHandler
+
+ PUBWEAK SDMMC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+ B SDMMC1_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream0_IRQHandler
+ B DMA2_Stream0_IRQHandler
+
+ PUBWEAK DMA2_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream1_IRQHandler
+ B DMA2_Stream1_IRQHandler
+
+ PUBWEAK DMA2_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream2_IRQHandler
+ B DMA2_Stream2_IRQHandler
+
+ PUBWEAK DMA2_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream3_IRQHandler
+ B DMA2_Stream3_IRQHandler
+
+ PUBWEAK DMA2_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream4_IRQHandler
+ B DMA2_Stream4_IRQHandler
+
+ PUBWEAK ETH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_IRQHandler
+ B ETH_IRQHandler
+
+ PUBWEAK ETH_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_WKUP_IRQHandler
+ B ETH_WKUP_IRQHandler
+
+ PUBWEAK FDCAN_CAL_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN_CAL_IRQHandler
+ B FDCAN_CAL_IRQHandler
+
+ PUBWEAK CM7_SEV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CM7_SEV_IRQHandler
+ B CM7_SEV_IRQHandler
+
+ PUBWEAK CM4_SEV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CM4_SEV_IRQHandler
+ B CM4_SEV_IRQHandler
+
+ PUBWEAK DMA2_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream5_IRQHandler
+ B DMA2_Stream5_IRQHandler
+
+ PUBWEAK DMA2_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream6_IRQHandler
+ B DMA2_Stream6_IRQHandler
+
+ PUBWEAK DMA2_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream7_IRQHandler
+ B DMA2_Stream7_IRQHandler
+
+ PUBWEAK USART6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler
+ B USART6_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_OUT_IRQHandler
+ B OTG_HS_EP1_OUT_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_IN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_IN_IRQHandler
+ B OTG_HS_EP1_IN_IRQHandler
+
+ PUBWEAK OTG_HS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_WKUP_IRQHandler
+ B OTG_HS_WKUP_IRQHandler
+
+ PUBWEAK OTG_HS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_IRQHandler
+ B OTG_HS_IRQHandler
+
+ PUBWEAK DCMI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_IRQHandler
+ B DCMI_IRQHandler
+
+ PUBWEAK CRYP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CRYP_IRQHandler
+ B CRYP_IRQHandler
+
+ PUBWEAK HASH_RNG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HASH_RNG_IRQHandler
+ B HASH_RNG_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ PUBWEAK UART7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART7_IRQHandler
+ B UART7_IRQHandler
+
+ PUBWEAK UART8_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART8_IRQHandler
+ B UART8_IRQHandler
+
+ PUBWEAK SPI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+ B SPI4_IRQHandler
+
+ PUBWEAK SPI5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI5_IRQHandler
+ B SPI5_IRQHandler
+
+ PUBWEAK SPI6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI6_IRQHandler
+ B SPI6_IRQHandler
+
+ PUBWEAK SAI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+ B SAI1_IRQHandler
+
+ PUBWEAK LTDC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_IRQHandler
+ B LTDC_IRQHandler
+
+ PUBWEAK LTDC_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_ER_IRQHandler
+ B LTDC_ER_IRQHandler
+
+ PUBWEAK DMA2D_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+ B DMA2D_IRQHandler
+
+ PUBWEAK SAI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+ B SAI2_IRQHandler
+
+ PUBWEAK QUADSPI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+ B QUADSPI_IRQHandler
+
+ PUBWEAK LPTIM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+ B LPTIM1_IRQHandler
+
+ PUBWEAK CEC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler
+ B CEC_IRQHandler
+
+ PUBWEAK I2C4_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+ B I2C4_EV_IRQHandler
+
+ PUBWEAK I2C4_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+ B I2C4_ER_IRQHandler
+
+ PUBWEAK SPDIF_RX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPDIF_RX_IRQHandler
+ B SPDIF_RX_IRQHandler
+
+ PUBWEAK OTG_FS_EP1_OUT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_EP1_OUT_IRQHandler
+ B OTG_FS_EP1_OUT_IRQHandler
+
+ PUBWEAK OTG_FS_EP1_IN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_EP1_IN_IRQHandler
+ B OTG_FS_EP1_IN_IRQHandler
+
+ PUBWEAK OTG_FS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_WKUP_IRQHandler
+ B OTG_FS_WKUP_IRQHandler
+
+ PUBWEAK OTG_FS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_IRQHandler
+ B OTG_FS_IRQHandler
+
+ PUBWEAK DMAMUX1_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+ B DMAMUX1_OVR_IRQHandler
+
+ PUBWEAK HRTIM1_Master_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_Master_IRQHandler
+ B HRTIM1_Master_IRQHandler
+
+ PUBWEAK HRTIM1_TIMA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMA_IRQHandler
+ B HRTIM1_TIMA_IRQHandler
+
+ PUBWEAK HRTIM1_TIMB_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMB_IRQHandler
+ B HRTIM1_TIMB_IRQHandler
+
+ PUBWEAK HRTIM1_TIMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMC_IRQHandler
+ B HRTIM1_TIMC_IRQHandler
+
+ PUBWEAK HRTIM1_TIMD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMD_IRQHandler
+ B HRTIM1_TIMD_IRQHandler
+
+ PUBWEAK HRTIM1_TIME_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIME_IRQHandler
+ B HRTIM1_TIME_IRQHandler
+
+ PUBWEAK HRTIM1_FLT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_FLT_IRQHandler
+ B HRTIM1_FLT_IRQHandler
+
+ PUBWEAK DFSDM1_FLT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT0_IRQHandler
+ B DFSDM1_FLT0_IRQHandler
+
+ PUBWEAK DFSDM1_FLT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+ B DFSDM1_FLT1_IRQHandler
+
+ PUBWEAK DFSDM1_FLT2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+ B DFSDM1_FLT2_IRQHandler
+
+ PUBWEAK DFSDM1_FLT3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+ B DFSDM1_FLT3_IRQHandler
+
+ PUBWEAK SAI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI3_IRQHandler
+ B SAI3_IRQHandler
+
+ PUBWEAK SWPMI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SWPMI1_IRQHandler
+ B SWPMI1_IRQHandler
+
+ PUBWEAK TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+ B TIM15_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK MDIOS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_WKUP_IRQHandler
+ B MDIOS_WKUP_IRQHandler
+
+ PUBWEAK MDIOS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_IRQHandler
+ B MDIOS_IRQHandler
+
+ PUBWEAK JPEG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+JPEG_IRQHandler
+ B JPEG_IRQHandler
+
+ PUBWEAK MDMA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDMA_IRQHandler
+ B MDMA_IRQHandler
+
+ PUBWEAK SDMMC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC2_IRQHandler
+ B SDMMC2_IRQHandler
+
+ PUBWEAK HSEM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM1_IRQHandler
+ B HSEM1_IRQHandler
+
+ PUBWEAK HSEM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM2_IRQHandler
+ B HSEM2_IRQHandler
+
+ PUBWEAK ADC3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC3_IRQHandler
+ B ADC3_IRQHandler
+
+ PUBWEAK DMAMUX2_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX2_OVR_IRQHandler
+ B DMAMUX2_OVR_IRQHandler
+
+ PUBWEAK BDMA_Channel0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel0_IRQHandler
+ B BDMA_Channel0_IRQHandler
+
+ PUBWEAK BDMA_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel1_IRQHandler
+ B BDMA_Channel1_IRQHandler
+
+ PUBWEAK BDMA_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel2_IRQHandler
+ B BDMA_Channel2_IRQHandler
+
+ PUBWEAK BDMA_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel3_IRQHandler
+ B BDMA_Channel3_IRQHandler
+
+ PUBWEAK BDMA_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel4_IRQHandler
+ B BDMA_Channel4_IRQHandler
+
+ PUBWEAK BDMA_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel5_IRQHandler
+ B BDMA_Channel5_IRQHandler
+
+ PUBWEAK BDMA_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel6_IRQHandler
+ B BDMA_Channel6_IRQHandler
+
+ PUBWEAK BDMA_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel7_IRQHandler
+ B BDMA_Channel7_IRQHandler
+
+ PUBWEAK COMP1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP1_IRQHandler
+ B COMP1_IRQHandler
+
+ PUBWEAK LPTIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+ B LPTIM2_IRQHandler
+
+ PUBWEAK LPTIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+ B LPTIM3_IRQHandler
+
+ PUBWEAK LPTIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM4_IRQHandler
+ B LPTIM4_IRQHandler
+
+ PUBWEAK LPTIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM5_IRQHandler
+ B LPTIM5_IRQHandler
+
+ PUBWEAK LPUART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+ B LPUART1_IRQHandler
+
+ PUBWEAK WWDG_RST_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_RST_IRQHandler
+ B WWDG_RST_IRQHandler
+
+ PUBWEAK CRS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+ B CRS_IRQHandler
+
+ PUBWEAK ECC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ECC_IRQHandler
+ B ECC_IRQHandler
+
+ PUBWEAK SAI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI4_IRQHandler
+ B SAI4_IRQHandler
+
+ PUBWEAK HOLD_CORE_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HOLD_CORE_IRQHandler
+ B HOLD_CORE_IRQHandler
+
+ PUBWEAK WAKEUP_PIN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WAKEUP_PIN_IRQHandler
+ B WAKEUP_PIN_IRQHandler
+ END
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h757xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h757xx.s new file mode 100644 index 0000000..0cdb441 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h757xx.s @@ -0,0 +1,1012 @@ +;/********************************************************************************
+;* File Name : startup_stm32h757xx.s
+;* Author : MCD Application Team
+;* Description : STM32H757xx devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)
+ DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD 0 ; Reserved
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4
+ DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_IRQHandler ; DCMI
+ DCD CRYP_IRQHandler ; CRYP crypto
+ DCD HASH_RNG_IRQHandler ; Hash and Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD QUADSPI_IRQHandler ; QUADSPI
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out
+ DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI
+ DCD OTG_FS_IRQHandler ; USB OTG FS
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts
+ DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt
+ DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt
+ DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt
+ DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt
+ DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt
+ DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD SAI3_IRQHandler ; SAI3 global Interrupt
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD JPEG_IRQHandler ; JPEG global Interrupt
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD DSI_IRQHandler ; DSI global Interrupt
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD HSEM2_IRQHandler ; HSEM2 global Interrupt
+ DCD ADC3_IRQHandler ; ADC3 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP1_IRQHandler ; COMP1 global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt
+ DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it)
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt
+ DCD SAI4_IRQHandler ; SAI4 global interrupt
+ DCD 0 ; Reserved
+ DCD HOLD_CORE_IRQHandler ; Hold core interrupt
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_AVD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_AVD_IRQHandler
+ B PVD_AVD_IRQHandler
+
+ PUBWEAK TAMP_STAMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TAMP_STAMP_IRQHandler
+ B TAMP_STAMP_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream0_IRQHandler
+ B DMA1_Stream0_IRQHandler
+
+ PUBWEAK DMA1_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream1_IRQHandler
+ B DMA1_Stream1_IRQHandler
+
+ PUBWEAK DMA1_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream2_IRQHandler
+ B DMA1_Stream2_IRQHandler
+
+ PUBWEAK DMA1_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream3_IRQHandler
+ B DMA1_Stream3_IRQHandler
+
+ PUBWEAK DMA1_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream4_IRQHandler
+ B DMA1_Stream4_IRQHandler
+
+ PUBWEAK DMA1_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream5_IRQHandler
+ B DMA1_Stream5_IRQHandler
+
+ PUBWEAK DMA1_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream6_IRQHandler
+ B DMA1_Stream6_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK FDCAN1_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+ B FDCAN1_IT0_IRQHandler
+
+ PUBWEAK FDCAN2_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT0_IRQHandler
+ B FDCAN2_IT0_IRQHandler
+
+ PUBWEAK FDCAN1_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+ B FDCAN1_IT1_IRQHandler
+
+ PUBWEAK FDCAN2_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT1_IRQHandler
+ B FDCAN2_IT1_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK TIM8_BRK_TIM12_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_TIM12_IRQHandler
+ B TIM8_BRK_TIM12_IRQHandler
+
+ PUBWEAK TIM8_UP_TIM13_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_TIM13_IRQHandler
+ B TIM8_UP_TIM13_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_TIM14_IRQHandler
+ B TIM8_TRG_COM_TIM14_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK DMA1_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream7_IRQHandler
+ B DMA1_Stream7_IRQHandler
+
+ PUBWEAK FMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+ B FMC_IRQHandler
+
+ PUBWEAK SDMMC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+ B SDMMC1_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream0_IRQHandler
+ B DMA2_Stream0_IRQHandler
+
+ PUBWEAK DMA2_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream1_IRQHandler
+ B DMA2_Stream1_IRQHandler
+
+ PUBWEAK DMA2_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream2_IRQHandler
+ B DMA2_Stream2_IRQHandler
+
+ PUBWEAK DMA2_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream3_IRQHandler
+ B DMA2_Stream3_IRQHandler
+
+ PUBWEAK DMA2_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream4_IRQHandler
+ B DMA2_Stream4_IRQHandler
+
+ PUBWEAK ETH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_IRQHandler
+ B ETH_IRQHandler
+
+ PUBWEAK ETH_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ETH_WKUP_IRQHandler
+ B ETH_WKUP_IRQHandler
+
+ PUBWEAK FDCAN_CAL_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN_CAL_IRQHandler
+ B FDCAN_CAL_IRQHandler
+
+ PUBWEAK CM7_SEV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CM7_SEV_IRQHandler
+ B CM7_SEV_IRQHandler
+
+ PUBWEAK CM4_SEV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CM4_SEV_IRQHandler
+ B CM4_SEV_IRQHandler
+
+ PUBWEAK DMA2_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream5_IRQHandler
+ B DMA2_Stream5_IRQHandler
+
+ PUBWEAK DMA2_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream6_IRQHandler
+ B DMA2_Stream6_IRQHandler
+
+ PUBWEAK DMA2_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream7_IRQHandler
+ B DMA2_Stream7_IRQHandler
+
+ PUBWEAK USART6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler
+ B USART6_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_OUT_IRQHandler
+ B OTG_HS_EP1_OUT_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_IN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_IN_IRQHandler
+ B OTG_HS_EP1_IN_IRQHandler
+
+ PUBWEAK OTG_HS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_WKUP_IRQHandler
+ B OTG_HS_WKUP_IRQHandler
+
+ PUBWEAK OTG_HS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_IRQHandler
+ B OTG_HS_IRQHandler
+
+ PUBWEAK DCMI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_IRQHandler
+ B DCMI_IRQHandler
+
+ PUBWEAK CRYP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CRYP_IRQHandler
+ B CRYP_IRQHandler
+
+ PUBWEAK HASH_RNG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HASH_RNG_IRQHandler
+ B HASH_RNG_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ PUBWEAK UART7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART7_IRQHandler
+ B UART7_IRQHandler
+
+ PUBWEAK UART8_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART8_IRQHandler
+ B UART8_IRQHandler
+
+ PUBWEAK SPI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+ B SPI4_IRQHandler
+
+ PUBWEAK SPI5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI5_IRQHandler
+ B SPI5_IRQHandler
+
+ PUBWEAK SPI6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI6_IRQHandler
+ B SPI6_IRQHandler
+
+ PUBWEAK SAI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+ B SAI1_IRQHandler
+
+ PUBWEAK LTDC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_IRQHandler
+ B LTDC_IRQHandler
+
+ PUBWEAK LTDC_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_ER_IRQHandler
+ B LTDC_ER_IRQHandler
+
+ PUBWEAK DMA2D_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+ B DMA2D_IRQHandler
+
+ PUBWEAK SAI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+ B SAI2_IRQHandler
+
+ PUBWEAK QUADSPI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+QUADSPI_IRQHandler
+ B QUADSPI_IRQHandler
+
+ PUBWEAK LPTIM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+ B LPTIM1_IRQHandler
+
+ PUBWEAK CEC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler
+ B CEC_IRQHandler
+
+ PUBWEAK I2C4_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+ B I2C4_EV_IRQHandler
+
+ PUBWEAK I2C4_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+ B I2C4_ER_IRQHandler
+
+ PUBWEAK SPDIF_RX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPDIF_RX_IRQHandler
+ B SPDIF_RX_IRQHandler
+
+ PUBWEAK OTG_FS_EP1_OUT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_EP1_OUT_IRQHandler
+ B OTG_FS_EP1_OUT_IRQHandler
+
+ PUBWEAK OTG_FS_EP1_IN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_EP1_IN_IRQHandler
+ B OTG_FS_EP1_IN_IRQHandler
+
+ PUBWEAK OTG_FS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_WKUP_IRQHandler
+ B OTG_FS_WKUP_IRQHandler
+
+ PUBWEAK OTG_FS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_FS_IRQHandler
+ B OTG_FS_IRQHandler
+
+ PUBWEAK DMAMUX1_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX1_OVR_IRQHandler
+ B DMAMUX1_OVR_IRQHandler
+
+ PUBWEAK HRTIM1_Master_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_Master_IRQHandler
+ B HRTIM1_Master_IRQHandler
+
+ PUBWEAK HRTIM1_TIMA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMA_IRQHandler
+ B HRTIM1_TIMA_IRQHandler
+
+ PUBWEAK HRTIM1_TIMB_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMB_IRQHandler
+ B HRTIM1_TIMB_IRQHandler
+
+ PUBWEAK HRTIM1_TIMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMC_IRQHandler
+ B HRTIM1_TIMC_IRQHandler
+
+ PUBWEAK HRTIM1_TIMD_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIMD_IRQHandler
+ B HRTIM1_TIMD_IRQHandler
+
+ PUBWEAK HRTIM1_TIME_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_TIME_IRQHandler
+ B HRTIM1_TIME_IRQHandler
+
+ PUBWEAK HRTIM1_FLT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HRTIM1_FLT_IRQHandler
+ B HRTIM1_FLT_IRQHandler
+
+ PUBWEAK DFSDM1_FLT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT0_IRQHandler
+ B DFSDM1_FLT0_IRQHandler
+
+ PUBWEAK DFSDM1_FLT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+ B DFSDM1_FLT1_IRQHandler
+
+ PUBWEAK DFSDM1_FLT2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+ B DFSDM1_FLT2_IRQHandler
+
+ PUBWEAK DFSDM1_FLT3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+ B DFSDM1_FLT3_IRQHandler
+
+ PUBWEAK SAI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI3_IRQHandler
+ B SAI3_IRQHandler
+
+ PUBWEAK SWPMI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SWPMI1_IRQHandler
+ B SWPMI1_IRQHandler
+
+ PUBWEAK TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+ B TIM15_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK MDIOS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_WKUP_IRQHandler
+ B MDIOS_WKUP_IRQHandler
+
+ PUBWEAK MDIOS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_IRQHandler
+ B MDIOS_IRQHandler
+
+ PUBWEAK JPEG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+JPEG_IRQHandler
+ B JPEG_IRQHandler
+
+ PUBWEAK MDMA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDMA_IRQHandler
+ B MDMA_IRQHandler
+
+ PUBWEAK DSI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DSI_IRQHandler
+ B DSI_IRQHandler
+
+ PUBWEAK SDMMC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC2_IRQHandler
+ B SDMMC2_IRQHandler
+
+ PUBWEAK HSEM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM1_IRQHandler
+ B HSEM1_IRQHandler
+
+ PUBWEAK HSEM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM2_IRQHandler
+ B HSEM2_IRQHandler
+
+ PUBWEAK ADC3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC3_IRQHandler
+ B ADC3_IRQHandler
+
+ PUBWEAK DMAMUX2_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX2_OVR_IRQHandler
+ B DMAMUX2_OVR_IRQHandler
+
+ PUBWEAK BDMA_Channel0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel0_IRQHandler
+ B BDMA_Channel0_IRQHandler
+
+ PUBWEAK BDMA_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel1_IRQHandler
+ B BDMA_Channel1_IRQHandler
+
+ PUBWEAK BDMA_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel2_IRQHandler
+ B BDMA_Channel2_IRQHandler
+
+ PUBWEAK BDMA_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel3_IRQHandler
+ B BDMA_Channel3_IRQHandler
+
+ PUBWEAK BDMA_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel4_IRQHandler
+ B BDMA_Channel4_IRQHandler
+
+ PUBWEAK BDMA_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel5_IRQHandler
+ B BDMA_Channel5_IRQHandler
+
+ PUBWEAK BDMA_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel6_IRQHandler
+ B BDMA_Channel6_IRQHandler
+
+ PUBWEAK BDMA_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA_Channel7_IRQHandler
+ B BDMA_Channel7_IRQHandler
+
+ PUBWEAK COMP1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP1_IRQHandler
+ B COMP1_IRQHandler
+
+ PUBWEAK LPTIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+ B LPTIM2_IRQHandler
+
+ PUBWEAK LPTIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+ B LPTIM3_IRQHandler
+
+ PUBWEAK LPTIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM4_IRQHandler
+ B LPTIM4_IRQHandler
+
+ PUBWEAK LPTIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM5_IRQHandler
+ B LPTIM5_IRQHandler
+
+ PUBWEAK LPUART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+ B LPUART1_IRQHandler
+
+ PUBWEAK WWDG_RST_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_RST_IRQHandler
+ B WWDG_RST_IRQHandler
+
+ PUBWEAK CRS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+ B CRS_IRQHandler
+
+ PUBWEAK ECC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ECC_IRQHandler
+ B ECC_IRQHandler
+
+ PUBWEAK SAI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI4_IRQHandler
+ B SAI4_IRQHandler
+
+ PUBWEAK HOLD_CORE_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HOLD_CORE_IRQHandler
+ B HOLD_CORE_IRQHandler
+
+ PUBWEAK WAKEUP_PIN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WAKEUP_PIN_IRQHandler
+ B WAKEUP_PIN_IRQHandler
+ END
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h7a3xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h7a3xx.s new file mode 100644 index 0000000..7affb6f --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h7a3xx.s @@ -0,0 +1,954 @@ +;/******************************************************************************
+;* @file startup_stm32h7a3xx.s
+;* @author MCD Application Team
+;* @brief STM32H7B3xx devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog Interrupt
+ DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection
+ DCD RTC_TAMP_STAMP_CSS_LSE_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD DFSDM2_IRQHandler ; DFSDM2 Interrupt
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD DFSDM1_FLT4_IRQHandler ; DFSDM Filter4 Interrupt
+ DCD DFSDM1_FLT5_IRQHandler ; DFSDM Filter5 Interrupt
+ DCD DFSDM1_FLT6_IRQHandler ; DFSDM Filter6 Interrupt
+ DCD DFSDM1_FLT7_IRQHandler ; DFSDM Filter7 Interrupt
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_PSSI_IRQHandler ; DCMI, PSSI
+ DCD 0 ; Reserved
+ DCD RNG_IRQHandler ; Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD OCTOSPI1_IRQHandler ; OCTOSPI1
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD 0 ; Reserved
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD JPEG_IRQHandler ; JPEG global Interrupt
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD 0 ; Reserved
+ DCD DAC2_IRQHandler ; DAC2 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA2_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA2_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA2_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA2_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA2_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA2_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA2_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA2_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP_IRQHandler ; COMP global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD UART9_IRQHandler ; UART9 global interrupt
+ DCD USART10_IRQHandler ; USART10 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD 0 ; Reserved
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC
+ DCD 0 ; Reserved
+ DCD DTS_IRQHandler ; DTS
+ DCD 0 ; Reserved
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+ DCD OCTOSPI2_IRQHandler ; OCTOSPI2
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD GFXMMU_IRQHandler ; GFXMMU
+ DCD BDMA1_IRQHandler ; BDMA1
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_PVM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+ B PVD_PVM_IRQHandler
+
+ PUBWEAK RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+ B RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream0_IRQHandler
+ B DMA1_Stream0_IRQHandler
+
+ PUBWEAK DMA1_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream1_IRQHandler
+ B DMA1_Stream1_IRQHandler
+
+ PUBWEAK DMA1_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream2_IRQHandler
+ B DMA1_Stream2_IRQHandler
+
+ PUBWEAK DMA1_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream3_IRQHandler
+ B DMA1_Stream3_IRQHandler
+
+ PUBWEAK DMA1_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream4_IRQHandler
+ B DMA1_Stream4_IRQHandler
+
+ PUBWEAK DMA1_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream5_IRQHandler
+ B DMA1_Stream5_IRQHandler
+
+ PUBWEAK DMA1_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream6_IRQHandler
+ B DMA1_Stream6_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK FDCAN1_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+ B FDCAN1_IT0_IRQHandler
+
+ PUBWEAK FDCAN2_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT0_IRQHandler
+ B FDCAN2_IT0_IRQHandler
+
+ PUBWEAK FDCAN1_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+ B FDCAN1_IT1_IRQHandler
+
+ PUBWEAK FDCAN2_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT1_IRQHandler
+ B FDCAN2_IT1_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK DFSDM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM2_IRQHandler
+ B DFSDM2_IRQHandler
+
+ PUBWEAK TIM8_BRK_TIM12_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_TIM12_IRQHandler
+ B TIM8_BRK_TIM12_IRQHandler
+
+ PUBWEAK TIM8_UP_TIM13_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_TIM13_IRQHandler
+ B TIM8_UP_TIM13_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_TIM14_IRQHandler
+ B TIM8_TRG_COM_TIM14_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK DMA1_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream7_IRQHandler
+ B DMA1_Stream7_IRQHandler
+
+ PUBWEAK FMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+ B FMC_IRQHandler
+
+ PUBWEAK SDMMC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+ B SDMMC1_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream0_IRQHandler
+ B DMA2_Stream0_IRQHandler
+
+ PUBWEAK DMA2_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream1_IRQHandler
+ B DMA2_Stream1_IRQHandler
+
+ PUBWEAK DMA2_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream2_IRQHandler
+ B DMA2_Stream2_IRQHandler
+
+ PUBWEAK DMA2_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream3_IRQHandler
+ B DMA2_Stream3_IRQHandler
+
+ PUBWEAK DMA2_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream4_IRQHandler
+ B DMA2_Stream4_IRQHandler
+
+ PUBWEAK FDCAN_CAL_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN_CAL_IRQHandler
+ B FDCAN_CAL_IRQHandler
+
+ PUBWEAK DFSDM1_FLT4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT4_IRQHandler
+ B DFSDM1_FLT4_IRQHandler
+
+ PUBWEAK DFSDM1_FLT5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT5_IRQHandler
+ B DFSDM1_FLT5_IRQHandler
+
+ PUBWEAK DFSDM1_FLT6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT6_IRQHandler
+ B DFSDM1_FLT6_IRQHandler
+
+ PUBWEAK DFSDM1_FLT7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT7_IRQHandler
+ B DFSDM1_FLT7_IRQHandler
+
+ PUBWEAK DMA2_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream5_IRQHandler
+ B DMA2_Stream5_IRQHandler
+
+ PUBWEAK DMA2_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream6_IRQHandler
+ B DMA2_Stream6_IRQHandler
+
+ PUBWEAK DMA2_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream7_IRQHandler
+ B DMA2_Stream7_IRQHandler
+
+ PUBWEAK USART6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler
+ B USART6_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_OUT_IRQHandler
+ B OTG_HS_EP1_OUT_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_IN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_IN_IRQHandler
+ B OTG_HS_EP1_IN_IRQHandler
+
+ PUBWEAK OTG_HS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_WKUP_IRQHandler
+ B OTG_HS_WKUP_IRQHandler
+
+ PUBWEAK OTG_HS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_IRQHandler
+ B OTG_HS_IRQHandler
+
+ PUBWEAK DCMI_PSSI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_PSSI_IRQHandler
+ B DCMI_PSSI_IRQHandler
+
+ PUBWEAK RNG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+ B RNG_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ PUBWEAK UART7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART7_IRQHandler
+ B UART7_IRQHandler
+
+ PUBWEAK UART8_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART8_IRQHandler
+ B UART8_IRQHandler
+
+ PUBWEAK SPI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+ B SPI4_IRQHandler
+
+ PUBWEAK SPI5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI5_IRQHandler
+ B SPI5_IRQHandler
+
+ PUBWEAK SPI6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI6_IRQHandler
+ B SPI6_IRQHandler
+
+ PUBWEAK SAI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+ B SAI1_IRQHandler
+
+ PUBWEAK LTDC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_IRQHandler
+ B LTDC_IRQHandler
+
+ PUBWEAK LTDC_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_ER_IRQHandler
+ B LTDC_ER_IRQHandler
+
+ PUBWEAK DMA2D_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+ B DMA2D_IRQHandler
+
+ PUBWEAK SAI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+ B SAI2_IRQHandler
+
+ PUBWEAK OCTOSPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI1_IRQHandler
+ B OCTOSPI1_IRQHandler
+
+ PUBWEAK LPTIM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+ B LPTIM1_IRQHandler
+
+ PUBWEAK CEC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler
+ B CEC_IRQHandler
+
+ PUBWEAK I2C4_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+ B I2C4_EV_IRQHandler
+
+ PUBWEAK I2C4_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+ B I2C4_ER_IRQHandler
+
+ PUBWEAK SPDIF_RX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPDIF_RX_IRQHandler
+ B SPDIF_RX_IRQHandler
+
+ PUBWEAK DMAMUX1_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+
+DMAMUX1_OVR_IRQHandler
+ B DMAMUX1_OVR_IRQHandler
+
+ PUBWEAK DFSDM1_FLT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+
+DFSDM1_FLT0_IRQHandler
+ B DFSDM1_FLT0_IRQHandler
+
+ PUBWEAK DFSDM1_FLT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+ B DFSDM1_FLT1_IRQHandler
+
+ PUBWEAK DFSDM1_FLT2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+ B DFSDM1_FLT2_IRQHandler
+
+ PUBWEAK DFSDM1_FLT3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+ B DFSDM1_FLT3_IRQHandler
+
+ PUBWEAK SWPMI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SWPMI1_IRQHandler
+ B SWPMI1_IRQHandler
+
+ PUBWEAK TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+ B TIM15_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK MDIOS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_WKUP_IRQHandler
+ B MDIOS_WKUP_IRQHandler
+
+ PUBWEAK MDIOS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_IRQHandler
+ B MDIOS_IRQHandler
+
+ PUBWEAK JPEG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+JPEG_IRQHandler
+ B JPEG_IRQHandler
+
+ PUBWEAK MDMA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDMA_IRQHandler
+ B MDMA_IRQHandler
+
+ PUBWEAK SDMMC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC2_IRQHandler
+ B SDMMC2_IRQHandler
+
+ PUBWEAK HSEM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM1_IRQHandler
+ B HSEM1_IRQHandler
+
+ PUBWEAK DAC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DAC2_IRQHandler
+ B DAC2_IRQHandler
+
+ PUBWEAK DMAMUX2_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX2_OVR_IRQHandler
+ B DMAMUX2_OVR_IRQHandler
+
+ PUBWEAK BDMA2_Channel0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel0_IRQHandler
+ B BDMA2_Channel0_IRQHandler
+
+ PUBWEAK BDMA2_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel1_IRQHandler
+ B BDMA2_Channel1_IRQHandler
+
+ PUBWEAK BDMA2_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel2_IRQHandler
+ B BDMA2_Channel2_IRQHandler
+
+ PUBWEAK BDMA2_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel3_IRQHandler
+ B BDMA2_Channel3_IRQHandler
+
+ PUBWEAK BDMA2_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel4_IRQHandler
+ B BDMA2_Channel4_IRQHandler
+
+ PUBWEAK BDMA2_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel5_IRQHandler
+ B BDMA2_Channel5_IRQHandler
+
+ PUBWEAK BDMA2_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel6_IRQHandler
+ B BDMA2_Channel6_IRQHandler
+
+ PUBWEAK BDMA2_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel7_IRQHandler
+ B BDMA2_Channel7_IRQHandler
+
+ PUBWEAK COMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+ B COMP_IRQHandler
+
+ PUBWEAK LPTIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+ B LPTIM2_IRQHandler
+
+ PUBWEAK LPTIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+ B LPTIM3_IRQHandler
+
+ PUBWEAK UART9_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART9_IRQHandler
+ B UART9_IRQHandler
+
+ PUBWEAK USART10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART10_IRQHandler
+ B USART10_IRQHandler
+
+ PUBWEAK LPUART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+ B LPUART1_IRQHandler
+
+ PUBWEAK CRS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+ B CRS_IRQHandler
+
+ PUBWEAK ECC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ECC_IRQHandler
+ B ECC_IRQHandler
+
+ PUBWEAK DTS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DTS_IRQHandler
+ B DTS_IRQHandler
+
+ PUBWEAK WAKEUP_PIN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WAKEUP_PIN_IRQHandler
+ B WAKEUP_PIN_IRQHandler
+
+ PUBWEAK OCTOSPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI2_IRQHandler
+ B OCTOSPI2_IRQHandler
+
+ PUBWEAK GFXMMU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+GFXMMU_IRQHandler
+ B GFXMMU_IRQHandler
+
+ PUBWEAK BDMA1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA1_IRQHandler
+ B BDMA1_IRQHandler
+ END
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h7a3xxq.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h7a3xxq.s new file mode 100644 index 0000000..20b25f6 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h7a3xxq.s @@ -0,0 +1,954 @@ +;/******************************************************************************
+;* @file startup_stm32h7a3xxq.s
+;* @author MCD Application Team
+;* @brief STM32H7B3xx devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog Interrupt
+ DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection
+ DCD RTC_TAMP_STAMP_CSS_LSE_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD DFSDM2_IRQHandler ; DFSDM2 Interrupt
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD DFSDM1_FLT4_IRQHandler ; DFSDM Filter4 Interrupt
+ DCD DFSDM1_FLT5_IRQHandler ; DFSDM Filter5 Interrupt
+ DCD DFSDM1_FLT6_IRQHandler ; DFSDM Filter6 Interrupt
+ DCD DFSDM1_FLT7_IRQHandler ; DFSDM Filter7 Interrupt
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_PSSI_IRQHandler ; DCMI, PSSI
+ DCD 0 ; Reserved
+ DCD RNG_IRQHandler ; Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD OCTOSPI1_IRQHandler ; OCTOSPI1
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD 0 ; Reserved
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD JPEG_IRQHandler ; JPEG global Interrupt
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD 0 ; Reserved
+ DCD DAC2_IRQHandler ; DAC2 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA2_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA2_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA2_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA2_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA2_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA2_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA2_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA2_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP_IRQHandler ; COMP global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD UART9_IRQHandler ; UART9 global interrupt
+ DCD USART10_IRQHandler ; USART10 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD 0 ; Reserved
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC
+ DCD 0 ; Reserved
+ DCD DTS_IRQHandler ; DTS
+ DCD 0 ; Reserved
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+ DCD OCTOSPI2_IRQHandler ; OCTOSPI2
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD GFXMMU_IRQHandler ; GFXMMU
+ DCD BDMA1_IRQHandler ; BDMA1
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_PVM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+ B PVD_PVM_IRQHandler
+
+ PUBWEAK RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+ B RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream0_IRQHandler
+ B DMA1_Stream0_IRQHandler
+
+ PUBWEAK DMA1_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream1_IRQHandler
+ B DMA1_Stream1_IRQHandler
+
+ PUBWEAK DMA1_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream2_IRQHandler
+ B DMA1_Stream2_IRQHandler
+
+ PUBWEAK DMA1_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream3_IRQHandler
+ B DMA1_Stream3_IRQHandler
+
+ PUBWEAK DMA1_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream4_IRQHandler
+ B DMA1_Stream4_IRQHandler
+
+ PUBWEAK DMA1_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream5_IRQHandler
+ B DMA1_Stream5_IRQHandler
+
+ PUBWEAK DMA1_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream6_IRQHandler
+ B DMA1_Stream6_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK FDCAN1_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+ B FDCAN1_IT0_IRQHandler
+
+ PUBWEAK FDCAN2_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT0_IRQHandler
+ B FDCAN2_IT0_IRQHandler
+
+ PUBWEAK FDCAN1_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+ B FDCAN1_IT1_IRQHandler
+
+ PUBWEAK FDCAN2_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT1_IRQHandler
+ B FDCAN2_IT1_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK DFSDM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM2_IRQHandler
+ B DFSDM2_IRQHandler
+
+ PUBWEAK TIM8_BRK_TIM12_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_TIM12_IRQHandler
+ B TIM8_BRK_TIM12_IRQHandler
+
+ PUBWEAK TIM8_UP_TIM13_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_TIM13_IRQHandler
+ B TIM8_UP_TIM13_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_TIM14_IRQHandler
+ B TIM8_TRG_COM_TIM14_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK DMA1_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream7_IRQHandler
+ B DMA1_Stream7_IRQHandler
+
+ PUBWEAK FMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+ B FMC_IRQHandler
+
+ PUBWEAK SDMMC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+ B SDMMC1_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream0_IRQHandler
+ B DMA2_Stream0_IRQHandler
+
+ PUBWEAK DMA2_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream1_IRQHandler
+ B DMA2_Stream1_IRQHandler
+
+ PUBWEAK DMA2_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream2_IRQHandler
+ B DMA2_Stream2_IRQHandler
+
+ PUBWEAK DMA2_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream3_IRQHandler
+ B DMA2_Stream3_IRQHandler
+
+ PUBWEAK DMA2_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream4_IRQHandler
+ B DMA2_Stream4_IRQHandler
+
+ PUBWEAK FDCAN_CAL_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN_CAL_IRQHandler
+ B FDCAN_CAL_IRQHandler
+
+ PUBWEAK DFSDM1_FLT4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT4_IRQHandler
+ B DFSDM1_FLT4_IRQHandler
+
+ PUBWEAK DFSDM1_FLT5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT5_IRQHandler
+ B DFSDM1_FLT5_IRQHandler
+
+ PUBWEAK DFSDM1_FLT6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT6_IRQHandler
+ B DFSDM1_FLT6_IRQHandler
+
+ PUBWEAK DFSDM1_FLT7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT7_IRQHandler
+ B DFSDM1_FLT7_IRQHandler
+
+ PUBWEAK DMA2_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream5_IRQHandler
+ B DMA2_Stream5_IRQHandler
+
+ PUBWEAK DMA2_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream6_IRQHandler
+ B DMA2_Stream6_IRQHandler
+
+ PUBWEAK DMA2_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream7_IRQHandler
+ B DMA2_Stream7_IRQHandler
+
+ PUBWEAK USART6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler
+ B USART6_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_OUT_IRQHandler
+ B OTG_HS_EP1_OUT_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_IN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_IN_IRQHandler
+ B OTG_HS_EP1_IN_IRQHandler
+
+ PUBWEAK OTG_HS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_WKUP_IRQHandler
+ B OTG_HS_WKUP_IRQHandler
+
+ PUBWEAK OTG_HS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_IRQHandler
+ B OTG_HS_IRQHandler
+
+ PUBWEAK DCMI_PSSI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_PSSI_IRQHandler
+ B DCMI_PSSI_IRQHandler
+
+ PUBWEAK RNG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+ B RNG_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ PUBWEAK UART7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART7_IRQHandler
+ B UART7_IRQHandler
+
+ PUBWEAK UART8_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART8_IRQHandler
+ B UART8_IRQHandler
+
+ PUBWEAK SPI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+ B SPI4_IRQHandler
+
+ PUBWEAK SPI5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI5_IRQHandler
+ B SPI5_IRQHandler
+
+ PUBWEAK SPI6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI6_IRQHandler
+ B SPI6_IRQHandler
+
+ PUBWEAK SAI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+ B SAI1_IRQHandler
+
+ PUBWEAK LTDC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_IRQHandler
+ B LTDC_IRQHandler
+
+ PUBWEAK LTDC_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_ER_IRQHandler
+ B LTDC_ER_IRQHandler
+
+ PUBWEAK DMA2D_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+ B DMA2D_IRQHandler
+
+ PUBWEAK SAI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+ B SAI2_IRQHandler
+
+ PUBWEAK OCTOSPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI1_IRQHandler
+ B OCTOSPI1_IRQHandler
+
+ PUBWEAK LPTIM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+ B LPTIM1_IRQHandler
+
+ PUBWEAK CEC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler
+ B CEC_IRQHandler
+
+ PUBWEAK I2C4_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+ B I2C4_EV_IRQHandler
+
+ PUBWEAK I2C4_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+ B I2C4_ER_IRQHandler
+
+ PUBWEAK SPDIF_RX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPDIF_RX_IRQHandler
+ B SPDIF_RX_IRQHandler
+
+ PUBWEAK DMAMUX1_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+
+DMAMUX1_OVR_IRQHandler
+ B DMAMUX1_OVR_IRQHandler
+
+ PUBWEAK DFSDM1_FLT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+
+DFSDM1_FLT0_IRQHandler
+ B DFSDM1_FLT0_IRQHandler
+
+ PUBWEAK DFSDM1_FLT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+ B DFSDM1_FLT1_IRQHandler
+
+ PUBWEAK DFSDM1_FLT2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+ B DFSDM1_FLT2_IRQHandler
+
+ PUBWEAK DFSDM1_FLT3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+ B DFSDM1_FLT3_IRQHandler
+
+ PUBWEAK SWPMI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SWPMI1_IRQHandler
+ B SWPMI1_IRQHandler
+
+ PUBWEAK TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+ B TIM15_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK MDIOS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_WKUP_IRQHandler
+ B MDIOS_WKUP_IRQHandler
+
+ PUBWEAK MDIOS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_IRQHandler
+ B MDIOS_IRQHandler
+
+ PUBWEAK JPEG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+JPEG_IRQHandler
+ B JPEG_IRQHandler
+
+ PUBWEAK MDMA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDMA_IRQHandler
+ B MDMA_IRQHandler
+
+ PUBWEAK SDMMC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC2_IRQHandler
+ B SDMMC2_IRQHandler
+
+ PUBWEAK HSEM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM1_IRQHandler
+ B HSEM1_IRQHandler
+
+ PUBWEAK DAC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DAC2_IRQHandler
+ B DAC2_IRQHandler
+
+ PUBWEAK DMAMUX2_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX2_OVR_IRQHandler
+ B DMAMUX2_OVR_IRQHandler
+
+ PUBWEAK BDMA2_Channel0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel0_IRQHandler
+ B BDMA2_Channel0_IRQHandler
+
+ PUBWEAK BDMA2_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel1_IRQHandler
+ B BDMA2_Channel1_IRQHandler
+
+ PUBWEAK BDMA2_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel2_IRQHandler
+ B BDMA2_Channel2_IRQHandler
+
+ PUBWEAK BDMA2_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel3_IRQHandler
+ B BDMA2_Channel3_IRQHandler
+
+ PUBWEAK BDMA2_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel4_IRQHandler
+ B BDMA2_Channel4_IRQHandler
+
+ PUBWEAK BDMA2_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel5_IRQHandler
+ B BDMA2_Channel5_IRQHandler
+
+ PUBWEAK BDMA2_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel6_IRQHandler
+ B BDMA2_Channel6_IRQHandler
+
+ PUBWEAK BDMA2_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel7_IRQHandler
+ B BDMA2_Channel7_IRQHandler
+
+ PUBWEAK COMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+ B COMP_IRQHandler
+
+ PUBWEAK LPTIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+ B LPTIM2_IRQHandler
+
+ PUBWEAK LPTIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+ B LPTIM3_IRQHandler
+
+ PUBWEAK UART9_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART9_IRQHandler
+ B UART9_IRQHandler
+
+ PUBWEAK USART10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART10_IRQHandler
+ B USART10_IRQHandler
+
+ PUBWEAK LPUART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+ B LPUART1_IRQHandler
+
+ PUBWEAK CRS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+ B CRS_IRQHandler
+
+ PUBWEAK ECC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ECC_IRQHandler
+ B ECC_IRQHandler
+
+ PUBWEAK DTS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DTS_IRQHandler
+ B DTS_IRQHandler
+
+ PUBWEAK WAKEUP_PIN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WAKEUP_PIN_IRQHandler
+ B WAKEUP_PIN_IRQHandler
+
+ PUBWEAK OCTOSPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI2_IRQHandler
+ B OCTOSPI2_IRQHandler
+
+ PUBWEAK GFXMMU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+GFXMMU_IRQHandler
+ B GFXMMU_IRQHandler
+
+ PUBWEAK BDMA1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA1_IRQHandler
+ B BDMA1_IRQHandler
+ END
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h7b0xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h7b0xx.s new file mode 100644 index 0000000..f5b7550 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h7b0xx.s @@ -0,0 +1,969 @@ +;/******************************************************************************
+;* @file startup_stm32h7b0xx.s
+;* @author MCD Application Team
+;* @brief STM32H7B0xx devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog Interrupt
+ DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection
+ DCD RTC_TAMP_STAMP_CSS_LSE_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD DFSDM2_IRQHandler ; DFSDM2 Interrupt
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD DFSDM1_FLT4_IRQHandler ; DFSDM Filter4 Interrupt
+ DCD DFSDM1_FLT5_IRQHandler ; DFSDM Filter5 Interrupt
+ DCD DFSDM1_FLT6_IRQHandler ; DFSDM Filter6 Interrupt
+ DCD DFSDM1_FLT7_IRQHandler ; DFSDM Filter7 Interrupt
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_PSSI_IRQHandler ; DCMI, PSSI
+ DCD CRYP_IRQHandler ; CRYP crypto global interrupt
+ DCD HASH_RNG_IRQHandler ; HASH, RNG
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD OCTOSPI1_IRQHandler ; OCTOSPI1
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD 0 ; Reserved
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD JPEG_IRQHandler ; JPEG global Interrupt
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD 0 ; Reserved
+ DCD DAC2_IRQHandler ; DAC2 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA2_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA2_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA2_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA2_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA2_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA2_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA2_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA2_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP_IRQHandler ; COMP global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD UART9_IRQHandler ; UART9 global interrupt
+ DCD USART10_IRQHandler ; USART10 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD 0 ; Reserved
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC
+ DCD 0 ; Reserved
+ DCD DTS_IRQHandler ; DTS
+ DCD 0 ; Reserved
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+ DCD OCTOSPI2_IRQHandler ; OCTOSPI2
+ DCD OTFDEC1_IRQHandler ; OTFDEC1
+ DCD OTFDEC2_IRQHandler ; OTFDEC2
+ DCD GFXMMU_IRQHandler ; GFXMMU
+ DCD BDMA1_IRQHandler ; BDMA1
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_PVM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+ B PVD_PVM_IRQHandler
+
+ PUBWEAK RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+ B RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream0_IRQHandler
+ B DMA1_Stream0_IRQHandler
+
+ PUBWEAK DMA1_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream1_IRQHandler
+ B DMA1_Stream1_IRQHandler
+
+ PUBWEAK DMA1_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream2_IRQHandler
+ B DMA1_Stream2_IRQHandler
+
+ PUBWEAK DMA1_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream3_IRQHandler
+ B DMA1_Stream3_IRQHandler
+
+ PUBWEAK DMA1_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream4_IRQHandler
+ B DMA1_Stream4_IRQHandler
+
+ PUBWEAK DMA1_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream5_IRQHandler
+ B DMA1_Stream5_IRQHandler
+
+ PUBWEAK DMA1_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream6_IRQHandler
+ B DMA1_Stream6_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK FDCAN1_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+ B FDCAN1_IT0_IRQHandler
+
+ PUBWEAK FDCAN2_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT0_IRQHandler
+ B FDCAN2_IT0_IRQHandler
+
+ PUBWEAK FDCAN1_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+ B FDCAN1_IT1_IRQHandler
+
+ PUBWEAK FDCAN2_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT1_IRQHandler
+ B FDCAN2_IT1_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK DFSDM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM2_IRQHandler
+ B DFSDM2_IRQHandler
+
+ PUBWEAK TIM8_BRK_TIM12_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_TIM12_IRQHandler
+ B TIM8_BRK_TIM12_IRQHandler
+
+ PUBWEAK TIM8_UP_TIM13_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_TIM13_IRQHandler
+ B TIM8_UP_TIM13_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_TIM14_IRQHandler
+ B TIM8_TRG_COM_TIM14_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK DMA1_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream7_IRQHandler
+ B DMA1_Stream7_IRQHandler
+
+ PUBWEAK FMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+ B FMC_IRQHandler
+
+ PUBWEAK SDMMC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+ B SDMMC1_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream0_IRQHandler
+ B DMA2_Stream0_IRQHandler
+
+ PUBWEAK DMA2_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream1_IRQHandler
+ B DMA2_Stream1_IRQHandler
+
+ PUBWEAK DMA2_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream2_IRQHandler
+ B DMA2_Stream2_IRQHandler
+
+ PUBWEAK DMA2_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream3_IRQHandler
+ B DMA2_Stream3_IRQHandler
+
+ PUBWEAK DMA2_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream4_IRQHandler
+ B DMA2_Stream4_IRQHandler
+
+ PUBWEAK FDCAN_CAL_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN_CAL_IRQHandler
+ B FDCAN_CAL_IRQHandler
+
+ PUBWEAK DFSDM1_FLT4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT4_IRQHandler
+ B DFSDM1_FLT4_IRQHandler
+
+ PUBWEAK DFSDM1_FLT5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT5_IRQHandler
+ B DFSDM1_FLT5_IRQHandler
+
+ PUBWEAK DFSDM1_FLT6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT6_IRQHandler
+ B DFSDM1_FLT6_IRQHandler
+
+ PUBWEAK DFSDM1_FLT7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT7_IRQHandler
+ B DFSDM1_FLT7_IRQHandler
+
+ PUBWEAK DMA2_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream5_IRQHandler
+ B DMA2_Stream5_IRQHandler
+
+ PUBWEAK DMA2_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream6_IRQHandler
+ B DMA2_Stream6_IRQHandler
+
+ PUBWEAK DMA2_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream7_IRQHandler
+ B DMA2_Stream7_IRQHandler
+
+ PUBWEAK USART6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler
+ B USART6_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_OUT_IRQHandler
+ B OTG_HS_EP1_OUT_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_IN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_IN_IRQHandler
+ B OTG_HS_EP1_IN_IRQHandler
+
+ PUBWEAK OTG_HS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_WKUP_IRQHandler
+ B OTG_HS_WKUP_IRQHandler
+
+ PUBWEAK OTG_HS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_IRQHandler
+ B OTG_HS_IRQHandler
+
+ PUBWEAK DCMI_PSSI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_PSSI_IRQHandler
+ B DCMI_PSSI_IRQHandler
+
+ PUBWEAK CRYP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CRYP_IRQHandler
+ B CRYP_IRQHandler
+
+ PUBWEAK HASH_RNG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HASH_RNG_IRQHandler
+ B HASH_RNG_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ PUBWEAK UART7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART7_IRQHandler
+ B UART7_IRQHandler
+
+ PUBWEAK UART8_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART8_IRQHandler
+ B UART8_IRQHandler
+
+ PUBWEAK SPI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+ B SPI4_IRQHandler
+
+ PUBWEAK SPI5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI5_IRQHandler
+ B SPI5_IRQHandler
+
+ PUBWEAK SPI6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI6_IRQHandler
+ B SPI6_IRQHandler
+
+ PUBWEAK SAI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+ B SAI1_IRQHandler
+
+ PUBWEAK LTDC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_IRQHandler
+ B LTDC_IRQHandler
+
+ PUBWEAK LTDC_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_ER_IRQHandler
+ B LTDC_ER_IRQHandler
+
+ PUBWEAK DMA2D_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+ B DMA2D_IRQHandler
+
+ PUBWEAK SAI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+ B SAI2_IRQHandler
+
+ PUBWEAK OCTOSPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI1_IRQHandler
+ B OCTOSPI1_IRQHandler
+
+ PUBWEAK LPTIM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+ B LPTIM1_IRQHandler
+
+ PUBWEAK CEC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler
+ B CEC_IRQHandler
+
+ PUBWEAK I2C4_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+ B I2C4_EV_IRQHandler
+
+ PUBWEAK I2C4_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+ B I2C4_ER_IRQHandler
+
+ PUBWEAK SPDIF_RX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPDIF_RX_IRQHandler
+ B SPDIF_RX_IRQHandler
+
+ PUBWEAK DMAMUX1_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+
+DMAMUX1_OVR_IRQHandler
+ B DMAMUX1_OVR_IRQHandler
+
+ PUBWEAK DFSDM1_FLT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+
+DFSDM1_FLT0_IRQHandler
+ B DFSDM1_FLT0_IRQHandler
+
+ PUBWEAK DFSDM1_FLT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+ B DFSDM1_FLT1_IRQHandler
+
+ PUBWEAK DFSDM1_FLT2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+ B DFSDM1_FLT2_IRQHandler
+
+ PUBWEAK DFSDM1_FLT3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+ B DFSDM1_FLT3_IRQHandler
+
+ PUBWEAK SWPMI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SWPMI1_IRQHandler
+ B SWPMI1_IRQHandler
+
+ PUBWEAK TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+ B TIM15_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK MDIOS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_WKUP_IRQHandler
+ B MDIOS_WKUP_IRQHandler
+
+ PUBWEAK MDIOS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_IRQHandler
+ B MDIOS_IRQHandler
+
+ PUBWEAK JPEG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+JPEG_IRQHandler
+ B JPEG_IRQHandler
+
+ PUBWEAK MDMA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDMA_IRQHandler
+ B MDMA_IRQHandler
+
+ PUBWEAK SDMMC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC2_IRQHandler
+ B SDMMC2_IRQHandler
+
+ PUBWEAK HSEM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM1_IRQHandler
+ B HSEM1_IRQHandler
+
+ PUBWEAK DAC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DAC2_IRQHandler
+ B DAC2_IRQHandler
+
+ PUBWEAK DMAMUX2_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX2_OVR_IRQHandler
+ B DMAMUX2_OVR_IRQHandler
+
+ PUBWEAK BDMA2_Channel0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel0_IRQHandler
+ B BDMA2_Channel0_IRQHandler
+
+ PUBWEAK BDMA2_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel1_IRQHandler
+ B BDMA2_Channel1_IRQHandler
+
+ PUBWEAK BDMA2_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel2_IRQHandler
+ B BDMA2_Channel2_IRQHandler
+
+ PUBWEAK BDMA2_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel3_IRQHandler
+ B BDMA2_Channel3_IRQHandler
+
+ PUBWEAK BDMA2_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel4_IRQHandler
+ B BDMA2_Channel4_IRQHandler
+
+ PUBWEAK BDMA2_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel5_IRQHandler
+ B BDMA2_Channel5_IRQHandler
+
+ PUBWEAK BDMA2_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel6_IRQHandler
+ B BDMA2_Channel6_IRQHandler
+
+ PUBWEAK BDMA2_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel7_IRQHandler
+ B BDMA2_Channel7_IRQHandler
+
+ PUBWEAK COMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+ B COMP_IRQHandler
+
+ PUBWEAK LPTIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+ B LPTIM2_IRQHandler
+
+ PUBWEAK LPTIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+ B LPTIM3_IRQHandler
+
+ PUBWEAK UART9_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART9_IRQHandler
+ B UART9_IRQHandler
+
+ PUBWEAK USART10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART10_IRQHandler
+ B USART10_IRQHandler
+
+ PUBWEAK LPUART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+ B LPUART1_IRQHandler
+
+ PUBWEAK CRS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+ B CRS_IRQHandler
+
+ PUBWEAK ECC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ECC_IRQHandler
+ B ECC_IRQHandler
+
+ PUBWEAK DTS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DTS_IRQHandler
+ B DTS_IRQHandler
+
+ PUBWEAK WAKEUP_PIN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WAKEUP_PIN_IRQHandler
+ B WAKEUP_PIN_IRQHandler
+
+ PUBWEAK OCTOSPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI2_IRQHandler
+ B OCTOSPI2_IRQHandler
+
+ PUBWEAK OTFDEC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTFDEC1_IRQHandler
+ B OTFDEC1_IRQHandler
+
+ PUBWEAK OTFDEC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTFDEC2_IRQHandler
+ B OTFDEC2_IRQHandler
+
+ PUBWEAK GFXMMU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+GFXMMU_IRQHandler
+ B GFXMMU_IRQHandler
+
+ PUBWEAK BDMA1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA1_IRQHandler
+ B BDMA1_IRQHandler
+ END
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h7b0xxq.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h7b0xxq.s new file mode 100644 index 0000000..b80e6ad --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h7b0xxq.s @@ -0,0 +1,969 @@ +;/******************************************************************************
+;* @file startup_stm32h7b0xxq.s
+;* @author MCD Application Team
+;* @brief STM32H7B0xx devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog Interrupt
+ DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection
+ DCD RTC_TAMP_STAMP_CSS_LSE_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD DFSDM2_IRQHandler ; DFSDM2 Interrupt
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD DFSDM1_FLT4_IRQHandler ; DFSDM Filter4 Interrupt
+ DCD DFSDM1_FLT5_IRQHandler ; DFSDM Filter5 Interrupt
+ DCD DFSDM1_FLT6_IRQHandler ; DFSDM Filter6 Interrupt
+ DCD DFSDM1_FLT7_IRQHandler ; DFSDM Filter7 Interrupt
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_PSSI_IRQHandler ; DCMI, PSSI
+ DCD CRYP_IRQHandler ; CRYP crypto global interrupt
+ DCD HASH_RNG_IRQHandler ; HASH, RNG
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD OCTOSPI1_IRQHandler ; OCTOSPI1
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD 0 ; Reserved
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD JPEG_IRQHandler ; JPEG global Interrupt
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD 0 ; Reserved
+ DCD DAC2_IRQHandler ; DAC2 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA2_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA2_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA2_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA2_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA2_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA2_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA2_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA2_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP_IRQHandler ; COMP global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD UART9_IRQHandler ; UART9 global interrupt
+ DCD USART10_IRQHandler ; USART10 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD 0 ; Reserved
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC
+ DCD 0 ; Reserved
+ DCD DTS_IRQHandler ; DTS
+ DCD 0 ; Reserved
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+ DCD OCTOSPI2_IRQHandler ; OCTOSPI2
+ DCD OTFDEC1_IRQHandler ; OTFDEC1
+ DCD OTFDEC2_IRQHandler ; OTFDEC2
+ DCD GFXMMU_IRQHandler ; GFXMMU
+ DCD BDMA1_IRQHandler ; BDMA1
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_PVM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+ B PVD_PVM_IRQHandler
+
+ PUBWEAK RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+ B RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream0_IRQHandler
+ B DMA1_Stream0_IRQHandler
+
+ PUBWEAK DMA1_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream1_IRQHandler
+ B DMA1_Stream1_IRQHandler
+
+ PUBWEAK DMA1_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream2_IRQHandler
+ B DMA1_Stream2_IRQHandler
+
+ PUBWEAK DMA1_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream3_IRQHandler
+ B DMA1_Stream3_IRQHandler
+
+ PUBWEAK DMA1_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream4_IRQHandler
+ B DMA1_Stream4_IRQHandler
+
+ PUBWEAK DMA1_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream5_IRQHandler
+ B DMA1_Stream5_IRQHandler
+
+ PUBWEAK DMA1_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream6_IRQHandler
+ B DMA1_Stream6_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK FDCAN1_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+ B FDCAN1_IT0_IRQHandler
+
+ PUBWEAK FDCAN2_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT0_IRQHandler
+ B FDCAN2_IT0_IRQHandler
+
+ PUBWEAK FDCAN1_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+ B FDCAN1_IT1_IRQHandler
+
+ PUBWEAK FDCAN2_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT1_IRQHandler
+ B FDCAN2_IT1_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK DFSDM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM2_IRQHandler
+ B DFSDM2_IRQHandler
+
+ PUBWEAK TIM8_BRK_TIM12_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_TIM12_IRQHandler
+ B TIM8_BRK_TIM12_IRQHandler
+
+ PUBWEAK TIM8_UP_TIM13_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_TIM13_IRQHandler
+ B TIM8_UP_TIM13_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_TIM14_IRQHandler
+ B TIM8_TRG_COM_TIM14_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK DMA1_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream7_IRQHandler
+ B DMA1_Stream7_IRQHandler
+
+ PUBWEAK FMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+ B FMC_IRQHandler
+
+ PUBWEAK SDMMC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+ B SDMMC1_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream0_IRQHandler
+ B DMA2_Stream0_IRQHandler
+
+ PUBWEAK DMA2_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream1_IRQHandler
+ B DMA2_Stream1_IRQHandler
+
+ PUBWEAK DMA2_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream2_IRQHandler
+ B DMA2_Stream2_IRQHandler
+
+ PUBWEAK DMA2_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream3_IRQHandler
+ B DMA2_Stream3_IRQHandler
+
+ PUBWEAK DMA2_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream4_IRQHandler
+ B DMA2_Stream4_IRQHandler
+
+ PUBWEAK FDCAN_CAL_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN_CAL_IRQHandler
+ B FDCAN_CAL_IRQHandler
+
+ PUBWEAK DFSDM1_FLT4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT4_IRQHandler
+ B DFSDM1_FLT4_IRQHandler
+
+ PUBWEAK DFSDM1_FLT5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT5_IRQHandler
+ B DFSDM1_FLT5_IRQHandler
+
+ PUBWEAK DFSDM1_FLT6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT6_IRQHandler
+ B DFSDM1_FLT6_IRQHandler
+
+ PUBWEAK DFSDM1_FLT7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT7_IRQHandler
+ B DFSDM1_FLT7_IRQHandler
+
+ PUBWEAK DMA2_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream5_IRQHandler
+ B DMA2_Stream5_IRQHandler
+
+ PUBWEAK DMA2_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream6_IRQHandler
+ B DMA2_Stream6_IRQHandler
+
+ PUBWEAK DMA2_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream7_IRQHandler
+ B DMA2_Stream7_IRQHandler
+
+ PUBWEAK USART6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler
+ B USART6_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_OUT_IRQHandler
+ B OTG_HS_EP1_OUT_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_IN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_IN_IRQHandler
+ B OTG_HS_EP1_IN_IRQHandler
+
+ PUBWEAK OTG_HS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_WKUP_IRQHandler
+ B OTG_HS_WKUP_IRQHandler
+
+ PUBWEAK OTG_HS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_IRQHandler
+ B OTG_HS_IRQHandler
+
+ PUBWEAK DCMI_PSSI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_PSSI_IRQHandler
+ B DCMI_PSSI_IRQHandler
+
+ PUBWEAK CRYP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CRYP_IRQHandler
+ B CRYP_IRQHandler
+
+ PUBWEAK HASH_RNG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HASH_RNG_IRQHandler
+ B HASH_RNG_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ PUBWEAK UART7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART7_IRQHandler
+ B UART7_IRQHandler
+
+ PUBWEAK UART8_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART8_IRQHandler
+ B UART8_IRQHandler
+
+ PUBWEAK SPI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+ B SPI4_IRQHandler
+
+ PUBWEAK SPI5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI5_IRQHandler
+ B SPI5_IRQHandler
+
+ PUBWEAK SPI6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI6_IRQHandler
+ B SPI6_IRQHandler
+
+ PUBWEAK SAI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+ B SAI1_IRQHandler
+
+ PUBWEAK LTDC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_IRQHandler
+ B LTDC_IRQHandler
+
+ PUBWEAK LTDC_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_ER_IRQHandler
+ B LTDC_ER_IRQHandler
+
+ PUBWEAK DMA2D_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+ B DMA2D_IRQHandler
+
+ PUBWEAK SAI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+ B SAI2_IRQHandler
+
+ PUBWEAK OCTOSPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI1_IRQHandler
+ B OCTOSPI1_IRQHandler
+
+ PUBWEAK LPTIM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+ B LPTIM1_IRQHandler
+
+ PUBWEAK CEC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler
+ B CEC_IRQHandler
+
+ PUBWEAK I2C4_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+ B I2C4_EV_IRQHandler
+
+ PUBWEAK I2C4_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+ B I2C4_ER_IRQHandler
+
+ PUBWEAK SPDIF_RX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPDIF_RX_IRQHandler
+ B SPDIF_RX_IRQHandler
+
+ PUBWEAK DMAMUX1_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+
+DMAMUX1_OVR_IRQHandler
+ B DMAMUX1_OVR_IRQHandler
+
+ PUBWEAK DFSDM1_FLT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+
+DFSDM1_FLT0_IRQHandler
+ B DFSDM1_FLT0_IRQHandler
+
+ PUBWEAK DFSDM1_FLT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+ B DFSDM1_FLT1_IRQHandler
+
+ PUBWEAK DFSDM1_FLT2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+ B DFSDM1_FLT2_IRQHandler
+
+ PUBWEAK DFSDM1_FLT3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+ B DFSDM1_FLT3_IRQHandler
+
+ PUBWEAK SWPMI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SWPMI1_IRQHandler
+ B SWPMI1_IRQHandler
+
+ PUBWEAK TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+ B TIM15_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK MDIOS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_WKUP_IRQHandler
+ B MDIOS_WKUP_IRQHandler
+
+ PUBWEAK MDIOS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_IRQHandler
+ B MDIOS_IRQHandler
+
+ PUBWEAK JPEG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+JPEG_IRQHandler
+ B JPEG_IRQHandler
+
+ PUBWEAK MDMA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDMA_IRQHandler
+ B MDMA_IRQHandler
+
+ PUBWEAK SDMMC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC2_IRQHandler
+ B SDMMC2_IRQHandler
+
+ PUBWEAK HSEM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM1_IRQHandler
+ B HSEM1_IRQHandler
+
+ PUBWEAK DAC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DAC2_IRQHandler
+ B DAC2_IRQHandler
+
+ PUBWEAK DMAMUX2_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX2_OVR_IRQHandler
+ B DMAMUX2_OVR_IRQHandler
+
+ PUBWEAK BDMA2_Channel0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel0_IRQHandler
+ B BDMA2_Channel0_IRQHandler
+
+ PUBWEAK BDMA2_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel1_IRQHandler
+ B BDMA2_Channel1_IRQHandler
+
+ PUBWEAK BDMA2_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel2_IRQHandler
+ B BDMA2_Channel2_IRQHandler
+
+ PUBWEAK BDMA2_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel3_IRQHandler
+ B BDMA2_Channel3_IRQHandler
+
+ PUBWEAK BDMA2_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel4_IRQHandler
+ B BDMA2_Channel4_IRQHandler
+
+ PUBWEAK BDMA2_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel5_IRQHandler
+ B BDMA2_Channel5_IRQHandler
+
+ PUBWEAK BDMA2_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel6_IRQHandler
+ B BDMA2_Channel6_IRQHandler
+
+ PUBWEAK BDMA2_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel7_IRQHandler
+ B BDMA2_Channel7_IRQHandler
+
+ PUBWEAK COMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+ B COMP_IRQHandler
+
+ PUBWEAK LPTIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+ B LPTIM2_IRQHandler
+
+ PUBWEAK LPTIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+ B LPTIM3_IRQHandler
+
+ PUBWEAK UART9_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART9_IRQHandler
+ B UART9_IRQHandler
+
+ PUBWEAK USART10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART10_IRQHandler
+ B USART10_IRQHandler
+
+ PUBWEAK LPUART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+ B LPUART1_IRQHandler
+
+ PUBWEAK CRS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+ B CRS_IRQHandler
+
+ PUBWEAK ECC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ECC_IRQHandler
+ B ECC_IRQHandler
+
+ PUBWEAK DTS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DTS_IRQHandler
+ B DTS_IRQHandler
+
+ PUBWEAK WAKEUP_PIN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WAKEUP_PIN_IRQHandler
+ B WAKEUP_PIN_IRQHandler
+
+ PUBWEAK OCTOSPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI2_IRQHandler
+ B OCTOSPI2_IRQHandler
+
+ PUBWEAK OTFDEC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTFDEC1_IRQHandler
+ B OTFDEC1_IRQHandler
+
+ PUBWEAK OTFDEC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTFDEC2_IRQHandler
+ B OTFDEC2_IRQHandler
+
+ PUBWEAK GFXMMU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+GFXMMU_IRQHandler
+ B GFXMMU_IRQHandler
+
+ PUBWEAK BDMA1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA1_IRQHandler
+ B BDMA1_IRQHandler
+ END
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h7b3xx.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h7b3xx.s new file mode 100644 index 0000000..d7b5802 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h7b3xx.s @@ -0,0 +1,969 @@ +;/******************************************************************************
+;* @file startup_stm32h7b3xx.s
+;* @author MCD Application Team
+;* @brief STM32H7B3xx devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog Interrupt
+ DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection
+ DCD RTC_TAMP_STAMP_CSS_LSE_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD DFSDM2_IRQHandler ; DFSDM2 Interrupt
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD DFSDM1_FLT4_IRQHandler ; DFSDM Filter4 Interrupt
+ DCD DFSDM1_FLT5_IRQHandler ; DFSDM Filter5 Interrupt
+ DCD DFSDM1_FLT6_IRQHandler ; DFSDM Filter6 Interrupt
+ DCD DFSDM1_FLT7_IRQHandler ; DFSDM Filter7 Interrupt
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_PSSI_IRQHandler ; DCMI, PSSI
+ DCD CRYP_IRQHandler ; CRYP crypto global interrupt
+ DCD HASH_RNG_IRQHandler ; HASH, RNG
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD OCTOSPI1_IRQHandler ; OCTOSPI1
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD 0 ; Reserved
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD JPEG_IRQHandler ; JPEG global Interrupt
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD 0 ; Reserved
+ DCD DAC2_IRQHandler ; DAC2 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA2_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA2_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA2_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA2_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA2_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA2_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA2_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA2_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP_IRQHandler ; COMP global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD UART9_IRQHandler ; UART9 global interrupt
+ DCD USART10_IRQHandler ; USART10 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD 0 ; Reserved
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC
+ DCD 0 ; Reserved
+ DCD DTS_IRQHandler ; DTS
+ DCD 0 ; Reserved
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+ DCD OCTOSPI2_IRQHandler ; OCTOSPI2
+ DCD OTFDEC1_IRQHandler ; OTFDEC1
+ DCD OTFDEC2_IRQHandler ; OTFDEC2
+ DCD GFXMMU_IRQHandler ; GFXMMU
+ DCD BDMA1_IRQHandler ; BDMA1
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_PVM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+ B PVD_PVM_IRQHandler
+
+ PUBWEAK RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+ B RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream0_IRQHandler
+ B DMA1_Stream0_IRQHandler
+
+ PUBWEAK DMA1_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream1_IRQHandler
+ B DMA1_Stream1_IRQHandler
+
+ PUBWEAK DMA1_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream2_IRQHandler
+ B DMA1_Stream2_IRQHandler
+
+ PUBWEAK DMA1_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream3_IRQHandler
+ B DMA1_Stream3_IRQHandler
+
+ PUBWEAK DMA1_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream4_IRQHandler
+ B DMA1_Stream4_IRQHandler
+
+ PUBWEAK DMA1_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream5_IRQHandler
+ B DMA1_Stream5_IRQHandler
+
+ PUBWEAK DMA1_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream6_IRQHandler
+ B DMA1_Stream6_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK FDCAN1_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+ B FDCAN1_IT0_IRQHandler
+
+ PUBWEAK FDCAN2_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT0_IRQHandler
+ B FDCAN2_IT0_IRQHandler
+
+ PUBWEAK FDCAN1_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+ B FDCAN1_IT1_IRQHandler
+
+ PUBWEAK FDCAN2_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT1_IRQHandler
+ B FDCAN2_IT1_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK DFSDM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM2_IRQHandler
+ B DFSDM2_IRQHandler
+
+ PUBWEAK TIM8_BRK_TIM12_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_TIM12_IRQHandler
+ B TIM8_BRK_TIM12_IRQHandler
+
+ PUBWEAK TIM8_UP_TIM13_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_TIM13_IRQHandler
+ B TIM8_UP_TIM13_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_TIM14_IRQHandler
+ B TIM8_TRG_COM_TIM14_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK DMA1_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream7_IRQHandler
+ B DMA1_Stream7_IRQHandler
+
+ PUBWEAK FMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+ B FMC_IRQHandler
+
+ PUBWEAK SDMMC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+ B SDMMC1_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream0_IRQHandler
+ B DMA2_Stream0_IRQHandler
+
+ PUBWEAK DMA2_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream1_IRQHandler
+ B DMA2_Stream1_IRQHandler
+
+ PUBWEAK DMA2_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream2_IRQHandler
+ B DMA2_Stream2_IRQHandler
+
+ PUBWEAK DMA2_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream3_IRQHandler
+ B DMA2_Stream3_IRQHandler
+
+ PUBWEAK DMA2_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream4_IRQHandler
+ B DMA2_Stream4_IRQHandler
+
+ PUBWEAK FDCAN_CAL_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN_CAL_IRQHandler
+ B FDCAN_CAL_IRQHandler
+
+ PUBWEAK DFSDM1_FLT4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT4_IRQHandler
+ B DFSDM1_FLT4_IRQHandler
+
+ PUBWEAK DFSDM1_FLT5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT5_IRQHandler
+ B DFSDM1_FLT5_IRQHandler
+
+ PUBWEAK DFSDM1_FLT6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT6_IRQHandler
+ B DFSDM1_FLT6_IRQHandler
+
+ PUBWEAK DFSDM1_FLT7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT7_IRQHandler
+ B DFSDM1_FLT7_IRQHandler
+
+ PUBWEAK DMA2_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream5_IRQHandler
+ B DMA2_Stream5_IRQHandler
+
+ PUBWEAK DMA2_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream6_IRQHandler
+ B DMA2_Stream6_IRQHandler
+
+ PUBWEAK DMA2_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream7_IRQHandler
+ B DMA2_Stream7_IRQHandler
+
+ PUBWEAK USART6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler
+ B USART6_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_OUT_IRQHandler
+ B OTG_HS_EP1_OUT_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_IN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_IN_IRQHandler
+ B OTG_HS_EP1_IN_IRQHandler
+
+ PUBWEAK OTG_HS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_WKUP_IRQHandler
+ B OTG_HS_WKUP_IRQHandler
+
+ PUBWEAK OTG_HS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_IRQHandler
+ B OTG_HS_IRQHandler
+
+ PUBWEAK DCMI_PSSI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_PSSI_IRQHandler
+ B DCMI_PSSI_IRQHandler
+
+ PUBWEAK CRYP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CRYP_IRQHandler
+ B CRYP_IRQHandler
+
+ PUBWEAK HASH_RNG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HASH_RNG_IRQHandler
+ B HASH_RNG_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ PUBWEAK UART7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART7_IRQHandler
+ B UART7_IRQHandler
+
+ PUBWEAK UART8_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART8_IRQHandler
+ B UART8_IRQHandler
+
+ PUBWEAK SPI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+ B SPI4_IRQHandler
+
+ PUBWEAK SPI5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI5_IRQHandler
+ B SPI5_IRQHandler
+
+ PUBWEAK SPI6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI6_IRQHandler
+ B SPI6_IRQHandler
+
+ PUBWEAK SAI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+ B SAI1_IRQHandler
+
+ PUBWEAK LTDC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_IRQHandler
+ B LTDC_IRQHandler
+
+ PUBWEAK LTDC_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_ER_IRQHandler
+ B LTDC_ER_IRQHandler
+
+ PUBWEAK DMA2D_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+ B DMA2D_IRQHandler
+
+ PUBWEAK SAI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+ B SAI2_IRQHandler
+
+ PUBWEAK OCTOSPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI1_IRQHandler
+ B OCTOSPI1_IRQHandler
+
+ PUBWEAK LPTIM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+ B LPTIM1_IRQHandler
+
+ PUBWEAK CEC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler
+ B CEC_IRQHandler
+
+ PUBWEAK I2C4_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+ B I2C4_EV_IRQHandler
+
+ PUBWEAK I2C4_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+ B I2C4_ER_IRQHandler
+
+ PUBWEAK SPDIF_RX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPDIF_RX_IRQHandler
+ B SPDIF_RX_IRQHandler
+
+ PUBWEAK DMAMUX1_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+
+DMAMUX1_OVR_IRQHandler
+ B DMAMUX1_OVR_IRQHandler
+
+ PUBWEAK DFSDM1_FLT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+
+DFSDM1_FLT0_IRQHandler
+ B DFSDM1_FLT0_IRQHandler
+
+ PUBWEAK DFSDM1_FLT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+ B DFSDM1_FLT1_IRQHandler
+
+ PUBWEAK DFSDM1_FLT2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+ B DFSDM1_FLT2_IRQHandler
+
+ PUBWEAK DFSDM1_FLT3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+ B DFSDM1_FLT3_IRQHandler
+
+ PUBWEAK SWPMI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SWPMI1_IRQHandler
+ B SWPMI1_IRQHandler
+
+ PUBWEAK TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+ B TIM15_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK MDIOS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_WKUP_IRQHandler
+ B MDIOS_WKUP_IRQHandler
+
+ PUBWEAK MDIOS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_IRQHandler
+ B MDIOS_IRQHandler
+
+ PUBWEAK JPEG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+JPEG_IRQHandler
+ B JPEG_IRQHandler
+
+ PUBWEAK MDMA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDMA_IRQHandler
+ B MDMA_IRQHandler
+
+ PUBWEAK SDMMC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC2_IRQHandler
+ B SDMMC2_IRQHandler
+
+ PUBWEAK HSEM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM1_IRQHandler
+ B HSEM1_IRQHandler
+
+ PUBWEAK DAC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DAC2_IRQHandler
+ B DAC2_IRQHandler
+
+ PUBWEAK DMAMUX2_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX2_OVR_IRQHandler
+ B DMAMUX2_OVR_IRQHandler
+
+ PUBWEAK BDMA2_Channel0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel0_IRQHandler
+ B BDMA2_Channel0_IRQHandler
+
+ PUBWEAK BDMA2_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel1_IRQHandler
+ B BDMA2_Channel1_IRQHandler
+
+ PUBWEAK BDMA2_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel2_IRQHandler
+ B BDMA2_Channel2_IRQHandler
+
+ PUBWEAK BDMA2_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel3_IRQHandler
+ B BDMA2_Channel3_IRQHandler
+
+ PUBWEAK BDMA2_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel4_IRQHandler
+ B BDMA2_Channel4_IRQHandler
+
+ PUBWEAK BDMA2_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel5_IRQHandler
+ B BDMA2_Channel5_IRQHandler
+
+ PUBWEAK BDMA2_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel6_IRQHandler
+ B BDMA2_Channel6_IRQHandler
+
+ PUBWEAK BDMA2_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel7_IRQHandler
+ B BDMA2_Channel7_IRQHandler
+
+ PUBWEAK COMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+ B COMP_IRQHandler
+
+ PUBWEAK LPTIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+ B LPTIM2_IRQHandler
+
+ PUBWEAK LPTIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+ B LPTIM3_IRQHandler
+
+ PUBWEAK UART9_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART9_IRQHandler
+ B UART9_IRQHandler
+
+ PUBWEAK USART10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART10_IRQHandler
+ B USART10_IRQHandler
+
+ PUBWEAK LPUART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+ B LPUART1_IRQHandler
+
+ PUBWEAK CRS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+ B CRS_IRQHandler
+
+ PUBWEAK ECC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ECC_IRQHandler
+ B ECC_IRQHandler
+
+ PUBWEAK DTS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DTS_IRQHandler
+ B DTS_IRQHandler
+
+ PUBWEAK WAKEUP_PIN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WAKEUP_PIN_IRQHandler
+ B WAKEUP_PIN_IRQHandler
+
+ PUBWEAK OCTOSPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI2_IRQHandler
+ B OCTOSPI2_IRQHandler
+
+ PUBWEAK OTFDEC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTFDEC1_IRQHandler
+ B OTFDEC1_IRQHandler
+
+ PUBWEAK OTFDEC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTFDEC2_IRQHandler
+ B OTFDEC2_IRQHandler
+
+ PUBWEAK GFXMMU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+GFXMMU_IRQHandler
+ B GFXMMU_IRQHandler
+
+ PUBWEAK BDMA1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA1_IRQHandler
+ B BDMA1_IRQHandler
+ END
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h7b3xxq.s b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h7b3xxq.s new file mode 100644 index 0000000..dfbffc0 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h7b3xxq.s @@ -0,0 +1,969 @@ +;/******************************************************************************
+;* @file startup_stm32h7b3xxq.s
+;* @author MCD Application Team
+;* @brief STM32H7B3xx devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog Interrupt
+ DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection
+ DCD RTC_TAMP_STAMP_CSS_LSE_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD DFSDM2_IRQHandler ; DFSDM2 Interrupt
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD DFSDM1_FLT4_IRQHandler ; DFSDM Filter4 Interrupt
+ DCD DFSDM1_FLT5_IRQHandler ; DFSDM Filter5 Interrupt
+ DCD DFSDM1_FLT6_IRQHandler ; DFSDM Filter6 Interrupt
+ DCD DFSDM1_FLT7_IRQHandler ; DFSDM Filter7 Interrupt
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_PSSI_IRQHandler ; DCMI, PSSI
+ DCD CRYP_IRQHandler ; CRYP crypto global interrupt
+ DCD HASH_RNG_IRQHandler ; HASH, RNG
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD OCTOSPI1_IRQHandler ; OCTOSPI1
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD 0 ; Reserved
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD JPEG_IRQHandler ; JPEG global Interrupt
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD 0 ; Reserved
+ DCD DAC2_IRQHandler ; DAC2 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA2_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA2_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA2_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA2_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA2_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA2_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA2_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA2_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP_IRQHandler ; COMP global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD UART9_IRQHandler ; UART9 global interrupt
+ DCD USART10_IRQHandler ; USART10 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD 0 ; Reserved
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC
+ DCD 0 ; Reserved
+ DCD DTS_IRQHandler ; DTS
+ DCD 0 ; Reserved
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+ DCD OCTOSPI2_IRQHandler ; OCTOSPI2
+ DCD OTFDEC1_IRQHandler ; OTFDEC1
+ DCD OTFDEC2_IRQHandler ; OTFDEC2
+ DCD GFXMMU_IRQHandler ; GFXMMU
+ DCD BDMA1_IRQHandler ; BDMA1
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_PVM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+ B PVD_PVM_IRQHandler
+
+ PUBWEAK RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+ B RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream0_IRQHandler
+ B DMA1_Stream0_IRQHandler
+
+ PUBWEAK DMA1_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream1_IRQHandler
+ B DMA1_Stream1_IRQHandler
+
+ PUBWEAK DMA1_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream2_IRQHandler
+ B DMA1_Stream2_IRQHandler
+
+ PUBWEAK DMA1_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream3_IRQHandler
+ B DMA1_Stream3_IRQHandler
+
+ PUBWEAK DMA1_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream4_IRQHandler
+ B DMA1_Stream4_IRQHandler
+
+ PUBWEAK DMA1_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream5_IRQHandler
+ B DMA1_Stream5_IRQHandler
+
+ PUBWEAK DMA1_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream6_IRQHandler
+ B DMA1_Stream6_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK FDCAN1_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+ B FDCAN1_IT0_IRQHandler
+
+ PUBWEAK FDCAN2_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT0_IRQHandler
+ B FDCAN2_IT0_IRQHandler
+
+ PUBWEAK FDCAN1_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+ B FDCAN1_IT1_IRQHandler
+
+ PUBWEAK FDCAN2_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT1_IRQHandler
+ B FDCAN2_IT1_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK DFSDM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM2_IRQHandler
+ B DFSDM2_IRQHandler
+
+ PUBWEAK TIM8_BRK_TIM12_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_TIM12_IRQHandler
+ B TIM8_BRK_TIM12_IRQHandler
+
+ PUBWEAK TIM8_UP_TIM13_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_TIM13_IRQHandler
+ B TIM8_UP_TIM13_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_TIM14_IRQHandler
+ B TIM8_TRG_COM_TIM14_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK DMA1_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream7_IRQHandler
+ B DMA1_Stream7_IRQHandler
+
+ PUBWEAK FMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+ B FMC_IRQHandler
+
+ PUBWEAK SDMMC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+ B SDMMC1_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream0_IRQHandler
+ B DMA2_Stream0_IRQHandler
+
+ PUBWEAK DMA2_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream1_IRQHandler
+ B DMA2_Stream1_IRQHandler
+
+ PUBWEAK DMA2_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream2_IRQHandler
+ B DMA2_Stream2_IRQHandler
+
+ PUBWEAK DMA2_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream3_IRQHandler
+ B DMA2_Stream3_IRQHandler
+
+ PUBWEAK DMA2_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream4_IRQHandler
+ B DMA2_Stream4_IRQHandler
+
+ PUBWEAK FDCAN_CAL_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN_CAL_IRQHandler
+ B FDCAN_CAL_IRQHandler
+
+ PUBWEAK DFSDM1_FLT4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT4_IRQHandler
+ B DFSDM1_FLT4_IRQHandler
+
+ PUBWEAK DFSDM1_FLT5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT5_IRQHandler
+ B DFSDM1_FLT5_IRQHandler
+
+ PUBWEAK DFSDM1_FLT6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT6_IRQHandler
+ B DFSDM1_FLT6_IRQHandler
+
+ PUBWEAK DFSDM1_FLT7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT7_IRQHandler
+ B DFSDM1_FLT7_IRQHandler
+
+ PUBWEAK DMA2_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream5_IRQHandler
+ B DMA2_Stream5_IRQHandler
+
+ PUBWEAK DMA2_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream6_IRQHandler
+ B DMA2_Stream6_IRQHandler
+
+ PUBWEAK DMA2_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream7_IRQHandler
+ B DMA2_Stream7_IRQHandler
+
+ PUBWEAK USART6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler
+ B USART6_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_OUT_IRQHandler
+ B OTG_HS_EP1_OUT_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_IN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_IN_IRQHandler
+ B OTG_HS_EP1_IN_IRQHandler
+
+ PUBWEAK OTG_HS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_WKUP_IRQHandler
+ B OTG_HS_WKUP_IRQHandler
+
+ PUBWEAK OTG_HS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_IRQHandler
+ B OTG_HS_IRQHandler
+
+ PUBWEAK DCMI_PSSI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_PSSI_IRQHandler
+ B DCMI_PSSI_IRQHandler
+
+ PUBWEAK CRYP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CRYP_IRQHandler
+ B CRYP_IRQHandler
+
+ PUBWEAK HASH_RNG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HASH_RNG_IRQHandler
+ B HASH_RNG_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ PUBWEAK UART7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART7_IRQHandler
+ B UART7_IRQHandler
+
+ PUBWEAK UART8_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART8_IRQHandler
+ B UART8_IRQHandler
+
+ PUBWEAK SPI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+ B SPI4_IRQHandler
+
+ PUBWEAK SPI5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI5_IRQHandler
+ B SPI5_IRQHandler
+
+ PUBWEAK SPI6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI6_IRQHandler
+ B SPI6_IRQHandler
+
+ PUBWEAK SAI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+ B SAI1_IRQHandler
+
+ PUBWEAK LTDC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_IRQHandler
+ B LTDC_IRQHandler
+
+ PUBWEAK LTDC_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_ER_IRQHandler
+ B LTDC_ER_IRQHandler
+
+ PUBWEAK DMA2D_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+ B DMA2D_IRQHandler
+
+ PUBWEAK SAI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+ B SAI2_IRQHandler
+
+ PUBWEAK OCTOSPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI1_IRQHandler
+ B OCTOSPI1_IRQHandler
+
+ PUBWEAK LPTIM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+ B LPTIM1_IRQHandler
+
+ PUBWEAK CEC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler
+ B CEC_IRQHandler
+
+ PUBWEAK I2C4_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+ B I2C4_EV_IRQHandler
+
+ PUBWEAK I2C4_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+ B I2C4_ER_IRQHandler
+
+ PUBWEAK SPDIF_RX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPDIF_RX_IRQHandler
+ B SPDIF_RX_IRQHandler
+
+ PUBWEAK DMAMUX1_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+
+DMAMUX1_OVR_IRQHandler
+ B DMAMUX1_OVR_IRQHandler
+
+ PUBWEAK DFSDM1_FLT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+
+DFSDM1_FLT0_IRQHandler
+ B DFSDM1_FLT0_IRQHandler
+
+ PUBWEAK DFSDM1_FLT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+ B DFSDM1_FLT1_IRQHandler
+
+ PUBWEAK DFSDM1_FLT2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+ B DFSDM1_FLT2_IRQHandler
+
+ PUBWEAK DFSDM1_FLT3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+ B DFSDM1_FLT3_IRQHandler
+
+ PUBWEAK SWPMI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SWPMI1_IRQHandler
+ B SWPMI1_IRQHandler
+
+ PUBWEAK TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+ B TIM15_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK MDIOS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_WKUP_IRQHandler
+ B MDIOS_WKUP_IRQHandler
+
+ PUBWEAK MDIOS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_IRQHandler
+ B MDIOS_IRQHandler
+
+ PUBWEAK JPEG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+JPEG_IRQHandler
+ B JPEG_IRQHandler
+
+ PUBWEAK MDMA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDMA_IRQHandler
+ B MDMA_IRQHandler
+
+ PUBWEAK SDMMC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC2_IRQHandler
+ B SDMMC2_IRQHandler
+
+ PUBWEAK HSEM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM1_IRQHandler
+ B HSEM1_IRQHandler
+
+ PUBWEAK DAC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DAC2_IRQHandler
+ B DAC2_IRQHandler
+
+ PUBWEAK DMAMUX2_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX2_OVR_IRQHandler
+ B DMAMUX2_OVR_IRQHandler
+
+ PUBWEAK BDMA2_Channel0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel0_IRQHandler
+ B BDMA2_Channel0_IRQHandler
+
+ PUBWEAK BDMA2_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel1_IRQHandler
+ B BDMA2_Channel1_IRQHandler
+
+ PUBWEAK BDMA2_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel2_IRQHandler
+ B BDMA2_Channel2_IRQHandler
+
+ PUBWEAK BDMA2_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel3_IRQHandler
+ B BDMA2_Channel3_IRQHandler
+
+ PUBWEAK BDMA2_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel4_IRQHandler
+ B BDMA2_Channel4_IRQHandler
+
+ PUBWEAK BDMA2_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel5_IRQHandler
+ B BDMA2_Channel5_IRQHandler
+
+ PUBWEAK BDMA2_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel6_IRQHandler
+ B BDMA2_Channel6_IRQHandler
+
+ PUBWEAK BDMA2_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel7_IRQHandler
+ B BDMA2_Channel7_IRQHandler
+
+ PUBWEAK COMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+ B COMP_IRQHandler
+
+ PUBWEAK LPTIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+ B LPTIM2_IRQHandler
+
+ PUBWEAK LPTIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+ B LPTIM3_IRQHandler
+
+ PUBWEAK UART9_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART9_IRQHandler
+ B UART9_IRQHandler
+
+ PUBWEAK USART10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART10_IRQHandler
+ B USART10_IRQHandler
+
+ PUBWEAK LPUART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+ B LPUART1_IRQHandler
+
+ PUBWEAK CRS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+ B CRS_IRQHandler
+
+ PUBWEAK ECC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ECC_IRQHandler
+ B ECC_IRQHandler
+
+ PUBWEAK DTS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DTS_IRQHandler
+ B DTS_IRQHandler
+
+ PUBWEAK WAKEUP_PIN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WAKEUP_PIN_IRQHandler
+ B WAKEUP_PIN_IRQHandler
+
+ PUBWEAK OCTOSPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI2_IRQHandler
+ B OCTOSPI2_IRQHandler
+
+ PUBWEAK OTFDEC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTFDEC1_IRQHandler
+ B OTFDEC1_IRQHandler
+
+ PUBWEAK OTFDEC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTFDEC2_IRQHandler
+ B OTFDEC2_IRQHandler
+
+ PUBWEAK GFXMMU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+GFXMMU_IRQHandler
+ B GFXMMU_IRQHandler
+
+ PUBWEAK BDMA1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA1_IRQHandler
+ B BDMA1_IRQHandler
+ END
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c new file mode 100644 index 0000000..851ebcb --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c @@ -0,0 +1,450 @@ +/**
+ ******************************************************************************
+ * @file system_stm32h7xx.c
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
+ *
+ * This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32h7xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock, it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32h7xx_system
+ * @{
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32h7xx.h"
+#include <math.h>
+
+#if !defined (HSE_VALUE)
+#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (CSI_VALUE)
+ #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Defines
+ * @{
+ */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) */
+/* #define DATA_IN_D2_SRAM */
+
+/* Note: Following vector table addresses must be defined in line with linker
+ configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+ anywhere in FLASH BANK1 or AXI SRAM, else the vector table is kept at the automatic
+ remap of boot address selected */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+/*!< Uncomment the following line if you need to relocate your vector Table
+ in D2 AXI SRAM else user remap will be done in FLASH BANK2. */
+/* #define VECT_TAB_SRAM */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS D2_AXISRAM_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x400. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x400. */
+#else
+#define VECT_TAB_BASE_ADDRESS FLASH_BANK2_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x400. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x400. */
+#endif /* VECT_TAB_SRAM */
+#else
+/*!< Uncomment the following line if you need to relocate your vector Table
+ in D1 AXI SRAM else user remap will be done in FLASH BANK1. */
+/* #define VECT_TAB_SRAM */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x400. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x400. */
+#else
+#define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x400. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x400. */
+#endif /* VECT_TAB_SRAM */
+#endif /* DUAL_CORE && CORE_CM4 */
+#endif /* USER_VECT_TAB_ADDRESS */
+/******************************************************************************/
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Variables
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+ uint32_t SystemCoreClock = 64000000;
+ uint32_t SystemD2Clock = 64000000;
+ const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting and vector table location
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit (void)
+{
+#if defined (DATA_IN_D2_SRAM)
+ __IO uint32_t tmpreg;
+#endif /* DATA_IN_D2_SRAM */
+
+ /* FPU settings ------------------------------------------------------------*/
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
+ #endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+
+ /* Increasing the CPU frequency */
+ if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+ }
+
+ /* Set HSION bit */
+ RCC->CR |= RCC_CR_HSION;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */
+ RCC->CR &= 0xEAF6ED7FU;
+
+ /* Decreasing the number of wait states because of lower CPU frequency */
+ if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+ }
+
+#if defined(D3_SRAM_BASE)
+ /* Reset D1CFGR register */
+ RCC->D1CFGR = 0x00000000;
+
+ /* Reset D2CFGR register */
+ RCC->D2CFGR = 0x00000000;
+
+ /* Reset D3CFGR register */
+ RCC->D3CFGR = 0x00000000;
+#else
+ /* Reset CDCFGR1 register */
+ RCC->CDCFGR1 = 0x00000000;
+
+ /* Reset CDCFGR2 register */
+ RCC->CDCFGR2 = 0x00000000;
+
+ /* Reset SRDCFGR register */
+ RCC->SRDCFGR = 0x00000000;
+#endif
+ /* Reset PLLCKSELR register */
+ RCC->PLLCKSELR = 0x02020200;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x01FF0000;
+ /* Reset PLL1DIVR register */
+ RCC->PLL1DIVR = 0x01010280;
+ /* Reset PLL1FRACR register */
+ RCC->PLL1FRACR = 0x00000000;
+
+ /* Reset PLL2DIVR register */
+ RCC->PLL2DIVR = 0x01010280;
+
+ /* Reset PLL2FRACR register */
+
+ RCC->PLL2FRACR = 0x00000000;
+ /* Reset PLL3DIVR register */
+ RCC->PLL3DIVR = 0x01010280;
+
+ /* Reset PLL3FRACR register */
+ RCC->PLL3FRACR = 0x00000000;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= 0xFFFBFFFFU;
+
+ /* Disable all interrupts */
+ RCC->CIER = 0x00000000;
+
+#if (STM32H7_DEV_ID == 0x450UL)
+ /* dual core CM7 or single core line */
+ if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
+ {
+ /* if stm32h7 revY*/
+ /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
+ *((__IO uint32_t*)0x51008108) = 0x000000001U;
+ }
+#endif /* STM32H7_DEV_ID */
+
+#if defined(DATA_IN_D2_SRAM)
+ /* in case of initialized data in D2 SRAM (AHB SRAM), enable the D2 SRAM clock (AHB SRAM clock) */
+#if defined(RCC_AHB2ENR_D2SRAM3EN)
+ RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
+#elif defined(RCC_AHB2ENR_D2SRAM2EN)
+ RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN);
+#else
+ RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
+#endif /* RCC_AHB2ENR_D2SRAM3EN */
+
+ tmpreg = RCC->AHB2ENR;
+ (void) tmpreg;
+#endif /* DATA_IN_D2_SRAM */
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+ /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D2 AXI-RAM or in Internal FLASH */
+#endif /* USER_VECT_TAB_ADDRESS */
+
+#else
+ /*
+ * Disable the FMC bank1 (enabled after reset).
+ * This, prevents CPU speculation access on this bank which blocks the use of FMC during
+ * 24us. During this time the others FMC master (such as LTDC) cannot use it!
+ */
+ FMC_Bank1_R->BTCR[0] = 0x000030D2;
+
+ /* Configure the Vector Table location -------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */
+#endif /* USER_VECT_TAB_ADDRESS */
+
+#endif /*DUAL_CORE && CORE_CM4*/
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock , it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
+ * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
+ *
+ * (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+ * 4 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ * (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+ * 64 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+ * 25 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
+ uint32_t common_system_clock;
+ float_t fracn1, pllvco;
+
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+
+ switch (RCC->CFGR & RCC_CFGR_SWS)
+ {
+ case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
+ common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
+ break;
+
+ case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
+ common_system_clock = CSI_VALUE;
+ break;
+
+ case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
+ common_system_clock = HSE_VALUE;
+ break;
+
+ case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
+
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
+ SYSCLK = PLL_VCO / PLLR
+ */
+ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+ pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ;
+ pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
+ fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
+
+ if (pllm != 0U)
+ {
+ switch (pllsource)
+ {
+ case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */
+
+ hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
+ pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+
+ break;
+
+ case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */
+ pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+ break;
+
+ case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */
+ pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+ break;
+
+ default:
+ hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
+ pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+ break;
+ }
+ pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
+ common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
+ }
+ else
+ {
+ common_system_clock = 0U;
+ }
+ break;
+
+ default:
+ common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
+ break;
+ }
+
+ /* Compute SystemClock frequency --------------------------------------------------*/
+#if defined (RCC_D1CFGR_D1CPRE)
+ tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
+
+ /* common_system_clock frequency : CM7 CPU frequency */
+ common_system_clock >>= tmp;
+
+ /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
+ SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+
+#else
+ tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos];
+
+ /* common_system_clock frequency : CM7 CPU frequency */
+ common_system_clock >>= tmp;
+
+ /* SystemD2Clock frequency : AXI and AHBs Clock frequency */
+ SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+ SystemCoreClock = SystemD2Clock;
+#else
+ SystemCoreClock = common_system_clock;
+#endif /* DUAL_CORE && CORE_CM4 */
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_boot_cm4_cm7.c b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_boot_cm4_cm7.c new file mode 100644 index 0000000..f46d7e5 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_boot_cm4_cm7.c @@ -0,0 +1,420 @@ +/**
+ ******************************************************************************
+ * @file system_stm32h7xx_dualcore_boot_cm4_cm7.c
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
+ * This provides system initialization template function is case of
+ * an application using a dual core STM32H7 device where
+ * Cortex-M7 and Cortex-M4 boot are enabled at the FLASH option bytes
+ *
+ * This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32h7xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock, it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32h7xx_system
+ * @{
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32h7xx.h"
+#include <math.h>
+
+#if !defined (HSE_VALUE)
+#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (CSI_VALUE)
+ #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Defines
+ * @{
+ */
+
+/************************* Miscellaneous Configuration ************************/
+/* Note: Following vector table addresses must be defined in line with linker
+ configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+ anywhere in FLASH BANK1 or AXI SRAM, else the vector table is kept at the automatic
+ remap of boot address selected */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+#if defined(CORE_CM4)
+/*!< Uncomment the following line if you need to relocate your vector Table
+ in D2 AXI SRAM else user remap will be done in FLASH BANK2. */
+/* #define VECT_TAB_SRAM */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS D2_AXISRAM_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x400. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x400. */
+#else
+#define VECT_TAB_BASE_ADDRESS FLASH_BANK2_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x400. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x400. */
+#endif /* VECT_TAB_SRAM */
+#elif defined(CORE_CM7)
+/*!< Uncomment the following line if you need to relocate your vector Table
+ in D1 AXI SRAM else user remap will be done in FLASH BANK1. */
+/* #define VECT_TAB_SRAM */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x400. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x400. */
+#else
+#define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x400. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x400. */
+#endif /* VECT_TAB_SRAM */
+#else
+#error Please #define CORE_CM4 or CORE_CM7
+#endif /* CORE_CM4 */
+#endif /* USER_VECT_TAB_ADDRESS */
+/******************************************************************************/
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Variables
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+ uint32_t SystemCoreClock = 64000000;
+ uint32_t SystemD2Clock = 64000000;
+ const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting and vector table location
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit (void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
+ #endif
+
+ /*SEVONPEND enabled so that an interrupt coming from the CPU(n) interrupt signal is
+ detectable by the CPU after a WFI/WFE instruction.*/
+ SCB->SCR |= SCB_SCR_SEVONPEND_Msk;
+
+#if defined(CORE_CM7)
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Increasing the CPU frequency */
+ if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+ }
+
+ /* Set HSION bit */
+ RCC->CR |= RCC_CR_HSION;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */
+ RCC->CR &= 0xEAF6ED7FU;
+
+ /* Decreasing the number of wait states because of lower CPU frequency */
+ if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+ }
+
+ /* Reset D1CFGR register */
+ RCC->D1CFGR = 0x00000000;
+
+ /* Reset D2CFGR register */
+ RCC->D2CFGR = 0x00000000;
+
+ /* Reset D3CFGR register */
+ RCC->D3CFGR = 0x00000000;
+
+ /* Reset PLLCKSELR register */
+ RCC->PLLCKSELR = 0x02020200;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x01FF0000;
+ /* Reset PLL1DIVR register */
+ RCC->PLL1DIVR = 0x01010280;
+ /* Reset PLL1FRACR register */
+ RCC->PLL1FRACR = 0x00000000;
+
+ /* Reset PLL2DIVR register */
+ RCC->PLL2DIVR = 0x01010280;
+
+ /* Reset PLL2FRACR register */
+
+ RCC->PLL2FRACR = 0x00000000;
+ /* Reset PLL3DIVR register */
+ RCC->PLL3DIVR = 0x01010280;
+
+ /* Reset PLL3FRACR register */
+ RCC->PLL3FRACR = 0x00000000;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= 0xFFFBFFFFU;
+
+ /* Disable all interrupts */
+ RCC->CIER = 0x00000000;
+
+ /* Enable CortexM7 HSEM EXTI line (line 78)*/
+ EXTI_D2->EMR3 |= 0x4000UL;
+
+ if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
+ {
+ /* if stm32h7 revY*/
+ /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
+ *((__IO uint32_t*)0x51008108) = 0x000000001U;
+ }
+
+#endif /* CORE_CM7*/
+
+#if defined(CORE_CM4)
+ /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D2 AXI-RAM or in Internal FLASH */
+#endif /* USER_VECT_TAB_ADDRESS */
+
+#elif defined(CORE_CM7)
+ /*
+ * Disable the FMC bank1 (enabled after reset).
+ * This, prevents CPU speculation access on this bank which blocks the use of FMC during
+ * 24us. During this time the others FMC master (such as LTDC) cannot use it!
+ */
+ FMC_Bank1_R->BTCR[0] = 0x000030D2;
+
+ /* Configure the Vector Table location -------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */
+#endif /* USER_VECT_TAB_ADDRESS */
+
+#else
+#error Please #define CORE_CM4 or CORE_CM7
+#endif /* CORE_CM4 */
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock , it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
+ * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
+ *
+ * (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+ * 4 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ * (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+ * 64 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+ * 25 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
+ uint32_t common_system_clock;
+ float_t fracn1, pllvco;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+
+ switch (RCC->CFGR & RCC_CFGR_SWS)
+ {
+ case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
+ common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
+ break;
+
+ case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
+ common_system_clock = CSI_VALUE;
+ break;
+
+ case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
+ common_system_clock = HSE_VALUE;
+ break;
+
+ case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
+
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
+ SYSCLK = PLL_VCO / PLLR
+ */
+ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+ pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ;
+ pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
+ fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
+
+ if (pllm != 0U)
+ {
+ switch (pllsource)
+ {
+ case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */
+
+ hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
+ pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+
+ break;
+
+ case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */
+ pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+ break;
+
+ case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */
+ pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+ break;
+
+ default:
+ hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
+ pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+ break;
+ }
+ pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
+ common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
+ }
+ else
+ {
+ common_system_clock = 0U;
+ }
+ break;
+
+ default:
+ common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
+ break;
+ }
+
+ /* Compute SystemClock frequency --------------------------------------------------*/
+ tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
+
+ /* common_system_clock frequency : CM7 CPU frequency */
+ common_system_clock >>= tmp;
+
+ /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
+ SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+
+#if defined(CORE_CM4)
+ SystemCoreClock = SystemD2Clock;
+#else
+ SystemCoreClock = common_system_clock;
+#endif /* CORE_CM4 */
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm4_cm7gated.c b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm4_cm7gated.c new file mode 100644 index 0000000..52e92b2 --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm4_cm7gated.c @@ -0,0 +1,411 @@ +/**
+ ******************************************************************************
+ * @file system_stm32h7xx_dualcore_bootcm4_cm7gated.c
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
+ * This file provides system initialization template function is case of
+ * an application using a dual core STM32H7 device where :
+ * Cortex-M4 boot is enabled at the FLASH option bytes
+ * Cortex-M7 boot is disabled at the FLASH option bytes
+ * Cortex-M7 boot can be enabled by the the Cortex-M4 (when needed)
+ * using the appropriate HAL function "HAL_RCCEx_EnableBootCore"
+ *
+ * This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32h7xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock, it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32h7xx_system
+ * @{
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32h7xx.h"
+#include <math.h>
+
+#if !defined (HSE_VALUE)
+#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (CSI_VALUE)
+ #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Defines
+ * @{
+ */
+
+/************************* Miscellaneous Configuration ************************/
+/* Note: Following vector table addresses must be defined in line with linker
+ configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+ anywhere in FLASH BANK1 or AXI SRAM, else the vector table is kept at the automatic
+ remap of boot address selected */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+#if defined(CORE_CM4)
+/*!< Uncomment the following line if you need to relocate your vector Table
+ in D2 AXI SRAM else user remap will be done in FLASH BANK2. */
+/* #define VECT_TAB_SRAM */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS D2_AXISRAM_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x400. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x400. */
+#else
+#define VECT_TAB_BASE_ADDRESS FLASH_BANK2_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x400. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x400. */
+#endif /* VECT_TAB_SRAM */
+#elif defined(CORE_CM7)
+/*!< Uncomment the following line if you need to relocate your vector Table
+ in D1 AXI SRAM else user remap will be done in FLASH BANK1. */
+/* #define VECT_TAB_SRAM */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x400. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x400. */
+#else
+#define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x400. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x400. */
+#endif /* VECT_TAB_SRAM */
+#else
+#error Please #define CORE_CM4 or CORE_CM7
+#endif /* CORE_CM4 */
+#endif /* USER_VECT_TAB_ADDRESS */
+/******************************************************************************/
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Variables
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+ uint32_t SystemCoreClock = 64000000;
+ uint32_t SystemD2Clock = 64000000;
+ const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting and vector table location
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit (void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
+ #endif
+
+#if defined(CORE_CM4)
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Increasing the CPU frequency */
+ if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+ }
+
+ /* Set HSION bit */
+ RCC->CR |= RCC_CR_HSION;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */
+ RCC->CR &= 0xEAF6ED7FU;
+
+ /* Decreasing the number of wait states because of lower CPU frequency */
+ if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+ }
+
+ /* Reset D1CFGR register */
+ RCC->D1CFGR = 0x00000000;
+
+ /* Reset D2CFGR register */
+ RCC->D2CFGR = 0x00000000;
+
+ /* Reset D3CFGR register */
+ RCC->D3CFGR = 0x00000000;
+
+ /* Reset PLLCKSELR register */
+ RCC->PLLCKSELR = 0x02020200;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x01FF0000;
+ /* Reset PLL1DIVR register */
+ RCC->PLL1DIVR = 0x01010280;
+ /* Reset PLL1FRACR register */
+ RCC->PLL1FRACR = 0x00000000;
+
+ /* Reset PLL2DIVR register */
+ RCC->PLL2DIVR = 0x01010280;
+
+ /* Reset PLL2FRACR register */
+
+ RCC->PLL2FRACR = 0x00000000;
+ /* Reset PLL3DIVR register */
+ RCC->PLL3DIVR = 0x01010280;
+
+ /* Reset PLL3FRACR register */
+ RCC->PLL3FRACR = 0x00000000;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= 0xFFFBFFFFU;
+
+ /* Disable all interrupts */
+ RCC->CIER = 0x00000000;
+
+ /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D2 AXI-RAM or in Internal FLASH */
+#endif /* USER_VECT_TAB_ADDRESS */
+#elif defined(CORE_CM7)
+ /* dual core CM7 or single core line */
+ if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
+ {
+ /* if stm32h7 revY*/
+ /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
+ *((__IO uint32_t*)0x51008108) = 0x000000001U;
+ }
+
+ /*
+ * Disable the FMC bank1 (enabled after reset).
+ * This, prevents CPU speculation access on this bank which blocks the use of FMC during
+ * 24us. During this time the others FMC master (such as LTDC) cannot use it!
+ */
+ FMC_Bank1_R->BTCR[0] = 0x000030D2;
+
+ /* Configure the Vector Table location -------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */
+#endif /* USER_VECT_TAB_ADDRESS */
+#else
+#error Please #define CORE_CM4 or CORE_CM7
+#endif /* CORE_CM4 */
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock , it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
+ * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
+ *
+ * (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+ * 4 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ * (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+ * 64 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+ * 25 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
+ uint32_t common_system_clock;
+ float_t fracn1, pllvco;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+
+ switch (RCC->CFGR & RCC_CFGR_SWS)
+ {
+ case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
+ common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
+ break;
+
+ case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
+ common_system_clock = CSI_VALUE;
+ break;
+
+ case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
+ common_system_clock = HSE_VALUE;
+ break;
+
+ case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
+
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
+ SYSCLK = PLL_VCO / PLLR
+ */
+ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+ pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ;
+ pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
+ fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
+
+ if (pllm != 0U)
+ {
+ switch (pllsource)
+ {
+ case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */
+
+ hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
+ pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+
+ break;
+
+ case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */
+ pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+ break;
+
+ case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */
+ pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+ break;
+
+ default:
+ hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
+ pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+ break;
+ }
+ pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
+ common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
+ }
+ else
+ {
+ common_system_clock = 0U;
+ }
+ break;
+
+ default:
+ common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
+ break;
+ }
+
+ /* Compute SystemClock frequency --------------------------------------------------*/
+ tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
+
+ /* common_system_clock frequency : CM7 CPU frequency */
+ common_system_clock >>= tmp;
+
+ /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
+ SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+ SystemCoreClock = SystemD2Clock;
+#else
+ SystemCoreClock = common_system_clock;
+#endif /* DUAL_CORE && CORE_CM4 */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm7_cm4gated.c b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm7_cm4gated.c new file mode 100644 index 0000000..46f972c --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm7_cm4gated.c @@ -0,0 +1,417 @@ +/**
+ ******************************************************************************
+ * @file system_stm32h7xx_dualcore_bootcm7_cm4gated.c
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
+ * This file provides system initialization template functions is case of
+ * an application using a dual core STM32H7 device where :
+ * Cortex-M7 boot is enabled at FLASH option bytes
+ * Cortex-M4 boot is disabled at FLASH option bytes
+ * Cortex-M4 boot can be enabled by the the Cortex-M7 (when needed)
+ * using the appropriate HAL function "HAL_RCCEx_EnableBootCore"
+ *
+ * This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32h7xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock, it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32h7xx_system
+ * @{
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32h7xx.h"
+#include <math.h>
+
+#if !defined (HSE_VALUE)
+#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (CSI_VALUE)
+ #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Defines
+ * @{
+ */
+
+/************************* Miscellaneous Configuration ************************/
+/* Note: Following vector table addresses must be defined in line with linker
+ configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+ anywhere in FLASH BANK1 or AXI SRAM, else the vector table is kept at the automatic
+ remap of boot address selected */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+#if defined(CORE_CM4)
+/*!< Uncomment the following line if you need to relocate your vector Table
+ in D2 AXI SRAM else user remap will be done in FLASH BANK2. */
+/* #define VECT_TAB_SRAM */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS D2_AXISRAM_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x400. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x400. */
+#else
+#define VECT_TAB_BASE_ADDRESS FLASH_BANK2_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x400. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x400. */
+#endif /* VECT_TAB_SRAM */
+#elif defined(CORE_CM7)
+/*!< Uncomment the following line if you need to relocate your vector Table
+ in D1 AXI SRAM else user remap will be done in FLASH BANK1. */
+/* #define VECT_TAB_SRAM */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x400. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x400. */
+#else
+#define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x400. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x400. */
+#endif /* VECT_TAB_SRAM */
+#else
+#error Please #define CORE_CM4 or CORE_CM7
+#endif /* CORE_CM4 */
+#endif /* USER_VECT_TAB_ADDRESS */
+/******************************************************************************/
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Variables
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+ uint32_t SystemCoreClock = 64000000;
+ uint32_t SystemD2Clock = 64000000;
+ const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting and vector table location
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit (void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
+ #endif
+
+#if defined(CORE_CM7)
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Increasing the CPU frequency */
+ if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+ }
+
+ /* Set HSION bit */
+ RCC->CR |= RCC_CR_HSION;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */
+ RCC->CR &= 0xEAF6ED7FU;
+
+ /* Decreasing the number of wait states because of lower CPU frequency */
+ if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+ }
+
+ /* Reset D1CFGR register */
+ RCC->D1CFGR = 0x00000000;
+
+ /* Reset D2CFGR register */
+ RCC->D2CFGR = 0x00000000;
+
+ /* Reset D3CFGR register */
+ RCC->D3CFGR = 0x00000000;
+
+ /* Reset PLLCKSELR register */
+ RCC->PLLCKSELR = 0x02020200;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x01FF0000;
+ /* Reset PLL1DIVR register */
+ RCC->PLL1DIVR = 0x01010280;
+ /* Reset PLL1FRACR register */
+ RCC->PLL1FRACR = 0x00000000;
+
+ /* Reset PLL2DIVR register */
+ RCC->PLL2DIVR = 0x01010280;
+
+ /* Reset PLL2FRACR register */
+
+ RCC->PLL2FRACR = 0x00000000;
+ /* Reset PLL3DIVR register */
+ RCC->PLL3DIVR = 0x01010280;
+
+ /* Reset PLL3FRACR register */
+ RCC->PLL3FRACR = 0x00000000;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= 0xFFFBFFFFU;
+
+ /* Disable all interrupts */
+ RCC->CIER = 0x00000000;
+
+ /* dual core CM7 or single core line */
+ if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
+ {
+ /* if stm32h7 revY*/
+ /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
+ *((__IO uint32_t*)0x51008108) = 0x000000001U;
+ }
+
+#endif /* CORE_CM7 */
+
+#if defined(CORE_CM4)
+
+ /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D2 AXI-RAM or in Internal FLASH */
+#endif /* USER_VECT_TAB_ADDRESS */
+
+#elif defined(CORE_CM7)
+ /*
+ * Disable the FMC bank1 (enabled after reset).
+ * This, prevents CPU speculation access on this bank which blocks the use of FMC during
+ * 24us. During this time the others FMC master (such as LTDC) cannot use it!
+ */
+ FMC_Bank1_R->BTCR[0] = 0x000030D2;
+
+ /* Configure the Vector Table location -------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */
+#endif /* USER_VECT_TAB_ADDRESS */
+
+#else
+#error Please #define CORE_CM4 or CORE_CM7
+#endif /* CORE_CM4 */
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock , it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
+ * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
+ *
+ * (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+ * 4 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ * (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+ * 64 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+ * 25 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
+ uint32_t common_system_clock;
+ float_t fracn1, pllvco;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+
+ switch (RCC->CFGR & RCC_CFGR_SWS)
+ {
+ case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
+ common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
+ break;
+
+ case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
+ common_system_clock = CSI_VALUE;
+ break;
+
+ case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
+ common_system_clock = HSE_VALUE;
+ break;
+
+ case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
+
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
+ SYSCLK = PLL_VCO / PLLR
+ */
+ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+ pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ;
+ pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
+ fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
+
+ if (pllm != 0U)
+ {
+ switch (pllsource)
+ {
+ case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */
+
+ hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
+ pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+
+ break;
+
+ case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */
+ pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+ break;
+
+ case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */
+ pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+ break;
+
+ default:
+ hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
+ pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+ break;
+ }
+ pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
+ common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
+ }
+ else
+ {
+ common_system_clock = 0U;
+ }
+ break;
+
+ default:
+ common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
+ break;
+ }
+
+ /* Compute SystemClock frequency --------------------------------------------------*/
+ tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
+
+ /* common_system_clock frequency : CM7 CPU frequency */
+ common_system_clock >>= tmp;
+
+ /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
+ SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+
+#if defined(CORE_CM4)
+ SystemCoreClock = SystemD2Clock;
+#else
+ SystemCoreClock = common_system_clock;
+#endif /* CORE_CM4 */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_singlecore.c b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_singlecore.c new file mode 100644 index 0000000..f06738b --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_singlecore.c @@ -0,0 +1,414 @@ +/**
+ ******************************************************************************
+ * @file system_stm32h7xx.c
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
+ * This provides system initialization template function is case of
+ * an application using a single core STM32H7 device
+ *
+ * This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32h7xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32h7xx_system
+ * @{
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32h7xx.h"
+#include <math.h>
+
+#if !defined (HSE_VALUE)
+#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (CSI_VALUE)
+ #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Defines
+ * @{
+ */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) */
+/* #define DATA_IN_D2_SRAM */
+
+/* Note: Following vector table addresses must be defined in line with linker
+ configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+ anywhere in FLASH BANK1 or AXI SRAM, else the vector table is kept at the automatic
+ remap of boot address selected */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+/*!< Uncomment the following line if you need to relocate your vector Table
+ in D1 AXI SRAM else user remap will be done in FLASH BANK1. */
+/* #define VECT_TAB_SRAM */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x400. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x400. */
+#else
+#define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field.
+ This value must be a multiple of 0x400. */
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
+ This value must be a multiple of 0x400. */
+#endif /* VECT_TAB_SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
+/******************************************************************************/
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Variables
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+ uint32_t SystemCoreClock = 64000000;
+ uint32_t SystemD2Clock = 64000000;
+ const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32H7xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting and vector table location
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit (void)
+{
+#if defined (DATA_IN_D2_SRAM)
+ __IO uint32_t tmpreg;
+#endif /* DATA_IN_D2_SRAM */
+
+ /* FPU settings ------------------------------------------------------------*/
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
+ #endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+
+ /* Increasing the CPU frequency */
+ if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+ }
+
+ /* Set HSION bit */
+ RCC->CR |= RCC_CR_HSION;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */
+ RCC->CR &= 0xEAF6ED7FU;
+
+ /* Decreasing the number of wait states because of lower CPU frequency */
+ if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
+ {
+ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+ }
+
+#if defined(D3_SRAM_BASE)
+ /* Reset D1CFGR register */
+ RCC->D1CFGR = 0x00000000;
+
+ /* Reset D2CFGR register */
+ RCC->D2CFGR = 0x00000000;
+
+ /* Reset D3CFGR register */
+ RCC->D3CFGR = 0x00000000;
+#else
+ /* Reset CDCFGR1 register */
+ RCC->CDCFGR1 = 0x00000000;
+
+ /* Reset CDCFGR2 register */
+ RCC->CDCFGR2 = 0x00000000;
+
+ /* Reset SRDCFGR register */
+ RCC->SRDCFGR = 0x00000000;
+#endif
+ /* Reset PLLCKSELR register */
+ RCC->PLLCKSELR = 0x02020200;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x01FF0000;
+ /* Reset PLL1DIVR register */
+ RCC->PLL1DIVR = 0x01010280;
+ /* Reset PLL1FRACR register */
+ RCC->PLL1FRACR = 0x00000000;
+
+ /* Reset PLL2DIVR register */
+ RCC->PLL2DIVR = 0x01010280;
+
+ /* Reset PLL2FRACR register */
+
+ RCC->PLL2FRACR = 0x00000000;
+ /* Reset PLL3DIVR register */
+ RCC->PLL3DIVR = 0x01010280;
+
+ /* Reset PLL3FRACR register */
+ RCC->PLL3FRACR = 0x00000000;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= 0xFFFBFFFFU;
+
+ /* Disable all interrupts */
+ RCC->CIER = 0x00000000;
+
+#if (STM32H7_DEV_ID == 0x450UL)
+ /* single core line */
+ if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
+ {
+ /* if stm32h7 revY*/
+ /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
+ *((__IO uint32_t*)0x51008108) = 0x000000001U;
+ }
+#endif
+
+#if defined (DATA_IN_D2_SRAM)
+ /* in case of initialized data in D2 SRAM (AHB SRAM), enable the D2 SRAM clock (AHB SRAM clock) */
+#if defined(RCC_AHB2ENR_D2SRAM3EN)
+ RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
+#elif defined(RCC_AHB2ENR_D2SRAM2EN)
+ RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN);
+#else
+ RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
+#endif /* RCC_AHB2ENR_D2SRAM3EN */
+
+ tmpreg = RCC->AHB2ENR;
+ (void) tmpreg;
+#endif /* DATA_IN_D2_SRAM */
+
+ /*
+ * Disable the FMC bank1 (enabled after reset).
+ * This, prevents CPU speculation access on this bank which blocks the use of FMC during
+ * 24us. During this time the others FMC master (such as LTDC) cannot use it!
+ */
+ FMC_Bank1_R->BTCR[0] = 0x000030D2;
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */
+#endif /* USER_VECT_TAB_ADDRESS */
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock , it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
+ * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
+ *
+ * (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+ * 4 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ * (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+ * 64 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+ * 25 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
+ float_t fracn1, pllvco;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+
+ switch (RCC->CFGR & RCC_CFGR_SWS)
+ {
+ case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
+ SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
+
+ break;
+
+ case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
+ SystemCoreClock = CSI_VALUE;
+ break;
+
+ case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
+ SystemCoreClock = HSE_VALUE;
+ break;
+
+ case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
+
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
+ SYSCLK = PLL_VCO / PLLR
+ */
+ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+ pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ;
+ pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
+ fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
+
+ if (pllm != 0U)
+ {
+ switch (pllsource)
+ {
+ case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */
+
+ hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
+ pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+
+ break;
+
+ case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */
+ pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+ break;
+
+ case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */
+ pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+ break;
+
+ default:
+ hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
+ pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+ break;
+ }
+ pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
+ SystemCoreClock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
+ }
+ else
+ {
+ SystemCoreClock = 0U;
+ }
+ break;
+
+ default:
+ SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
+ break;
+ }
+
+ /* Compute SystemClock frequency --------------------------------------------------*/
+#if defined (RCC_D1CFGR_D1CPRE)
+ tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
+
+ /* SystemCoreClock frequency : CM7 CPU frequency */
+ SystemCoreClock >>= tmp;
+
+ /* SystemD2Clock frequency : AXI and AHBs Clock frequency */
+ SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+#else
+ tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos];
+
+ SystemCoreClock >>= tmp;
+ /* SystemD2Clock frequency : AXI and AHBs Clock frequency */
+ SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+#endif
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
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