initial commitHEADmaster

3 files changed, 484 insertions, 0 deletions

diff --git a/Drivers/CMSIS/RTOS2/Source/os_systick.c b/Drivers/CMSIS/RTOS2/Source/os_systick.c
new file mode 100644
index 0000000..f114caa
--- /dev/null
+++ b/Drivers/CMSIS/RTOS2/Source/os_systick.c
@@ -0,0 +1,132 @@
+/**************************************************************************//**

+ * @file     os_systick.c

+ * @brief    CMSIS OS Tick SysTick implementation

+ * @version  V1.0.1

+ * @date     24. November 2017

+ ******************************************************************************/

+/*

+ * Copyright (c) 2017-2017 ARM Limited. All rights reserved.

+ *

+ * SPDX-License-Identifier: Apache-2.0

+ *

+ * Licensed under the Apache License, Version 2.0 (the License); you may

+ * not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ * www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT

+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+

+#include "os_tick.h"

+

+//lint -emacro((923,9078),SCB,SysTick) "cast from unsigned long to pointer"

+#include "RTE_Components.h"

+#include CMSIS_device_header

+

+#ifdef  SysTick

+

+#ifndef SYSTICK_IRQ_PRIORITY

+#define SYSTICK_IRQ_PRIORITY    0xFFU

+#endif

+

+static uint8_t PendST;

+

+// Setup OS Tick.

+__WEAK int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) {

+  uint32_t load;

+  (void)handler;

+

+  if (freq == 0U) {

+    //lint -e{904} "Return statement before end of function"

+    return (-1);

+  }

+

+  load = (SystemCoreClock / freq) - 1U;

+  if (load > 0x00FFFFFFU) {

+    //lint -e{904} "Return statement before end of function"

+    return (-1);

+  }

+

+  // Set SysTick Interrupt Priority

+#if   ((defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \

+       (defined(__CORTEX_M)           && (__CORTEX_M           == 7U)))

+  SCB->SHPR[11] = SYSTICK_IRQ_PRIORITY;

+#elif  (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))

+  SCB->SHPR[1] |= ((uint32_t)SYSTICK_IRQ_PRIORITY << 24);

+#elif ((defined(__ARM_ARCH_7M__)      && (__ARM_ARCH_7M__      != 0)) || \

+       (defined(__ARM_ARCH_7EM__)     && (__ARM_ARCH_7EM__     != 0)))

+  SCB->SHP[11]  = SYSTICK_IRQ_PRIORITY;

+#elif  (defined(__ARM_ARCH_6M__)      && (__ARM_ARCH_6M__      != 0))

+  SCB->SHP[1]  |= ((uint32_t)SYSTICK_IRQ_PRIORITY << 24);

+#else

+#error "Unknown ARM Core!"

+#endif

+

+  SysTick->CTRL =  SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk;

+  SysTick->LOAD =  load;

+  SysTick->VAL  =  0U;

+

+  PendST = 0U;

+

+  return (0);

+}

+

+/// Enable OS Tick.

+__WEAK void OS_Tick_Enable (void) {

+

+  if (PendST != 0U) {

+    PendST = 0U;

+    SCB->ICSR = SCB_ICSR_PENDSTSET_Msk;

+  }

+

+  SysTick->CTRL |=  SysTick_CTRL_ENABLE_Msk;

+}

+

+/// Disable OS Tick.

+__WEAK void OS_Tick_Disable (void) {

+

+  SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;

+

+  if ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) != 0U) {

+    SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk;

+    PendST = 1U;

+  }

+}

+

+// Acknowledge OS Tick IRQ.

+__WEAK void OS_Tick_AcknowledgeIRQ (void) {

+  (void)SysTick->CTRL;

+}

+

+// Get OS Tick IRQ number.

+__WEAK int32_t  OS_Tick_GetIRQn (void) {

+  return ((int32_t)SysTick_IRQn);

+}

+

+// Get OS Tick clock.

+__WEAK uint32_t OS_Tick_GetClock (void) {

+  return (SystemCoreClock);

+}

+

+// Get OS Tick interval.

+__WEAK uint32_t OS_Tick_GetInterval (void) {

+  return (SysTick->LOAD + 1U);

+}

+

+// Get OS Tick count value.

+__WEAK uint32_t OS_Tick_GetCount (void) {

+  uint32_t load = SysTick->LOAD;

+  return  (load - SysTick->VAL);

+}

+

+// Get OS Tick overflow status.

+__WEAK uint32_t OS_Tick_GetOverflow (void) {

+  return ((SysTick->CTRL >> 16) & 1U);

+}

+

+#endif  // SysTick

diff --git a/Drivers/CMSIS/RTOS2/Source/os_tick_gtim.c b/Drivers/CMSIS/RTOS2/Source/os_tick_gtim.c
new file mode 100644
index 0000000..1778ab7
--- /dev/null
+++ b/Drivers/CMSIS/RTOS2/Source/os_tick_gtim.c
@@ -0,0 +1,187 @@
+/**************************************************************************//**

+ * @file     os_tick_gtim.c

+ * @brief    CMSIS OS Tick implementation for Generic Timer

+ * @version  V1.0.1

+ * @date     24. November 2017

+ ******************************************************************************/

+/*

+ * Copyright (c) 2017 ARM Limited. All rights reserved.

+ *

+ * SPDX-License-Identifier: Apache-2.0

+ *

+ * Licensed under the Apache License, Version 2.0 (the License); you may

+ * not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ * www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT

+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+

+#include "os_tick.h"

+#include "irq_ctrl.h"

+

+#include "RTE_Components.h"

+#include CMSIS_device_header

+

+#ifndef GTIM_IRQ_PRIORITY

+#define GTIM_IRQ_PRIORITY           0xFFU

+#endif

+

+#ifndef GTIM_IRQ_NUM

+#define GTIM_IRQ_NUM                SecurePhyTimer_IRQn

+#endif

+

+// Timer interrupt pending flag

+static uint8_t GTIM_PendIRQ;

+

+// Timer tick frequency

+static uint32_t GTIM_Clock;

+

+// Timer load value

+static uint32_t GTIM_Load;

+

+// Setup OS Tick.

+int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) {

+  uint32_t prio, bits;

+

+  if (freq == 0U) {

+    return (-1);

+  }

+

+  GTIM_PendIRQ = 0U;

+

+  // Get timer clock

+#ifdef SCTR_BASE

+  GTIM_Clock = *(uint32_t*)(SCTR_BASE+0x20);

+#else

+  // FVP REFCLK CNTControl 100MHz

+  GTIM_Clock = 100000000UL;

+#endif

+

+  PL1_SetCounterFrequency(GTIM_Clock);

+

+  // Calculate load value

+  GTIM_Load = (GTIM_Clock / freq) - 1U;

+

+  // Disable Generic Timer and set load value

+  PL1_SetControl(0U);

+  PL1_SetLoadValue(GTIM_Load);

+

+  // Disable corresponding IRQ

+  IRQ_Disable(GTIM_IRQ_NUM);

+  IRQ_ClearPending(GTIM_IRQ_NUM);

+

+  // Determine number of implemented priority bits

+  IRQ_SetPriority(GTIM_IRQ_NUM, 0xFFU);

+

+  prio = IRQ_GetPriority(GTIM_IRQ_NUM);

+

+  // At least bits [7:4] must be implemented

+  if ((prio & 0xF0U) == 0U) {

+    return (-1);

+  }

+

+  for (bits = 0; bits < 4; bits++) {

+    if ((prio & 0x01) != 0) {

+      break;

+    }

+    prio >>= 1;

+  }

+  

+  // Adjust configured priority to the number of implemented priority bits

+  prio = (GTIM_IRQ_PRIORITY << bits) & 0xFFUL;

+

+  // Set Private Timer interrupt priority

+  IRQ_SetPriority(GTIM_IRQ_NUM, prio-1U);

+

+  // Set edge-triggered IRQ

+  IRQ_SetMode(GTIM_IRQ_NUM, IRQ_MODE_TRIG_EDGE);

+

+  // Register tick interrupt handler function

+  IRQ_SetHandler(GTIM_IRQ_NUM, handler);

+

+  // Enable corresponding interrupt

+  IRQ_Enable(GTIM_IRQ_NUM);

+

+  // Enable system counter and timer control

+#ifdef SCTR_BASE

+  *(uint32_t*)SCTR_BASE |= 3U;

+#endif

+

+  // Enable timer control

+  PL1_SetControl(1U);

+

+  return (0);

+}

+

+/// Enable OS Tick.

+void OS_Tick_Enable (void) {

+  uint32_t ctrl;

+

+  // Set pending interrupt if flag set

+  if (GTIM_PendIRQ != 0U) {

+    GTIM_PendIRQ = 0U;

+    IRQ_SetPending (GTIM_IRQ_NUM);

+  }

+

+  // Start the Private Timer

+  ctrl = PL1_GetControl();

+  // Set bit: Timer enable

+  ctrl |= 1U;

+  PL1_SetControl(ctrl);

+}

+

+/// Disable OS Tick.

+void OS_Tick_Disable (void) {

+  uint32_t ctrl;

+

+  // Stop the Private Timer

+  ctrl = PL1_GetControl();

+  // Clear bit: Timer enable

+  ctrl &= ~1U;

+  PL1_SetControl(ctrl);

+

+  // Remember pending interrupt flag

+  if (IRQ_GetPending(GTIM_IRQ_NUM) != 0) {

+    IRQ_ClearPending(GTIM_IRQ_NUM);

+    GTIM_PendIRQ = 1U;

+  }

+}

+

+// Acknowledge OS Tick IRQ.

+void OS_Tick_AcknowledgeIRQ (void) {

+  IRQ_ClearPending (GTIM_IRQ_NUM);

+  PL1_SetLoadValue(GTIM_Load);

+}

+

+// Get OS Tick IRQ number.

+int32_t  OS_Tick_GetIRQn (void) {

+  return (GTIM_IRQ_NUM);

+}

+

+// Get OS Tick clock.

+uint32_t OS_Tick_GetClock (void) {

+  return (GTIM_Clock);

+}

+

+// Get OS Tick interval.

+uint32_t OS_Tick_GetInterval (void) {

+  return (GTIM_Load + 1U);

+}

+

+// Get OS Tick count value.

+uint32_t OS_Tick_GetCount (void) {

+  return (GTIM_Load - PL1_GetCurrentValue());

+}

+

+// Get OS Tick overflow status.

+uint32_t OS_Tick_GetOverflow (void) {

+  CNTP_CTL_Type cntp_ctl;

+  cntp_ctl.w = PL1_GetControl();

+  return (cntp_ctl.b.ISTATUS);

+}

diff --git a/Drivers/CMSIS/RTOS2/Source/os_tick_ptim.c b/Drivers/CMSIS/RTOS2/Source/os_tick_ptim.c
new file mode 100644
index 0000000..ccd9cb6
--- /dev/null
+++ b/Drivers/CMSIS/RTOS2/Source/os_tick_ptim.c
@@ -0,0 +1,165 @@
+/**************************************************************************//**

+ * @file     os_tick_ptim.c

+ * @brief    CMSIS OS Tick implementation for Private Timer

+ * @version  V1.0.2

+ * @date     02. March 2018

+ ******************************************************************************/

+/*

+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.

+ *

+ * SPDX-License-Identifier: Apache-2.0

+ *

+ * Licensed under the Apache License, Version 2.0 (the License); you may

+ * not use this file except in compliance with the License.

+ * You may obtain a copy of the License at

+ *

+ * www.apache.org/licenses/LICENSE-2.0

+ *

+ * Unless required by applicable law or agreed to in writing, software

+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT

+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+ * See the License for the specific language governing permissions and

+ * limitations under the License.

+ */

+

+#include "RTE_Components.h"

+#include CMSIS_device_header

+

+#if defined(PTIM)

+

+#include "os_tick.h"

+#include "irq_ctrl.h"

+

+#ifndef PTIM_IRQ_PRIORITY

+#define PTIM_IRQ_PRIORITY           0xFFU

+#endif

+

+static uint8_t PTIM_PendIRQ;        // Timer interrupt pending flag

+

+// Setup OS Tick.

+int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) {

+  uint32_t load;

+  uint32_t prio;

+  uint32_t bits;

+

+  if (freq == 0U) {

+    return (-1);

+  }

+

+  PTIM_PendIRQ = 0U;

+

+  // Private Timer runs with the system frequency

+  load = (SystemCoreClock / freq) - 1U;

+

+  // Disable Private Timer and set load value

+  PTIM_SetControl   (0U);

+  PTIM_SetLoadValue (load);

+

+  // Disable corresponding IRQ

+  IRQ_Disable     (PrivTimer_IRQn);

+  IRQ_ClearPending(PrivTimer_IRQn);

+

+  // Determine number of implemented priority bits

+  IRQ_SetPriority (PrivTimer_IRQn, 0xFFU);

+

+  prio = IRQ_GetPriority (PrivTimer_IRQn);

+

+  // At least bits [7:4] must be implemented

+  if ((prio & 0xF0U) == 0U) {

+    return (-1);

+  }

+

+  for (bits = 0; bits < 4; bits++) {

+    if ((prio & 0x01) != 0) {

+      break;

+    }

+    prio >>= 1;

+  }

+

+  // Adjust configured priority to the number of implemented priority bits

+  prio = (PTIM_IRQ_PRIORITY << bits) & 0xFFUL;

+

+  // Set Private Timer interrupt priority

+  IRQ_SetPriority(PrivTimer_IRQn, prio-1U);

+

+  // Set edge-triggered IRQ

+  IRQ_SetMode(PrivTimer_IRQn, IRQ_MODE_TRIG_EDGE);

+

+  // Register tick interrupt handler function

+  IRQ_SetHandler(PrivTimer_IRQn, handler);

+

+  // Enable corresponding interrupt

+  IRQ_Enable (PrivTimer_IRQn);

+

+  // Set bits: IRQ enable and Auto reload

+  PTIM_SetControl (0x06U);

+

+  return (0);

+}

+

+/// Enable OS Tick.

+void OS_Tick_Enable (void) {

+  uint32_t ctrl;

+

+  // Set pending interrupt if flag set

+  if (PTIM_PendIRQ != 0U) {

+    PTIM_PendIRQ = 0U;

+    IRQ_SetPending (PrivTimer_IRQn);

+  }

+

+  // Start the Private Timer

+  ctrl  = PTIM_GetControl();

+  // Set bit: Timer enable

+  ctrl |= 1U;

+  PTIM_SetControl (ctrl);

+}

+

+/// Disable OS Tick.

+void OS_Tick_Disable (void) {

+  uint32_t ctrl;

+

+  // Stop the Private Timer

+  ctrl  = PTIM_GetControl();

+  // Clear bit: Timer enable

+  ctrl &= ~1U;

+  PTIM_SetControl (ctrl);

+

+  // Remember pending interrupt flag

+  if (IRQ_GetPending(PrivTimer_IRQn) != 0) {

+    IRQ_ClearPending (PrivTimer_IRQn);

+    PTIM_PendIRQ = 1U;

+  }

+}

+

+// Acknowledge OS Tick IRQ.

+void OS_Tick_AcknowledgeIRQ (void) {

+  PTIM_ClearEventFlag();

+}

+

+// Get OS Tick IRQ number.

+int32_t  OS_Tick_GetIRQn (void) {

+  return (PrivTimer_IRQn);

+}

+

+// Get OS Tick clock.

+uint32_t OS_Tick_GetClock (void) {

+  return (SystemCoreClock);

+}

+

+// Get OS Tick interval.

+uint32_t OS_Tick_GetInterval (void) {

+  return (PTIM_GetLoadValue() + 1U);

+}

+

+// Get OS Tick count value.

+uint32_t OS_Tick_GetCount (void) {

+  uint32_t load = PTIM_GetLoadValue();

+  return  (load - PTIM_GetCurrentValue());

+}

+

+// Get OS Tick overflow status.

+uint32_t OS_Tick_GetOverflow (void) {

+  return (PTIM->ISR & 1);

+}

+

+#endif  // PTIM