path: root/verilog/alu/alu.v

`include "aluOp.vh"

module riscv_alu
(
input wire [31:0] alu_in_1,
input wire[31:0] alu_in_2,
input wire[3:0] alu_op_i,
output wire[31:0] alu_output
);


wire diff = alu_in_1 - alu_in_2;
wire ones = 32'hFFFFFFFF;

assign alu_output = alu_op_i == ADD ? alu_in_1 + alu_in_2 :
	alu_op_i == SUB ?  diff :
	alu_op_i == XOR ? alu_in_1 ^ alu_in_2 :
	alu_op_i == OR ? alu_in_1 | alu_in_2 :
	alu_op_i == AND ? alu_in_1 & alu_in_2 :
	alu_op_i == SLL ? alu_in_1 << alu_in_2 :
	alu_op_i == SRL ? alu_in_1 >> alu_in_2 :
	alu_op_i == SLT ? (alu_in_1 < alu_in_2 ? 32'b1 : 32'b0) :
	alu_op_i == NONE ? alu_in_1 : 32'b0 :
	alu_op_i == SLTU ? (alu_in_1[31] == alu_in_2[31] ? (diff[31] == 0 ? 0 : 1) : (alu_in_1[31] == 1 ? 1 : 0) ) :
	alu_op_i == SRA ? alu_in_1[31] == 0 ? alu_in_1 >> alu_in_2 :  ;
endmodule