path: root/verilog/alu/v6/aluOp.vh

`ifndef ALU_OP
`define ALU_OP
// 1st bit that is no longer there == SUB/SRA/NONE
`define ADDSUB          3'b000 
`define XOR             3'b100
`define OR              3'b110
`define AND             3'b111
`define SLL             3'b001
`define SR              3'b101
`define SLT             3'b010
`define SLTU            3'b011
`define NONE            3'b111

`endif