path: root/verilog/alu/v6/obj_dir/Valu6.cpp

// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Model implementation (design independent parts)

#include "Valu6.h"
#include "Valu6__Syms.h"
#include "verilated_vcd_c.h"

//============================================================
// Constructors

Valu6::Valu6(VerilatedContext* _vcontextp__, const char* _vcname__)
    : vlSymsp{new Valu6__Syms(_vcontextp__, _vcname__, this)}
    , alu_op_i{vlSymsp->TOP.alu_op_i}
    , alu_in_1{vlSymsp->TOP.alu_in_1}
    , alu_in_2{vlSymsp->TOP.alu_in_2}
    , alu_output{vlSymsp->TOP.alu_output}
    , rootp{&(vlSymsp->TOP)}
{
}

Valu6::Valu6(const char* _vcname__)
    : Valu6(nullptr, _vcname__)
{
}

//============================================================
// Destructor

Valu6::~Valu6() {
    delete vlSymsp;
}

//============================================================
// Evaluation loop

void Valu6___024root___eval_initial(Valu6___024root* vlSelf);
void Valu6___024root___eval_settle(Valu6___024root* vlSelf);
void Valu6___024root___eval(Valu6___024root* vlSelf);
#ifdef VL_DEBUG
void Valu6___024root___eval_debug_assertions(Valu6___024root* vlSelf);
#endif  // VL_DEBUG
void Valu6___024root___final(Valu6___024root* vlSelf);

static void _eval_initial_loop(Valu6__Syms* __restrict vlSymsp) {
    vlSymsp->__Vm_didInit = true;
    Valu6___024root___eval_initial(&(vlSymsp->TOP));
    // Evaluate till stable
    vlSymsp->__Vm_activity = true;
    do {
        VL_DEBUG_IF(VL_DBG_MSGF("+ Initial loop\n"););
        Valu6___024root___eval_settle(&(vlSymsp->TOP));
        Valu6___024root___eval(&(vlSymsp->TOP));
    } while (0);
}

void Valu6::eval_step() {
    VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate Valu6::eval_step\n"); );
#ifdef VL_DEBUG
    // Debug assertions
    Valu6___024root___eval_debug_assertions(&(vlSymsp->TOP));
#endif  // VL_DEBUG
    // Initialize
    if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp);
    // Evaluate till stable
    vlSymsp->__Vm_activity = true;
    do {
        VL_DEBUG_IF(VL_DBG_MSGF("+ Clock loop\n"););
        Valu6___024root___eval(&(vlSymsp->TOP));
    } while (0);
    // Evaluate cleanup
}

//============================================================
// Utilities

VerilatedContext* Valu6::contextp() const {
    return vlSymsp->_vm_contextp__;
}

const char* Valu6::name() const {
    return vlSymsp->name();
}

//============================================================
// Invoke final blocks

VL_ATTR_COLD void Valu6::final() {
    Valu6___024root___final(&(vlSymsp->TOP));
}

//============================================================
// Trace configuration

void Valu6___024root__trace_init_top(Valu6___024root* vlSelf, VerilatedVcd* tracep);

VL_ATTR_COLD static void trace_init(void* voidSelf, VerilatedVcd* tracep, uint32_t code) {
    // Callback from tracep->open()
    Valu6___024root* const __restrict vlSelf VL_ATTR_UNUSED = static_cast<Valu6___024root*>(voidSelf);
    Valu6__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
    if (!vlSymsp->_vm_contextp__->calcUnusedSigs()) {
        VL_FATAL_MT(__FILE__, __LINE__, __FILE__,
            "Turning on wave traces requires Verilated::traceEverOn(true) call before time 0.");
    }
    vlSymsp->__Vm_baseCode = code;
    tracep->scopeEscape(' ');
    tracep->pushNamePrefix(std::string{vlSymsp->name()} + ' ');
    Valu6___024root__trace_init_top(vlSelf, tracep);
    tracep->popNamePrefix();
    tracep->scopeEscape('.');
}

VL_ATTR_COLD void Valu6___024root__trace_register(Valu6___024root* vlSelf, VerilatedVcd* tracep);

VL_ATTR_COLD void Valu6::trace(VerilatedVcdC* tfp, int levels, int options) {
    if (false && levels && options) {}  // Prevent unused
    tfp->spTrace()->addInitCb(&trace_init, &(vlSymsp->TOP));
    Valu6___024root__trace_register(&(vlSymsp->TOP), tfp->spTrace());
}