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| author | joshua <joshua@joshuayun.com> | 2022-05-16 11:03:38 -0400 |
|---|---|---|
| committer | joshua <joshua@joshuayun.com> | 2022-05-16 11:03:38 -0400 |
| commit | 112415c3d50f900f3ee10edd1161eb80b97c42c7 (patch) | |
| tree | 070cd1baeadc653c9b4a26a80d5cd5afa03d7df5 | |
| parent | 18d1ae8dd266a6aa126479a742e0e6f257d5f8a9 (diff) | |
| download | riscv-processor-inorder-112415c3d50f900f3ee10edd1161eb80b97c42c7.tar.gz | |
gitignore
| -rw-r--r-- | .gitignore | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -1,2 +1,3 @@ verilog/*/*/obj_dir/* verilog/*/*/obj_dir +verilog/*/*/waveform.vcd |