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| author | joshua <joshua@joshuayun.com> | 2022-04-16 23:00:55 -0500 |
|---|---|---|
| committer | joshua <joshua@joshuayun.com> | 2022-04-16 23:00:55 -0500 |
| commit | d6b7d26cf51b4b3a7b5604f9b81bb43f55cbc33c (patch) | |
| tree | c337d4454d3a4d5aa01ad3531e8c723b09fe7d0e /verilog/alu/aluOp.vh | |
| parent | 2f1be3c7aabb42ac3ad4347595d5d7be0e2ad6a0 (diff) | |
| download | riscv-processor-inorder-d6b7d26cf51b4b3a7b5604f9b81bb43f55cbc33c.tar.gz | |
Added pdfs and more alu stuff
Diffstat (limited to 'verilog/alu/aluOp.vh')
| -rw-r--r-- | verilog/alu/aluOp.vh | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/verilog/alu/aluOp.vh b/verilog/alu/aluOp.vh new file mode 100644 index 0000000..c67cd33 --- /dev/null +++ b/verilog/alu/aluOp.vh @@ -0,0 +1,14 @@ +`ifndef ALU_OP +`define ALU_OP +`define ADD 4'b0000 +`define SUB 4'b1000 +`define XOR 4'b0100 +`define OR 4'b0110 +`define AND 4'b0111 +`define SLL 4'b0001 +`define SRL 4'b0101 +`define SRA 4'b1101 +`define SLT 4'b0010 +`define SLTU 4'b0011 +`define NONE 4'h1111 +`endif |