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author | joshua <joshua@fedora.framework> | 2022-05-14 23:30:38 -0500 |
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committer | joshua <joshua@fedora.framework> | 2022-05-14 23:30:38 -0500 |
commit | b8936029065835366e9e057a219c0c5194db8662 (patch) | |
tree | 31e50944ac6e23850f92bb0e0f6d851b74307f60 /verilog/alu/obj_dir/Valu___024root__Slow.cpp | |
parent | d6b7d26cf51b4b3a7b5604f9b81bb43f55cbc33c (diff) | |
download | riscv-processor-inorder-b8936029065835366e9e057a219c0c5194db8662.tar.gz |
Verilog update
Diffstat (limited to 'verilog/alu/obj_dir/Valu___024root__Slow.cpp')
-rw-r--r-- | verilog/alu/obj_dir/Valu___024root__Slow.cpp | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/verilog/alu/obj_dir/Valu___024root__Slow.cpp b/verilog/alu/obj_dir/Valu___024root__Slow.cpp new file mode 100644 index 0000000..7e197c5 --- /dev/null +++ b/verilog/alu/obj_dir/Valu___024root__Slow.cpp @@ -0,0 +1,25 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design implementation internals +// See Valu.h for the primary calling header + +#include "verilated.h" + +#include "Valu__Syms.h" +#include "Valu___024root.h" + +void Valu___024root___ctor_var_reset(Valu___024root* vlSelf); + +Valu___024root::Valu___024root(const char* _vcname__) + : VerilatedModule(_vcname__) + { + // Reset structure values + Valu___024root___ctor_var_reset(this); +} + +void Valu___024root::__Vconfigure(Valu__Syms* _vlSymsp, bool first) { + if (false && first) {} // Prevent unused + this->vlSymsp = _vlSymsp; +} + +Valu___024root::~Valu___024root() { +} |