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| author | joshua <joshua@fedora.framework> | 2022-05-14 23:30:38 -0500 |
|---|---|---|
| committer | joshua <joshua@fedora.framework> | 2022-05-14 23:30:38 -0500 |
| commit | b8936029065835366e9e057a219c0c5194db8662 (patch) | |
| tree | 31e50944ac6e23850f92bb0e0f6d851b74307f60 /verilog/alu/v1/Makefile | |
| parent | d6b7d26cf51b4b3a7b5604f9b81bb43f55cbc33c (diff) | |
| download | riscv-processor-inorder-b8936029065835366e9e057a219c0c5194db8662.tar.gz | |
Verilog update
Diffstat (limited to 'verilog/alu/v1/Makefile')
| -rw-r--r-- | verilog/alu/v1/Makefile | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/verilog/alu/v1/Makefile b/verilog/alu/v1/Makefile new file mode 100644 index 0000000..74816c7 --- /dev/null +++ b/verilog/alu/v1/Makefile @@ -0,0 +1,35 @@ +PROJ=alu +VERION:=r0.2 +RM = rm -rf +COPY = cp -a +PATH_SEP = / + + +crab: ${PROJ}.dfu + +dfu: ${PROJ}.dfu + dfu-util -D $< + + +%.json: %.v + yosys -p "read_verilog $<; synth_ecp5 -top ${PROJ} -json $@" + +%_out.config: %.json + nextpnr-ecp5 --json $< --textcfg $@ --25k --package CSFBGA285 --lpf crab.pcf + +%.bit: %_out.config + ecppack --compress --freq 38.8 --input $< --bit $@ + +%.dfu : %.bit + $(COPY) $< $@ + dfu-suffix -v 1209 -p 5af0 -a $@ + +sim: + verilator -Wall --cc --exe --build tbalu.cpp alu.v --trace && ./obj_dir/Valu > out +simclean: + rm -rf obj_dir/* out + +clean: + $(RM) -f ${PROJ}.bit ${PROJ}_out.config ${PROJ}.json ${PROJ}.dfu + +.PHONY: prog clean |