Verilog update

1 files changed, 16 insertions, 0 deletions

diff --git a/verilog/alu/v1/aluOp.h b/verilog/alu/v1/aluOp.h
new file mode 100644
index 0000000..999dac2
--- /dev/null
+++ b/verilog/alu/v1/aluOp.h
@@ -0,0 +1,16 @@
+#ifndef ALU_OP
+#define ALU_OP
+
+#define ADD             0
+#define SUB             8
+#define XOR             4
+#define OR              6
+#define AND             7
+#define SLL             1
+#define SRL             5
+#define SRA             13
+#define SLT             2
+#define SLTU            3
+#define NONE            15
+
+#endif