diff options
| author | joshua <joshua@fedora.framework> | 2022-05-14 23:30:38 -0500 |
|---|---|---|
| committer | joshua <joshua@fedora.framework> | 2022-05-14 23:30:38 -0500 |
| commit | b8936029065835366e9e057a219c0c5194db8662 (patch) | |
| tree | 31e50944ac6e23850f92bb0e0f6d851b74307f60 /verilog/alu/v6/LUTS | |
| parent | d6b7d26cf51b4b3a7b5604f9b81bb43f55cbc33c (diff) | |
| download | riscv-processor-inorder-b8936029065835366e9e057a219c0c5194db8662.tar.gz | |
Verilog update
Diffstat (limited to 'verilog/alu/v6/LUTS')
| -rw-r--r-- | verilog/alu/v6/LUTS | 172 |
1 files changed, 172 insertions, 0 deletions
diff --git a/verilog/alu/v6/LUTS b/verilog/alu/v6/LUTS new file mode 100644 index 0000000..ec716bd --- /dev/null +++ b/verilog/alu/v6/LUTS @@ -0,0 +1,172 @@ + +ADD SUB no share + + Number of wires: 233 + Number of wire bits: 644 + Number of public wires: 233 + Number of public wire bits: 644 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 256 + CCU2C 32 + L6MUX21 32 + LUT4 128 + PFUMX 64 + + + +ADD SUB Sharing + + Number of wires: 12 + Number of wire bits: 356 + Number of public wires: 12 + Number of public wire bits: 356 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 128 + CCU2C 32 + LUT4 96 + +XOR + + Number of wires: 204 + Number of wire bits: 548 + Number of public wires: 204 + Number of public wire bits: 548 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 320 + CCU2C 32 + L6MUX21 32 + LUT4 192 + PFUMX 64 + + +AND + OR + + Number of wires: 204 + Number of wire bits: 548 + Number of public wires: 204 + Number of public wire bits: 548 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 320 + CCU2C 32 + L6MUX21 32 + LUT4 192 + PFUMX 64 + + + Number of wires: 212 + Number of wire bits: 556 + Number of public wires: 212 + Number of public wire bits: 556 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 328 + CCU2C 32 + L6MUX21 34 + LUT4 196 + PFUMX 66 + + +=== alu6 === + + Number of wires: 529 + Number of wire bits: 1122 + Number of public wires: 529 + Number of public wire bits: 1122 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 731 + CCU2C 32 + L6MUX21 66 + LUT4 475 + PFUMX 158 + +=== alu6 === Shift left + + Number of wires: 526 + Number of wire bits: 1100 + Number of public wires: 526 + Number of public wire bits: 1100 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 730 + CCU2C 32 + L6MUX21 67 + LUT4 473 + PFUMX 158 + +Shift right + + Number of wires: 1161 + Number of wire bits: 2070 + Number of public wires: 1161 + Number of public wire bits: 2070 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 1456 + CCU2C 32 + L6MUX21 174 + LUT4 923 + PFUMX 327 + +Shift right muxed + +=== alu6 === + + Number of wires: 843 + Number of wire bits: 1731 + Number of public wires: 843 + Number of public wire bits: 1731 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 1134 + CCU2C 32 + L6MUX21 103 + LUT4 756 + PFUMX 243 + +Set less than signed + +=== alu6 === + + Number of wires: 843 + Number of wire bits: 1731 + Number of public wires: 843 + Number of public wire bits: 1731 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 1134 + CCU2C 32 + L6MUX21 103 + LUT4 756 + PFUMX 243 + +Set less than unsigned + +=== alu6 === + + Number of wires: 871 + Number of wire bits: 1857 + Number of public wires: 871 + Number of public wire bits: 1857 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 1183 + CCU2C 48 + L6MUX21 109 + LUT4 778 + PFUMX 248 |