Verilog update

1 files changed, 40 insertions, 0 deletions

diff --git a/verilog/alu/v6/Makefile b/verilog/alu/v6/Makefile
new file mode 100644
index 0000000..437e09f
--- /dev/null
+++ b/verilog/alu/v6/Makefile
@@ -0,0 +1,40 @@
+PROJ=alu6
+VERION:=r0.2
+RM = rm -rf
+COPY = cp -a
+PATH_SEP = /
+
+
+crab: ${PROJ}.dfu
+
+dfu: ${PROJ}.dfu
+	dfu-util -D $<
+
+
+%.json: %.v
+	yosys -p "read_verilog $<; synth_ecp5 -top ${PROJ} -json $@"
+
+%_out.config: %.json
+	nextpnr-ecp5 --json $< --textcfg $@ --25k --package CSFBGA285 --lpf crab.pcf
+
+%.bit: %_out.config
+	ecppack --compress --freq 38.8 --input $< --bit $@
+
+%.dfu : %.bit
+	$(COPY) $< $@
+	dfu-suffix -v 1209 -p 5af0 -a $@
+
+sim:
+	verilator -Wall --cc --exe --build tbalu.cpp alu6.v --trace && ./obj_dir/Valu6 > out
+simgate:
+	yosys -p "read_verilog ${PROJ}.v; synth_ecp5 -top ${PROJ} -blif ${PROJ}.blif"
+	yosys -o synth_${PROJ}.v ${PROJ}.blif
+	verilator -Wall --cc --exe --build tbalu.cpp synth_alu6.v --trace && ./obj_dir/Valu6 > out
+
+simclean:
+	rm -rf obj_dir/* out
+
+clean:
+	$(RM) -f ${PROJ}.bit ${PROJ}_out.config ${PROJ}.json ${PROJ}.dfu
+
+.PHONY: prog clean