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authorJoshua Yun <jjyun4@illinois.edu>2023-08-28 14:42:23 -0500
committerJoshua Yun <jjyun4@illinois.edu>2023-08-28 14:42:23 -0500
commitc1fa3c36da28e9e947f6279329c47777f31fe7a2 (patch)
treebd321c8e33200427b23bffe96c7c1bae90d8a044 /verilog/alu/v6/alu6.v
parentd069ea63cce08c0f5c8d7da7f8ab05115bd8d856 (diff)
downloadriscv-processor-inorder-master.tar.gz
Added new riscv processor design into git repoHEADmaster
Diffstat (limited to 'verilog/alu/v6/alu6.v')
-rw-r--r--verilog/alu/v6/alu6.v30
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diff --git a/verilog/alu/v6/alu6.v b/verilog/alu/v6/alu6.v
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-`default_nettype none
-`timescale 1us/1ns
-
-`include "aluOp.vh"
-
-module alu6
-(
-input wire [31:0] alu_in_1,
-input wire[31:0] alu_in_2,
-input wire[3:0] alu_op_i,
-output wire[31:0] alu_output
-);
-
-wire [31:0] complement2 = ~alu_in_2 + 1'b1;
-wire [31:0] sum = alu_in_1 + (alu_op_i[3] | (alu_op_i[1] & ~alu_op_i[0]) == 1'b1 ? complement2 : alu_in_2);
-wire [31:0] right = alu_in_1 >> alu_in_2[5:0] | (alu_op_i[3] == 0 ? 32'b0 :
- (32'hFFFFFFFF << (alu_in_2[31] == 1'b1 ? 5'b0 : {~alu_in_2[4] , ~alu_in_2[3], ~alu_in_2[2], ~alu_in_2[1], ~alu_in_2[0]})));
-
-assign alu_output =
- alu_op_i[2:0] == `ADDSUB ? sum :
- alu_op_i[2:0] == `XOR ? alu_in_1 ^ alu_in_2 :
- alu_op_i[2:0] == `OR ? alu_in_1 | alu_in_2 :
- alu_op_i[2:0] == `AND ? alu_in_1 & alu_in_2 :
- alu_op_i[2:0] == `SLL ? alu_in_2[6] == 1 ? 32'b0 : alu_in_1 << alu_in_2[5:0] :
- alu_op_i[2:0] == `SR ? right :
- alu_op_i[2:0] == `SLT ? {31'b0, sum[31]} :
- alu_op_i[2:0] == `SLTU ? (alu_in_1 < alu_in_2 ? 32'b1 : 32'b0) :
- 32'b0;
-endmodule
-