Verilog update

1 files changed, 30 insertions, 0 deletions

diff --git a/verilog/alu/v6/alu6.v b/verilog/alu/v6/alu6.v
new file mode 100644
index 0000000..2f0f00c
--- /dev/null
+++ b/verilog/alu/v6/alu6.v
@@ -0,0 +1,30 @@
+`default_nettype none
+`timescale 1us/1ns
+
+`include "aluOp.vh"
+
+module alu6
+(
+input wire [31:0] alu_in_1,
+input wire[31:0] alu_in_2,
+input wire[3:0] alu_op_i,
+output wire[31:0] alu_output
+);
+
+wire [31:0] complement2 = ~alu_in_2 + 1'b1;
+wire [31:0] sum = alu_in_1 + (alu_op_i[3] | (alu_op_i[1] & ~alu_op_i[0]) == 1'b1 ?  complement2 : alu_in_2);
+wire [31:0] right = alu_in_1 >> alu_in_2[5:0] | (alu_op_i[3] == 0 ? 32'b0 : 
+	(32'hFFFFFFFF << (alu_in_2[31] == 1'b1 ? 5'b0 : {~alu_in_2[4] , ~alu_in_2[3], ~alu_in_2[2], ~alu_in_2[1], ~alu_in_2[0]})));
+
+assign alu_output =
+	alu_op_i[2:0] == `ADDSUB ? sum :
+	alu_op_i[2:0] == `XOR ? alu_in_1 ^ alu_in_2 :
+	alu_op_i[2:0] == `OR ? alu_in_1 | alu_in_2 :
+	alu_op_i[2:0] == `AND ? alu_in_1 & alu_in_2 :
+	alu_op_i[2:0] == `SLL ? alu_in_2[6] == 1 ? 32'b0 : alu_in_1 << alu_in_2[5:0] :
+	alu_op_i[2:0] == `SR ? right :
+	alu_op_i[2:0] == `SLT ? {31'b0, sum[31]} :
+	alu_op_i[2:0] == `SLTU ? (alu_in_1 < alu_in_2 ? 32'b1 : 32'b0) :
+	32'b0;
+endmodule
+