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| author | Joshua Yun <jjyun4@illinois.edu> | 2023-08-28 14:42:23 -0500 |
|---|---|---|
| committer | Joshua Yun <jjyun4@illinois.edu> | 2023-08-28 14:42:23 -0500 |
| commit | c1fa3c36da28e9e947f6279329c47777f31fe7a2 (patch) | |
| tree | bd321c8e33200427b23bffe96c7c1bae90d8a044 /verilog/alu/v6/aluOp.vh | |
| parent | d069ea63cce08c0f5c8d7da7f8ab05115bd8d856 (diff) | |
| download | riscv-processor-inorder-master.tar.gz | |
Diffstat (limited to 'verilog/alu/v6/aluOp.vh')
| -rw-r--r-- | verilog/alu/v6/aluOp.vh | 14 |
1 files changed, 0 insertions, 14 deletions
diff --git a/verilog/alu/v6/aluOp.vh b/verilog/alu/v6/aluOp.vh deleted file mode 100644 index 0e8c41a..0000000 --- a/verilog/alu/v6/aluOp.vh +++ /dev/null @@ -1,14 +0,0 @@ -`ifndef ALU_OP -`define ALU_OP -// 1st bit that is no longer there == SUB/SRA/NONE -`define ADDSUB 3'b000 -`define XOR 3'b100 -`define OR 3'b110 -`define AND 3'b111 -`define SLL 3'b001 -`define SR 3'b101 -`define SLT 3'b010 -`define SLTU 3'b011 -`define NONE 3'b111 - -`endif |