Added new riscv processor design into git repoHEADmaster

1 files changed, 0 insertions, 42 deletions

diff --git a/verilog/alu/v6/shifter.v b/verilog/alu/v6/shifter.v
deleted file mode 100644
index 7030a1c..0000000
--- a/verilog/alu/v6/shifter.v
+++ /dev/null
@@ -1,42 +0,0 @@
-`default_nettype none
-`timescale 1us/1ns
-
-module rightshifter
-(
-	input wire [31:0] shift,
-	input wire [31:0] number,
-	output wire [31:0] shifted
-);
-
-always @ (*)
-begin
-	if (number[5] == 1'b1)
-	begin
-		shifted = {32{number[31]}};
-	end
-	else
-	begin
-		if (number[4] == 1'b1)
-		begin
-			shifted = {{16{number[31]}}, number[31:16]}
-		end
-		if (number[3] == 1'b1)
-		begin
-			shifted = {{8{number[31]}}, number[31:8]}
-		end
-		if (number[2] == 1'b1)
-		begin
-			shifted = {{4{number[31]}}, number[31:4]}
-		end
-		if (number[1] == 1'b1)
-		begin
-			shifted = {{2{number[31]}}, number[31:2]}
-		end
-		if (number[0] == 1'b1)
-		begin
-			shifted = {number[31], number[31:1]}
-		end
-	end
-end
-
-endmodule