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| author | Joshua Yun <jjyun4@illinois.edu> | 2023-08-28 14:42:23 -0500 |
|---|---|---|
| committer | Joshua Yun <jjyun4@illinois.edu> | 2023-08-28 14:42:23 -0500 |
| commit | c1fa3c36da28e9e947f6279329c47777f31fe7a2 (patch) | |
| tree | bd321c8e33200427b23bffe96c7c1bae90d8a044 /verilog/alu/v6/synth_alu6.v alu6.blif | |
| parent | d069ea63cce08c0f5c8d7da7f8ab05115bd8d856 (diff) | |
| download | riscv-processor-inorder-c1fa3c36da28e9e947f6279329c47777f31fe7a2.tar.gz | |
Diffstat (limited to 'verilog/alu/v6/synth_alu6.v alu6.blif')
| -rw-r--r-- | verilog/alu/v6/synth_alu6.v alu6.blif | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/verilog/alu/v6/synth_alu6.v alu6.blif b/verilog/alu/v6/synth_alu6.v alu6.blif deleted file mode 100644 index 8186d4c..0000000 --- a/verilog/alu/v6/synth_alu6.v alu6.blif +++ /dev/null @@ -1 +0,0 @@ -# Generated by Yosys 0.15+70 (git sha1 48d7a6c47, gcc 11.2.0 -march=x86-64 -mtune=generic -O2 -fno-plt -fexceptions -fstack-clash-protection -fcf-protection -fPIC -Os) |