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| author | joshua <joshua@joshuayun.com> | 2021-12-14 01:46:40 -0600 |
|---|---|---|
| committer | joshua <joshua@joshuayun.com> | 2021-12-14 01:46:40 -0600 |
| commit | 9dc6d7180438031d25daf6a68a3959c3cfa9312d (patch) | |
| tree | e7bcab090bf1872392c0ca40e6128269136d42be /verilog/alu_ops.vh | |
| download | riscv-processor-inorder-9dc6d7180438031d25daf6a68a3959c3cfa9312d.tar.gz | |
Initial Commit
Diffstat (limited to 'verilog/alu_ops.vh')
| -rw-r--r-- | verilog/alu_ops.vh | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/verilog/alu_ops.vh b/verilog/alu_ops.vh new file mode 100644 index 0000000..258e124 --- /dev/null +++ b/verilog/alu_ops.vh @@ -0,0 +1,14 @@ +`ifndef ALU_OP +`define ALU_OP +`define NONE 4'b0000 +`define SLL 4'b0001 +`define SRL 4'b0010 +`define SRA 4'b0011 +`define ADD 4'b0100 +`define SUB 4'b0110 +`define AND 4'b0111 +`define OR 4'b1000 +`define XOR 4'b1001 +`define SLTU 4'b1010 +`define SLT 4'b1011 +`endif |