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-rw-r--r--ddr3demo.pdfbin0 -> 2044510 bytes
-rw-r--r--instructions48
-rw-r--r--isa.pdfbin0 -> 1021610 bytes
-rw-r--r--isalist.pdfbin0 -> 557830 bytes
-rw-r--r--privileged.pdfbin0 -> 533858 bytes
-rw-r--r--ramcontroller.pdfbin0 -> 1475875 bytes
-rw-r--r--report/report.pdfbin0 -> 70125 bytes
-rw-r--r--report/report.tex180
-rw-r--r--riscv-card.pdfbin0 -> 121074 bytes
-rwxr-xr-xverilog/a.out202
-rw-r--r--verilog/alu_ops.vh14
-rw-r--r--verilog/bench_alu.v23
-rwxr-xr-xverilog/fpu/a.out688
-rwxr-xr-xverilog/fpu/compile4
-rw-r--r--verilog/fpu/exp_calc.v152
-rw-r--r--verilog/fpu/fpu.v71
-rw-r--r--verilog/fpu/fpu_2.v54
-rw-r--r--verilog/fpu/fpu_2.v.add.bak54
-rw-r--r--verilog/fpu/fpu_3.v36
-rw-r--r--verilog/fpu/fpu_bench.v58
-rw-r--r--verilog/riscv_alu.v39
21 files changed, 1623 insertions, 0 deletions
diff --git a/ddr3demo.pdf b/ddr3demo.pdf
new file mode 100644
index 0000000..24c9089
--- /dev/null
+++ b/ddr3demo.pdf
Binary files differ
diff --git a/instructions b/instructions
new file mode 100644
index 0000000..a2efe86
--- /dev/null
+++ b/instructions
@@ -0,0 +1,48 @@
+R-Type (Register to Register)
+add 0110011 000 0000000
+sub 0110011 000 0100000
+sll 0110011 001 0000000
+xor 0110011 100 0000000
+sri 0110011 101 0000000
+sra 0110011 101 0000000
+or 0110011 110 0000000
+and 0110011 111 0000000
+lr.d 0110011 011 0001000
+sc.d 0110011 011 0001100
+
+I-type Immediate and Load operations
+lb 0000011 000 N/A
+lh 0000011 001 N/A
+lw 0000011 010 N/A
+ld 0000011 011 N/A
+lbu 0000011 100 N/A
+lhu 0000011 101 N/A
+lwu 0000011 110 N/A
+addi 0010011 000 N/A
+slli 0010011 001 000000
+xori 0010011 100 N/A
+srli 0010011 101 000000
+srai 0010011 101 010000
+ori 0010011 110 N/A
+andi 0010011 111 N/A
+jalr 1100111 000 N/A
+
+S-type (Store)
+sb 0100011 000 N/A
+sh 0100011 001 N/A
+sw 0100011 010 N/A
+sd 0100011 111 N/A
+
+SB-type (Branches)
+beq 1100111 000 N/A
+bne 1100111 001 N/A
+blt 1100111 100 N/A
+bqe 1100111 101 N/A
+bltu 1100111 110 N/A
+bqeu 1100111 111 N/A
+
+U-type (Long immediate)
+lui 0110111 N/A N/A
+
+Unconditional Jumps
+UJ-type jalr 1101111 N/A N/A
diff --git a/isa.pdf b/isa.pdf
new file mode 100644
index 0000000..533c1cb
--- /dev/null
+++ b/isa.pdf
Binary files differ
diff --git a/isalist.pdf b/isalist.pdf
new file mode 100644
index 0000000..f5d2c53
--- /dev/null
+++ b/isalist.pdf
Binary files differ
diff --git a/privileged.pdf b/privileged.pdf
new file mode 100644
index 0000000..2303a01
--- /dev/null
+++ b/privileged.pdf
Binary files differ
diff --git a/ramcontroller.pdf b/ramcontroller.pdf
new file mode 100644
index 0000000..da8e3e5
--- /dev/null
+++ b/ramcontroller.pdf
Binary files differ
diff --git a/report/report.pdf b/report/report.pdf
new file mode 100644
index 0000000..d9f3a9e
--- /dev/null
+++ b/report/report.pdf
Binary files differ
diff --git a/report/report.tex b/report/report.tex
new file mode 100644
index 0000000..0daee27
--- /dev/null
+++ b/report/report.tex
@@ -0,0 +1,180 @@
+\documentclass[12pt]{article}
+
+\usepackage[margin=1in]{geometry}
+\setlength{\parindent}{0pt}
+
+\begin{document}
+\section {Introduction}
+\subsection{Purpose of the Project}
+\par
+The purpose of this project is to explore how floating point numbers are operated on in a CPU, as well as how different parts of the CPU signal each other to pass information and commands between different parts.
+Most FPGAs have their FPU blocks optimized where the code is no longer readable, and understanding how they are implemented at a fundamental level in verilog will also allow the group to write and conceptualize better verilog.
+With this project, the implementation will also require me to gain practical experience with either System Verilog or Verilog, allowing me to use those in other projects in the future.
+\subsection{Features of the Project}
+\par
+The two features of the current version of the project are:
+\begin{itemize}
+ \item All RISCV-I ALU operations
+ \item FPU Addition
+ \item FPU Subtraction (Incomplete)
+\end{itemize}
+\section{Design Overview}
+\par The main design of the FPU is a simple ALU which (currently) supports two operations of the floating point variety, i.e. adding and subtraction.
+The pipeline of the testing to building of the FPU is first it is written in Verilog, test benches are executed to verify its functionality, with a special focus on edge cases.
+All the verilog is then checked to make sure that it is synthesizeable, before it is then built onto the FPGA using Yosys and Nextpnr.
+\section{Implementation Details}
+\subsection{Floating point IEEE-754 Representation}
+\par Floating point notation in the IEEE standard is taking advantage of scientific notation to represent numbers both extremely large and small using the same number of bits in the same configuration.
+This is done by using the following representation:
+\begin{itemize}
+ \item 1 bit at the beginning to represent sign
+ \item 8 bits after to represent the exponent, which is the 8 bit value minus 127
+ \item 23 bit mantissa at the end, representing the actual value of the number.
+\end{itemize}
+
+An example number would be as follows:
+$0\_01111111\_11000000000000000000000$
+This is the number 1.75, since we have 0 bit 1, i.e. positive, 127 for the exponent, meaning $2^{127-127} = 2^0$, and a mantissa of 110000... when combined with a hidden bit, yields $1.11 * 2^0$ or $1.75$
+
+\subsection{Algorithm for addition and subtraction}
+\par Simply put, the algorithim is as follows:
+\begin{itemize}
+ \item{Pull both numbers' hidden bits in}
+ \item{Denormalize number with smaller exponent, i.e. make the two numbers have the same exponent}
+ \item{Negate numbers which are negative}
+ \item{Add or Subtract (Add two's complement) the numbers}
+ \item{Renormalize i.e. shift if there is a carry and add to the exp}
+ \item{Put the sign, new exponent and mantissa into the output}
+\end{itemize}
+\subsection{Implementation in Verilog}
+\par The implementation of the RISCV-I ALU was trivial, and only used the unoptimized verilog arithmetic elements, and so will not be included in this report. (If curious it will be on git.joshuayun.com along with the FPU).
+The FPU was implemented using only assign statements, as it is a combinational logic only circuit in most cases, however this does introduce much more complexity into the design, as only ternary operators can be used in assign statements which need choice logic.
+
+\subsection{Testbench}
+\par
+The testbench was quite naively implemented, with the group simply trying multiple test cases sequentially without a loop due to the fact that the bench was used mostly as a way to debug the output, rather than a true test of functionality: the code can be found in the appendix or on my git repository (soon @ git.joshuayun.com)
+
+\subsection{FPGA}
+\par The verilog was all synthesized and put onto the Orangecrab using the yosys nextpnr toolchain, however there was not sufficient time to test the true functionality of the FPU on an actual FPGA due to an inability for data to be taken out or display from the FPGA, nor could data be put into the FPGA.
+
+\section{Results}
+\par The verilog on the FPU in the icarus verilog simulator is passing all of the given tests, however it does not fully have NaN, infinity, nor zero functionality.
+However, more tests on niche cases, i.e. larger + smaller numbers and certain signed operations may be dysfunctional at the moment.
+
+\section{Problems and Challenges}
+\subsection{Design Problems}
+The only major issue with designing and planing out the mechanics of the FPU was the issue of not having the proper knowledge on how exactly to best implement these algorithms, especially when it came to try and deal with adding negative numbers or subtracting positive ones, as it was often not clear how to properly represent negative numbers internally in the FPU, as well as when then carry is used for determining sign or carrying the exponent higher.
+\subsection{Debugging}
+The major problem encountered in this project mostly dealt with understanding the actual algorithms at the lower levels that the FPUs use, as well as how they would be synthesized in verilog.
+Having a small amount of verilog experience meant that the second issue was mitigated, but still was a problem in that there were often many smaller mistakes that were difficult to find which significantly changed the output of the FPU.
+It was also difficult having consistent debugging information in the FPU at all times, mostly due to the fact that since the FPUs is a series of combinational logic with assign statements, internal displays could not be used on the ternary operators to determine whether the branching condition was correct or not.
+
+\section{Future Plans}
+The main future plan for this project is the first add most of the NaN and zero functionality to this FPU, as it is lacking even the most basic of operation support other than two non-zero integers.
+The next obvious step would then be to implement division and multiplication using the FPU, and this would most likely along with significant amounts of debugging be the completion of the FPU.
+Future plans will also include incoroporating this into a RISCV-I processor that I plan to design and synthesize onto an FPGA, along with enough modifications to the control logic and FPU to make it RISCV-IF compliant as well.
+\section{References}
+\begin{verbatim}
+Martin, R., 2021. Computer Organization and Design Unit 7: Floating Point.
+[online] Cis.upenn.edu. [Accessed 12 December 2021].
+\end{verbatim}
+
+\pagebreak
+\section{Appendix}
+\subsection{Verilog FPU}
+\begin{verbatim}
+`include "exp_calc.v"
+module fpu_2(
+ input wire add_not,
+ input wire[31:0] a_in, b_in,
+ output wire[31:0] out
+);
+
+wire[23:0] a_sig, b_sig, b_shft_sig, a_shft_sig, a_sign_sig, b_sign_sig;
+wire[24:0] sig_sum, sig_diff, sig_op, sig_final;
+wire[7:0] exp;
+wire[7:0] diff, neg_diff;
+wire same_sign;
+
+assign diff = a_in[30:23] - b_in[30:23];
+assign neg_diff = b_in[30:23] - a_in[30:23];
+assign exp = diff[7] ? b_in[30:23] : a_in[30:23];
+
+assign same_sign = ~(a_in[31] ^ b_in[31]);
+
+// Pull hidden bit into sig, if exp 0, no hidden bit
+assign a_sig = (|a_in[30:23] ? {1'b1, a_in[22:0]} : {1'b0, a_in[22:0]});
+assign b_sig = (|b_in[30:23] ? {1'b1, b_in[22:0]} : {1'b0, b_in[22:0]});
+
+assign a_shft_sig = (diff[7] ? a_sig >> neg_diff : a_sig);
+assign b_shft_sig = (diff[7] ? b_sig : b_sig >> diff);
+
+//2C Invert if Negative and not same signs
+assign a_sign_sig = same_sign ? a_shft_sig :
+(a_in[31] ? ~(a_shft_sig) + 24'b1 : a_shft_sig);
+assign b_sign_sig = same_sign ? b_shft_sig :
+(b_in[31] ? ~(b_shft_sig) + 24'b1 : b_shft_sig);
+
+//Adding
+assign sig_sum = a_sign_sig + b_sign_sig;
+/* assign sig_sum = a_shft_sig + b_shft_sig; */
+//Subtraction
+assign sig_diff = a_shft_sig + ~(b_shft_sig) + 25'b1;
+
+assign sig_op = add_not ? sig_diff : sig_sum;
+assign sig_final = sig_op[24] | same_sign ? sig_op : ~(sig_op) + 24'b1;
+
+
+// Assign exp and mantissa
+assign out[31] = a_shft_sig > b_shft_sig ? a_in[31] : b_in[31];
+assign out[30:23] = sig_sum[24] & same_sign ? exp + 8'b1 : (same_sign ? exp : exp);
+assign out[22:0] = sig_final[24] & same_sign ? sig_final[23:1] : sig_final[22:0];
+
+//assign out = {sig_sum, 7'b0};
+// assign out = {diff, neg_diff, 16'b0};
+/* assign out = {sig_op, 7'b0}; */
+
+endmodule
+\end{verbatim}
+
+\subsection{Verilog Testbench}
+\begin{verbatim}
+`timescale 1us/1ns
+
+`include "fpu_2.v"
+
+module fpu_bench;
+
+reg[31:0] input1, input2;
+reg add = 1'b1;
+wire[31:0] fpu_output;
+
+fpu_2 fpu0 (add,input1, input2, fpu_output);
+
+initial begin
+ input1=32'b00111111010000000000000000000000; // -.75
+ input2=32'b10111111110000000000000000000000; // -1.5
+ #5;
+ $display("\nSum: %16b + %16b\n = %16b",input1,input2,fpu_output);
+
+ input1=32'b00111110100000000000000000000000; //.25
+ input2=32'b00111111010000000000000000000000; // .75
+ #5;
+ $display("\nSum: %16b + %16b = %16b",input1,input2,fpu_output);
+
+ input1=32'b01000000000111001100110011001101; // 2.45
+ input2=32'b00111111001001100110011001100110; //.65
+ #5;
+ $display("\nSum: %16b + %16b\n = %16b",input1,input2,fpu_output);
+
+ input1=32'b01000000000111001100110011001101; // 2.45
+ input2=32'b10111111001001100110011001100110; //.65
+ #5;
+ $display("\nSum: %16b + %16b\n = %16b",input1[22:0],input2[22:0],fpu_output[31:8]);
+
+
+ $finish;
+end
+endmodule
+\end{verbatim}
+\end{document}
diff --git a/riscv-card.pdf b/riscv-card.pdf
new file mode 100644
index 0000000..be17bed
--- /dev/null
+++ b/riscv-card.pdf
Binary files differ
diff --git a/verilog/a.out b/verilog/a.out
new file mode 100755
index 0000000..77036bc
--- /dev/null
+++ b/verilog/a.out
@@ -0,0 +1,202 @@
+#! /usr/bin/vvp
+:ivl_version "11.0 (stable)" "(v11_0)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision - 9;
+:vpi_module "/usr/lib/ivl/system.vpi";
+:vpi_module "/usr/lib/ivl/vhdl_sys.vpi";
+:vpi_module "/usr/lib/ivl/vhdl_textio.vpi";
+:vpi_module "/usr/lib/ivl/v2005_math.vpi";
+:vpi_module "/usr/lib/ivl/va_math.vpi";
+S_0x5585f3becd70 .scope module, "bench_alu" "bench_alu" 2 6;
+ .timescale -6 -9;
+v0x5585f3c3e500_0 .net "alu_out", 31 0, L_0x5585f3c3e890; 1 drivers
+v0x5585f3c3e5e0_0 .var "input1", 31 0;
+v0x5585f3c3e680_0 .var "input2", 31 0;
+v0x5585f3c3e720_0 .var "op", 3 0;
+S_0x5585f3becf00 .scope module, "alu0" "riscv_alu" 2 12, 3 1 0, S_0x5585f3becd70;
+ .timescale -6 -9;
+ .port_info 0 /INPUT 32 "alu_in_1";
+ .port_info 1 /INPUT 32 "alu_in_2";
+ .port_info 2 /INPUT 4 "alu_op_i";
+ .port_info 3 /OUTPUT 32 "alu_output";
+L_0x5585f3c3e890 .functor BUFZ 32, v0x5585f3c3e3a0_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+v0x5585f3c29b30_0 .net/s "alu_in_1", 31 0, v0x5585f3c3e5e0_0; 1 drivers
+v0x5585f3c3dff0_0 .net "alu_in_2", 31 0, v0x5585f3c3e680_0; 1 drivers
+v0x5585f3c3e0d0_0 .net "alu_op_i", 3 0, v0x5585f3c3e720_0; 1 drivers
+v0x5585f3c3e190_0 .net "alu_output", 31 0, L_0x5585f3c3e890; alias, 1 drivers
+v0x5585f3c3e270_0 .net "sub_alu", 31 0, L_0x5585f3c3e7f0; 1 drivers
+v0x5585f3c3e3a0_0 .var "tmp_out", 31 0;
+E_0x5585f3c2a2f0 .event edge, v0x5585f3c3e0d0_0, v0x5585f3c29b30_0, v0x5585f3c3dff0_0, v0x5585f3c3e270_0;
+L_0x5585f3c3e7f0 .arith/sub 32, v0x5585f3c3e5e0_0, v0x5585f3c3e680_0;
+ .scope S_0x5585f3becf00;
+T_0 ;
+ %wait E_0x5585f3c2a2f0;
+ %load/vec4 v0x5585f3c3e0d0_0;
+ %dup/vec4;
+ %pushi/vec4 4, 0, 4;
+ %cmp/u;
+ %jmp/1 T_0.0, 6;
+ %dup/vec4;
+ %pushi/vec4 6, 0, 4;
+ %cmp/u;
+ %jmp/1 T_0.1, 6;
+ %dup/vec4;
+ %pushi/vec4 9, 0, 4;
+ %cmp/u;
+ %jmp/1 T_0.2, 6;
+ %dup/vec4;
+ %pushi/vec4 8, 0, 4;
+ %cmp/u;
+ %jmp/1 T_0.3, 6;
+ %dup/vec4;
+ %pushi/vec4 7, 0, 4;
+ %cmp/u;
+ %jmp/1 T_0.4, 6;
+ %dup/vec4;
+ %pushi/vec4 1, 0, 4;
+ %cmp/u;
+ %jmp/1 T_0.5, 6;
+ %dup/vec4;
+ %pushi/vec4 2, 0, 4;
+ %cmp/u;
+ %jmp/1 T_0.6, 6;
+ %dup/vec4;
+ %pushi/vec4 3, 0, 4;
+ %cmp/u;
+ %jmp/1 T_0.7, 6;
+ %dup/vec4;
+ %pushi/vec4 11, 0, 4;
+ %cmp/u;
+ %jmp/1 T_0.8, 6;
+ %dup/vec4;
+ %pushi/vec4 10, 0, 4;
+ %cmp/u;
+ %jmp/1 T_0.9, 6;
+ %load/vec4 v0x5585f3c29b30_0;
+ %store/vec4 v0x5585f3c3e3a0_0, 0, 32;
+ %jmp T_0.11;
+T_0.0 ;
+ %load/vec4 v0x5585f3c29b30_0;
+ %load/vec4 v0x5585f3c3dff0_0;
+ %add;
+ %store/vec4 v0x5585f3c3e3a0_0, 0, 32;
+ %jmp T_0.11;
+T_0.1 ;
+ %load/vec4 v0x5585f3c3e270_0;
+ %store/vec4 v0x5585f3c3e3a0_0, 0, 32;
+ %jmp T_0.11;
+T_0.2 ;
+ %load/vec4 v0x5585f3c29b30_0;
+ %load/vec4 v0x5585f3c3dff0_0;
+ %xor;
+ %store/vec4 v0x5585f3c3e3a0_0, 0, 32;
+ %jmp T_0.11;
+T_0.3 ;
+ %load/vec4 v0x5585f3c29b30_0;
+ %load/vec4 v0x5585f3c3dff0_0;
+ %or;
+ %store/vec4 v0x5585f3c3e3a0_0, 0, 32;
+ %jmp T_0.11;
+T_0.4 ;
+ %load/vec4 v0x5585f3c29b30_0;
+ %load/vec4 v0x5585f3c3dff0_0;
+ %and;
+ %store/vec4 v0x5585f3c3e3a0_0, 0, 32;
+ %jmp T_0.11;
+T_0.5 ;
+ %load/vec4 v0x5585f3c29b30_0;
+ %ix/getv 4, v0x5585f3c3dff0_0;
+ %shiftl 4;
+ %store/vec4 v0x5585f3c3e3a0_0, 0, 32;
+ %jmp T_0.11;
+T_0.6 ;
+ %load/vec4 v0x5585f3c29b30_0;
+ %ix/getv 4, v0x5585f3c3dff0_0;
+ %shiftr 4;
+ %store/vec4 v0x5585f3c3e3a0_0, 0, 32;
+ %jmp T_0.11;
+T_0.7 ;
+ %load/vec4 v0x5585f3c29b30_0;
+ %ix/getv 4, v0x5585f3c3dff0_0;
+ %shiftr/s 4;
+ %store/vec4 v0x5585f3c3e3a0_0, 0, 32;
+ %jmp T_0.11;
+T_0.8 ;
+ %load/vec4 v0x5585f3c29b30_0;
+ %load/vec4 v0x5585f3c3dff0_0;
+ %cmp/u;
+ %flag_mov 8, 5;
+ %jmp/0 T_0.12, 8;
+ %pushi/vec4 1, 0, 32;
+ %jmp/1 T_0.13, 8;
+T_0.12 ; End of true expr.
+ %pushi/vec4 0, 0, 32;
+ %jmp/0 T_0.13, 8;
+ ; End of false expr.
+ %blend;
+T_0.13;
+ %store/vec4 v0x5585f3c3e3a0_0, 0, 32;
+ %jmp T_0.11;
+T_0.9 ;
+ %load/vec4 v0x5585f3c29b30_0;
+ %parti/s 1, 31, 6;
+ %load/vec4 v0x5585f3c3dff0_0;
+ %parti/s 1, 31, 6;
+ %cmp/ne;
+ %jmp/0xz T_0.14, 4;
+ %load/vec4 v0x5585f3c29b30_0;
+ %parti/s 1, 31, 6;
+ %flag_set/vec4 8;
+ %jmp/0 T_0.16, 8;
+ %pushi/vec4 1, 0, 32;
+ %jmp/1 T_0.17, 8;
+T_0.16 ; End of true expr.
+ %pushi/vec4 0, 0, 32;
+ %jmp/0 T_0.17, 8;
+ ; End of false expr.
+ %blend;
+T_0.17;
+ %store/vec4 v0x5585f3c3e3a0_0, 0, 32;
+ %jmp T_0.15;
+T_0.14 ;
+ %load/vec4 v0x5585f3c3e270_0;
+ %parti/s 1, 31, 6;
+ %flag_set/vec4 8;
+ %jmp/0 T_0.18, 8;
+ %pushi/vec4 1, 0, 32;
+ %jmp/1 T_0.19, 8;
+T_0.18 ; End of true expr.
+ %pushi/vec4 0, 0, 32;
+ %jmp/0 T_0.19, 8;
+ ; End of false expr.
+ %blend;
+T_0.19;
+ %store/vec4 v0x5585f3c3e3a0_0, 0, 32;
+T_0.15 ;
+ %jmp T_0.11;
+T_0.11 ;
+ %pop/vec4 1;
+ %jmp T_0;
+ .thread T_0, $push;
+ .scope S_0x5585f3becd70;
+T_1 ;
+ %pushi/vec4 11, 0, 4;
+ %store/vec4 v0x5585f3c3e720_0, 0, 4;
+ %pushi/vec4 10, 0, 32;
+ %store/vec4 v0x5585f3c3e5e0_0, 0, 32;
+ %pushi/vec4 13, 0, 32;
+ %store/vec4 v0x5585f3c3e680_0, 0, 32;
+ %delay 50000, 0;
+ %load/vec4 v0x5585f3c3e5e0_0;
+ %load/vec4 v0x5585f3c3e680_0;
+ %load/vec4 v0x5585f3c3e500_0;
+ %vpi_call 2 19 "$display", "\012ALU OP AND: %d %16b + %d %16b = %d %b", S<2,vec4,s32>, v0x5585f3c3e5e0_0, S<1,vec4,s32>, v0x5585f3c3e680_0, S<0,vec4,s32>, v0x5585f3c3e500_0 {3 0 0};
+ %vpi_call 2 20 "$finish" {0 0 0};
+ %end;
+ .thread T_1;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+ "N/A";
+ "<interactive>";
+ "bench_alu.v";
+ "./riscv_alu.v";
diff --git a/verilog/alu_ops.vh b/verilog/alu_ops.vh
new file mode 100644
index 0000000..258e124
--- /dev/null
+++ b/verilog/alu_ops.vh
@@ -0,0 +1,14 @@
+`ifndef ALU_OP
+`define ALU_OP
+`define NONE 4'b0000
+`define SLL 4'b0001
+`define SRL 4'b0010
+`define SRA 4'b0011
+`define ADD 4'b0100
+`define SUB 4'b0110
+`define AND 4'b0111
+`define OR 4'b1000
+`define XOR 4'b1001
+`define SLTU 4'b1010
+`define SLT 4'b1011
+`endif
diff --git a/verilog/bench_alu.v b/verilog/bench_alu.v
new file mode 100644
index 0000000..9c0140c
--- /dev/null
+++ b/verilog/bench_alu.v
@@ -0,0 +1,23 @@
+`timescale 1us/1ns
+
+`include "riscv_alu.v"
+`include "alu_ops.vh"
+
+module bench_alu;
+
+reg [3:0] op;
+reg [31:0] input1, input2;
+wire [31:0] alu_out;
+
+riscv_alu alu0 (input1, input2, op, alu_out);
+
+initial begin
+ op=`SLT;
+ input1=32'hA;
+ input2=32'hD;
+ #50
+ $display("\nALU OP AND: %d %16b + %d %16b = %d %b", $signed(input1), input1, $signed(input2), input2, $signed(alu_out), alu_out);
+ $finish;
+end
+
+endmodule
diff --git a/verilog/fpu/a.out b/verilog/fpu/a.out
new file mode 100755
index 0000000..6b5c150
--- /dev/null
+++ b/verilog/fpu/a.out
@@ -0,0 +1,688 @@
+#! /usr/bin/vvp
+:ivl_version "11.0 (stable)" "(v11_0)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision - 9;
+:vpi_module "/usr/lib/ivl/system.vpi";
+:vpi_module "/usr/lib/ivl/vhdl_sys.vpi";
+:vpi_module "/usr/lib/ivl/vhdl_textio.vpi";
+:vpi_module "/usr/lib/ivl/v2005_math.vpi";
+:vpi_module "/usr/lib/ivl/va_math.vpi";
+S_0x5592cfc9f490 .scope module, "fpu_bench" "fpu_bench" 2 5;
+ .timescale -6 -9;
+v0x5592cfd06280_0 .var "add", 0 0;
+v0x5592cfd06340_0 .net "fpu_output", 31 0, L_0x5592cfd1eeb0; 1 drivers
+v0x5592cfd06410_0 .var "input1", 31 0;
+v0x5592cfd06510_0 .var "input2", 31 0;
+S_0x5592cfc9da90 .scope module, "fpu0" "fpu_2" 2 11, 3 2 0, S_0x5592cfc9f490;
+ .timescale -6 -9;
+ .port_info 0 /INPUT 1 "add_not";
+ .port_info 1 /INPUT 32 "a_in";
+ .port_info 2 /INPUT 32 "b_in";
+ .port_info 3 /OUTPUT 32 "out";
+L_0x5592cfd06840 .functor XOR 1, L_0x5592cfd07040, L_0x5592cfd070e0, C4<0>, C4<0>;
+L_0x5592cfd07290 .functor NOT 1, L_0x5592cfd06840, C4<0>, C4<0>, C4<0>;
+L_0x5592cfd07180 .functor NOT 24, L_0x5592cfd088a0, C4<000000000000000000000000>, C4<000000000000000000000000>, C4<000000000000000000000000>;
+L_0x5592cfd19060 .functor NOT 24, L_0x5592cfd08c20, C4<000000000000000000000000>, C4<000000000000000000000000>, C4<000000000000000000000000>;
+L_0x5592cfd196e0 .functor NOT 25, L_0x5592cfd1a420, C4<0000000000000000000000000>, C4<0000000000000000000000000>, C4<0000000000000000000000000>;
+L_0x5592cfd1a5b0 .functor OR 1, L_0x5592cfd1aca0, L_0x5592cfd07290, C4<0>, C4<0>;
+L_0x5592cfd1aeb0 .functor NOT 25, L_0x5592cfd1a980, C4<0000000000000000000000000>, C4<0000000000000000000000000>, C4<0000000000000000000000000>;
+L_0x5592cfd1afc0 .functor OR 1, L_0x5592cfd1b620, L_0x5592cfd1b870, C4<0>, C4<0>;
+L_0x5592cfd1ba00 .functor AND 1, v0x5592cfd06280_0, L_0x5592cfd1afc0, C4<1>, C4<1>;
+L_0x5592cfd1bdc0 .functor XOR 1, L_0x5592cfd1bac0, L_0x5592cfd1bd20, C4<0>, C4<0>;
+L_0x5592cfd1bf30 .functor XOR 1, L_0x5592cfd1bdc0, v0x5592cfd06280_0, C4<0>, C4<0>;
+L_0x5592cfd1e3a0 .functor AND 1, L_0x5592cfd1e0b0, L_0x5592cfd07290, C4<1>, C4<1>;
+L_0x5592cfd1e570 .functor AND 1, L_0x5592cfd1fe90, L_0x5592cfd07290, C4<1>, C4<1>;
+v0x5592cfcff120_0 .net *"_ivl_1", 7 0, L_0x5592cfd065e0; 1 drivers
+v0x5592cfcff220_0 .net *"_ivl_100", 24 0, L_0x5592cfd19c60; 1 drivers
+L_0x7ff85d2be1c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0x5592cfcff300_0 .net *"_ivl_103", 0 0, L_0x7ff85d2be1c8; 1 drivers
+v0x5592cfcff3c0_0 .net *"_ivl_104", 24 0, L_0x5592cfd19d50; 1 drivers
+L_0x7ff85d2be210 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0x5592cfcff4a0_0 .net *"_ivl_107", 0 0, L_0x7ff85d2be210; 1 drivers
+v0x5592cfcff5d0_0 .net *"_ivl_110", 24 0, L_0x5592cfd1a130; 1 drivers
+L_0x7ff85d2be258 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0x5592cfcff6b0_0 .net *"_ivl_113", 0 0, L_0x7ff85d2be258; 1 drivers
+v0x5592cfcff790_0 .net *"_ivl_114", 24 0, L_0x5592cfd1a420; 1 drivers
+L_0x7ff85d2be2a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0x5592cfcff870_0 .net *"_ivl_117", 0 0, L_0x7ff85d2be2a0; 1 drivers
+v0x5592cfcff950_0 .net *"_ivl_118", 24 0, L_0x5592cfd196e0; 1 drivers
+v0x5592cfcffa30_0 .net *"_ivl_120", 24 0, L_0x5592cfd1a510; 1 drivers
+L_0x7ff85d2be2e8 .functor BUFT 1, C4<0000000000000000000000001>, C4<0>, C4<0>, C4<0>;
+v0x5592cfcffb10_0 .net/2u *"_ivl_122", 24 0, L_0x7ff85d2be2e8; 1 drivers
+v0x5592cfcffbf0_0 .net *"_ivl_129", 0 0, L_0x5592cfd1aca0; 1 drivers
+v0x5592cfcffcd0_0 .net *"_ivl_13", 0 0, L_0x5592cfd06c70; 1 drivers
+v0x5592cfcffdb0_0 .net *"_ivl_130", 0 0, L_0x5592cfd1a5b0; 1 drivers
+v0x5592cfcffe90_0 .net *"_ivl_132", 24 0, L_0x5592cfd1aeb0; 1 drivers
+L_0x7ff85d2be330 .functor BUFT 1, C4<0000000000000000000000001>, C4<0>, C4<0>, C4<0>;
+v0x5592cfcfff70_0 .net/2u *"_ivl_134", 24 0, L_0x7ff85d2be330; 1 drivers
+v0x5592cfd00050_0 .net *"_ivl_136", 24 0, L_0x5592cfd1af20; 1 drivers
+v0x5592cfd00130_0 .net *"_ivl_143", 0 0, L_0x5592cfd1b620; 1 drivers
+v0x5592cfd00210_0 .net *"_ivl_145", 0 0, L_0x5592cfd1b870; 1 drivers
+v0x5592cfd002f0_0 .net *"_ivl_146", 0 0, L_0x5592cfd1afc0; 1 drivers
+v0x5592cfd003d0_0 .net *"_ivl_148", 0 0, L_0x5592cfd1ba00; 1 drivers
+v0x5592cfd004b0_0 .net *"_ivl_15", 7 0, L_0x5592cfd06d60; 1 drivers
+v0x5592cfd00590_0 .net *"_ivl_151", 0 0, L_0x5592cfd1bac0; 1 drivers
+v0x5592cfd00670_0 .net *"_ivl_153", 0 0, L_0x5592cfd1bd20; 1 drivers
+v0x5592cfd00750_0 .net *"_ivl_154", 0 0, L_0x5592cfd1bdc0; 1 drivers
+v0x5592cfd00830_0 .net *"_ivl_156", 0 0, L_0x5592cfd1bf30; 1 drivers
+v0x5592cfd00910_0 .net *"_ivl_158", 0 0, L_0x5592cfd1c030; 1 drivers
+L_0x7ff85d2be3c0 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>;
+v0x5592cfd009d0_0 .net/2u *"_ivl_160", 1 0, L_0x7ff85d2be3c0; 1 drivers
+L_0x7ff85d2be408 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
+v0x5592cfd00ab0_0 .net/2u *"_ivl_162", 1 0, L_0x7ff85d2be408; 1 drivers
+v0x5592cfd00b90_0 .net *"_ivl_164", 1 0, L_0x5592cfd1c2a0; 1 drivers
+v0x5592cfd00c70_0 .net *"_ivl_167", 0 0, L_0x5592cfd1c3e0; 1 drivers
+v0x5592cfd00d50_0 .net *"_ivl_168", 1 0, L_0x5592cfd1c660; 1 drivers
+v0x5592cfd00e30_0 .net *"_ivl_17", 7 0, L_0x5592cfd06e50; 1 drivers
+L_0x7ff85d2be450 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0x5592cfd00f10_0 .net *"_ivl_171", 0 0, L_0x7ff85d2be450; 1 drivers
+v0x5592cfd00ff0_0 .net *"_ivl_172", 1 0, L_0x5592cfd1c7a0; 1 drivers
+v0x5592cfd010d0_0 .net *"_ivl_174", 0 0, L_0x5592cfd1cb20; 1 drivers
+v0x5592cfd01190_0 .net *"_ivl_177", 0 0, L_0x5592cfd1cbc0; 1 drivers
+v0x5592cfd01270_0 .net *"_ivl_178", 1 0, L_0x5592cfd1ce60; 1 drivers
+L_0x7ff85d2be498 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0x5592cfd01350_0 .net *"_ivl_181", 0 0, L_0x7ff85d2be498; 1 drivers
+v0x5592cfd01430_0 .net *"_ivl_183", 0 0, L_0x5592cfd1cfa0; 1 drivers
+v0x5592cfd01510_0 .net *"_ivl_184", 1 0, L_0x5592cfd1d250; 1 drivers
+L_0x7ff85d2be4e0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0x5592cfd015f0_0 .net *"_ivl_187", 0 0, L_0x7ff85d2be4e0; 1 drivers
+v0x5592cfd016d0_0 .net *"_ivl_188", 1 0, L_0x5592cfd1d390; 1 drivers
+v0x5592cfd017b0_0 .net *"_ivl_190", 1 0, L_0x5592cfd1d740; 1 drivers
+v0x5592cfd01890_0 .net *"_ivl_193", 0 0, L_0x5592cfd1d8d0; 1 drivers
+v0x5592cfd01970_0 .net *"_ivl_197", 0 0, L_0x5592cfd1dbf0; 1 drivers
+v0x5592cfd01a50_0 .net *"_ivl_198", 7 0, L_0x5592cfd1dce0; 1 drivers
+v0x5592cfd01b30_0 .net *"_ivl_200", 7 0, L_0x5592cfd1e010; 1 drivers
+v0x5592cfd01c10_0 .net *"_ivl_203", 0 0, L_0x5592cfd1e0b0; 1 drivers
+v0x5592cfd01cf0_0 .net *"_ivl_204", 0 0, L_0x5592cfd1e3a0; 1 drivers
+L_0x7ff85d2be528 .functor BUFT 1, C4<00000001>, C4<0>, C4<0>, C4<0>;
+v0x5592cfd01dd0_0 .net/2u *"_ivl_206", 7 0, L_0x7ff85d2be528; 1 drivers
+v0x5592cfd01eb0_0 .net *"_ivl_208", 7 0, L_0x5592cfd1e4d0; 1 drivers
+v0x5592cfd01f90_0 .net *"_ivl_21", 0 0, L_0x5592cfd07040; 1 drivers
+v0x5592cfd02070_0 .net *"_ivl_210", 7 0, L_0x5592cfd1e630; 1 drivers
+v0x5592cfd02150_0 .net *"_ivl_212", 7 0, L_0x5592cfd1e9c0; 1 drivers
+v0x5592cfd02230_0 .net *"_ivl_214", 7 0, L_0x5592cfd1eb00; 1 drivers
+v0x5592cfd02310_0 .net *"_ivl_220", 22 0, L_0x5592cfd1f040; 1 drivers
+v0x5592cfd023f0_0 .net *"_ivl_222", 0 0, L_0x5592cfd1f360; 1 drivers
+v0x5592cfd024d0_0 .net *"_ivl_224", 22 0, L_0x5592cfd1f490; 1 drivers
+v0x5592cfd025b0_0 .net *"_ivl_226", 22 0, L_0x5592cfd1f7c0; 1 drivers
+v0x5592cfd02690_0 .net *"_ivl_227", 22 0, L_0x5592cfd1f860; 1 drivers
+v0x5592cfd02770_0 .net *"_ivl_229", 22 0, L_0x5592cfd1fc40; 1 drivers
+v0x5592cfd02850_0 .net *"_ivl_23", 0 0, L_0x5592cfd070e0; 1 drivers
+v0x5592cfd02930_0 .net *"_ivl_232", 0 0, L_0x5592cfd1fe90; 1 drivers
+v0x5592cfd02e20_0 .net *"_ivl_233", 0 0, L_0x5592cfd1e570; 1 drivers
+v0x5592cfd02f00_0 .net *"_ivl_236", 22 0, L_0x5592cfd201e0; 1 drivers
+v0x5592cfd02fe0_0 .net *"_ivl_238", 22 0, L_0x5592cfd20280; 1 drivers
+v0x5592cfd030c0_0 .net *"_ivl_24", 0 0, L_0x5592cfd06840; 1 drivers
+v0x5592cfd031a0_0 .net *"_ivl_240", 22 0, L_0x5592cfd205e0; 1 drivers
+v0x5592cfd03280_0 .net *"_ivl_241", 22 0, L_0x5592cfd20680; 1 drivers
+v0x5592cfd03360_0 .net *"_ivl_243", 22 0, L_0x5592cfd20a90; 1 drivers
+v0x5592cfd03440_0 .net *"_ivl_245", 22 0, L_0x5592cfd20c20; 1 drivers
+v0x5592cfd03520_0 .net *"_ivl_29", 7 0, L_0x5592cfd07350; 1 drivers
+v0x5592cfd03600_0 .net *"_ivl_3", 7 0, L_0x5592cfd066b0; 1 drivers
+v0x5592cfd036e0_0 .net *"_ivl_31", 0 0, L_0x5592cfd073f0; 1 drivers
+L_0x7ff85d2be018 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0x5592cfd037a0_0 .net/2u *"_ivl_32", 0 0, L_0x7ff85d2be018; 1 drivers
+v0x5592cfd03880_0 .net *"_ivl_35", 22 0, L_0x5592cfd07560; 1 drivers
+v0x5592cfd03960_0 .net *"_ivl_36", 23 0, L_0x5592cfd07600; 1 drivers
+L_0x7ff85d2be060 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0x5592cfd03a40_0 .net/2u *"_ivl_38", 0 0, L_0x7ff85d2be060; 1 drivers
+v0x5592cfd03b20_0 .net *"_ivl_41", 22 0, L_0x5592cfd077d0; 1 drivers
+v0x5592cfd03c00_0 .net *"_ivl_42", 23 0, L_0x5592cfd07870; 1 drivers
+v0x5592cfd03ce0_0 .net *"_ivl_47", 7 0, L_0x5592cfd07c10; 1 drivers
+v0x5592cfd03dc0_0 .net *"_ivl_49", 0 0, L_0x5592cfd079e0; 1 drivers
+L_0x7ff85d2be0a8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
+v0x5592cfd03e80_0 .net/2u *"_ivl_50", 0 0, L_0x7ff85d2be0a8; 1 drivers
+v0x5592cfd03f60_0 .net *"_ivl_53", 22 0, L_0x5592cfd07db0; 1 drivers
+v0x5592cfd04040_0 .net *"_ivl_54", 23 0, L_0x5592cfd07f10; 1 drivers
+L_0x7ff85d2be0f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0x5592cfd04120_0 .net/2u *"_ivl_56", 0 0, L_0x7ff85d2be0f0; 1 drivers
+v0x5592cfd04200_0 .net *"_ivl_59", 22 0, L_0x5592cfd08080; 1 drivers
+v0x5592cfd042e0_0 .net *"_ivl_60", 23 0, L_0x5592cfd081f0; 1 drivers
+v0x5592cfd043c0_0 .net *"_ivl_65", 0 0, L_0x5592cfd085d0; 1 drivers
+v0x5592cfd044a0_0 .net *"_ivl_66", 23 0, L_0x5592cfd08670; 1 drivers
+v0x5592cfd04580_0 .net *"_ivl_7", 7 0, L_0x5592cfd06950; 1 drivers
+v0x5592cfd04660_0 .net *"_ivl_71", 0 0, L_0x5592cfd089e0; 1 drivers
+v0x5592cfd04740_0 .net *"_ivl_72", 23 0, L_0x5592cfd08b80; 1 drivers
+v0x5592cfd04820_0 .net *"_ivl_77", 0 0, L_0x5592cfd08e70; 1 drivers
+v0x5592cfd04900_0 .net *"_ivl_78", 23 0, L_0x5592cfd07180; 1 drivers
+L_0x7ff85d2be138 .functor BUFT 1, C4<000000000000000000000001>, C4<0>, C4<0>, C4<0>;
+v0x5592cfd049e0_0 .net/2u *"_ivl_80", 23 0, L_0x7ff85d2be138; 1 drivers
+v0x5592cfd04ac0_0 .net *"_ivl_82", 23 0, L_0x5592cfd18fc0; 1 drivers
+v0x5592cfd04ba0_0 .net *"_ivl_84", 23 0, L_0x5592cfd19290; 1 drivers
+v0x5592cfd04c80_0 .net *"_ivl_89", 0 0, L_0x5592cfd195a0; 1 drivers
+v0x5592cfd04d60_0 .net *"_ivl_9", 7 0, L_0x5592cfd06a20; 1 drivers
+v0x5592cfd04e40_0 .net *"_ivl_90", 23 0, L_0x5592cfd19060; 1 drivers
+L_0x7ff85d2be180 .functor BUFT 1, C4<000000000000000000000001>, C4<0>, C4<0>, C4<0>;
+v0x5592cfd04f20_0 .net/2u *"_ivl_92", 23 0, L_0x7ff85d2be180; 1 drivers
+v0x5592cfd05000_0 .net *"_ivl_94", 23 0, L_0x5592cfd19640; 1 drivers
+v0x5592cfd050e0_0 .net *"_ivl_96", 23 0, L_0x5592cfd198e0; 1 drivers
+v0x5592cfd051c0_0 .net "a_in", 31 0, v0x5592cfd06410_0; 1 drivers
+v0x5592cfd052a0_0 .net "a_shft_sig", 23 0, L_0x5592cfd088a0; 1 drivers
+v0x5592cfd05380_0 .net "a_sig", 23 0, L_0x5592cfd07a80; 1 drivers
+v0x5592cfd05460_0 .net "a_sign_sig", 23 0, L_0x5592cfd193d0; 1 drivers
+v0x5592cfd05540_0 .net "add_not", 0 0, v0x5592cfd06280_0; 1 drivers
+v0x5592cfd05600_0 .net "b_in", 31 0, v0x5592cfd06510_0; 1 drivers
+v0x5592cfd056e0_0 .net "b_shft_sig", 23 0, L_0x5592cfd08c20; 1 drivers
+v0x5592cfd057c0_0 .net "b_sig", 23 0, L_0x5592cfd08360; 1 drivers
+v0x5592cfd058a0_0 .net "b_sign_sig", 23 0, L_0x5592cfd19a20; 1 drivers
+v0x5592cfd05980_0 .net "diff", 7 0, L_0x5592cfd067a0; 1 drivers
+v0x5592cfd05a60_0 .net "exp", 7 0, L_0x5592cfd06ef0; 1 drivers
+v0x5592cfd05b20_0 .net "exp_diff", 7 0, L_0x5592cfd1b4e0; 1 drivers
+v0x5592cfd05bc0_0 .net "neg_diff", 7 0, L_0x5592cfd06ac0; 1 drivers
+v0x5592cfd05c80_0 .net "out", 31 0, L_0x5592cfd1eeb0; alias, 1 drivers
+v0x5592cfd05d60_0 .net "same_sign", 0 0, L_0x5592cfd07290; 1 drivers
+v0x5592cfd05e20_0 .net "sig_diff", 24 0, L_0x5592cfd1a840; 1 drivers
+v0x5592cfd05f00_0 .net "sig_diff_final", 24 0, v0x5592cfcfec10_0; 1 drivers
+v0x5592cfd05fc0_0 .net "sig_final", 24 0, L_0x5592cfd1b220; 1 drivers
+v0x5592cfd06060_0 .net "sig_op", 24 0, L_0x5592cfd1a980; 1 drivers
+v0x5592cfd06120_0 .net "sig_sum", 24 0, L_0x5592cfd19ff0; 1 drivers
+L_0x5592cfd065e0 .part v0x5592cfd06410_0, 23, 8;
+L_0x5592cfd066b0 .part v0x5592cfd06510_0, 23, 8;
+L_0x5592cfd067a0 .arith/sub 8, L_0x5592cfd065e0, L_0x5592cfd066b0;
+L_0x5592cfd06950 .part v0x5592cfd06510_0, 23, 8;
+L_0x5592cfd06a20 .part v0x5592cfd06410_0, 23, 8;
+L_0x5592cfd06ac0 .arith/sub 8, L_0x5592cfd06950, L_0x5592cfd06a20;
+L_0x5592cfd06c70 .part L_0x5592cfd067a0, 7, 1;
+L_0x5592cfd06d60 .part v0x5592cfd06510_0, 23, 8;
+L_0x5592cfd06e50 .part v0x5592cfd06410_0, 23, 8;
+L_0x5592cfd06ef0 .functor MUXZ 8, L_0x5592cfd06e50, L_0x5592cfd06d60, L_0x5592cfd06c70, C4<>;
+L_0x5592cfd07040 .part v0x5592cfd06410_0, 31, 1;
+L_0x5592cfd070e0 .part v0x5592cfd06510_0, 31, 1;
+L_0x5592cfd07350 .part v0x5592cfd06410_0, 23, 8;
+L_0x5592cfd073f0 .reduce/or L_0x5592cfd07350;
+L_0x5592cfd07560 .part v0x5592cfd06410_0, 0, 23;
+L_0x5592cfd07600 .concat [ 23 1 0 0], L_0x5592cfd07560, L_0x7ff85d2be018;
+L_0x5592cfd077d0 .part v0x5592cfd06410_0, 0, 23;
+L_0x5592cfd07870 .concat [ 23 1 0 0], L_0x5592cfd077d0, L_0x7ff85d2be060;
+L_0x5592cfd07a80 .functor MUXZ 24, L_0x5592cfd07870, L_0x5592cfd07600, L_0x5592cfd073f0, C4<>;
+L_0x5592cfd07c10 .part v0x5592cfd06510_0, 23, 8;
+L_0x5592cfd079e0 .reduce/or L_0x5592cfd07c10;
+L_0x5592cfd07db0 .part v0x5592cfd06510_0, 0, 23;
+L_0x5592cfd07f10 .concat [ 23 1 0 0], L_0x5592cfd07db0, L_0x7ff85d2be0a8;
+L_0x5592cfd08080 .part v0x5592cfd06510_0, 0, 23;
+L_0x5592cfd081f0 .concat [ 23 1 0 0], L_0x5592cfd08080, L_0x7ff85d2be0f0;
+L_0x5592cfd08360 .functor MUXZ 24, L_0x5592cfd081f0, L_0x5592cfd07f10, L_0x5592cfd079e0, C4<>;
+L_0x5592cfd085d0 .part L_0x5592cfd067a0, 7, 1;
+L_0x5592cfd08670 .shift/r 24, L_0x5592cfd07a80, L_0x5592cfd06ac0;
+L_0x5592cfd088a0 .functor MUXZ 24, L_0x5592cfd07a80, L_0x5592cfd08670, L_0x5592cfd085d0, C4<>;
+L_0x5592cfd089e0 .part L_0x5592cfd067a0, 7, 1;
+L_0x5592cfd08b80 .shift/r 24, L_0x5592cfd08360, L_0x5592cfd067a0;
+L_0x5592cfd08c20 .functor MUXZ 24, L_0x5592cfd08b80, L_0x5592cfd08360, L_0x5592cfd089e0, C4<>;
+L_0x5592cfd08e70 .part v0x5592cfd06410_0, 31, 1;
+L_0x5592cfd18fc0 .arith/sum 24, L_0x5592cfd07180, L_0x7ff85d2be138;
+L_0x5592cfd19290 .functor MUXZ 24, L_0x5592cfd088a0, L_0x5592cfd18fc0, L_0x5592cfd08e70, C4<>;
+L_0x5592cfd193d0 .functor MUXZ 24, L_0x5592cfd19290, L_0x5592cfd088a0, L_0x5592cfd07290, C4<>;
+L_0x5592cfd195a0 .part v0x5592cfd06510_0, 31, 1;
+L_0x5592cfd19640 .arith/sum 24, L_0x5592cfd19060, L_0x7ff85d2be180;
+L_0x5592cfd198e0 .functor MUXZ 24, L_0x5592cfd08c20, L_0x5592cfd19640, L_0x5592cfd195a0, C4<>;
+L_0x5592cfd19a20 .functor MUXZ 24, L_0x5592cfd198e0, L_0x5592cfd08c20, L_0x5592cfd07290, C4<>;
+L_0x5592cfd19c60 .concat [ 24 1 0 0], L_0x5592cfd193d0, L_0x7ff85d2be1c8;
+L_0x5592cfd19d50 .concat [ 24 1 0 0], L_0x5592cfd19a20, L_0x7ff85d2be210;
+L_0x5592cfd19ff0 .arith/sum 25, L_0x5592cfd19c60, L_0x5592cfd19d50;
+L_0x5592cfd1a130 .concat [ 24 1 0 0], L_0x5592cfd088a0, L_0x7ff85d2be258;
+L_0x5592cfd1a420 .concat [ 24 1 0 0], L_0x5592cfd08c20, L_0x7ff85d2be2a0;
+L_0x5592cfd1a510 .arith/sum 25, L_0x5592cfd1a130, L_0x5592cfd196e0;
+L_0x5592cfd1a840 .arith/sum 25, L_0x5592cfd1a510, L_0x7ff85d2be2e8;
+L_0x5592cfd1a980 .functor MUXZ 25, L_0x5592cfd19ff0, L_0x5592cfd1a840, v0x5592cfd06280_0, C4<>;
+L_0x5592cfd1aca0 .part L_0x5592cfd1a980, 24, 1;
+L_0x5592cfd1af20 .arith/sum 25, L_0x5592cfd1aeb0, L_0x7ff85d2be330;
+L_0x5592cfd1b220 .functor MUXZ 25, L_0x5592cfd1af20, L_0x5592cfd1a980, L_0x5592cfd1a5b0, C4<>;
+L_0x5592cfd1b620 .part v0x5592cfd06410_0, 31, 1;
+L_0x5592cfd1b870 .part v0x5592cfd06510_0, 31, 1;
+L_0x5592cfd1bac0 .part v0x5592cfd06410_0, 31, 1;
+L_0x5592cfd1bd20 .part v0x5592cfd06510_0, 31, 1;
+L_0x5592cfd1c030 .cmp/gt 24, L_0x5592cfd088a0, L_0x5592cfd08c20;
+L_0x5592cfd1c2a0 .functor MUXZ 2, L_0x7ff85d2be408, L_0x7ff85d2be3c0, L_0x5592cfd1c030, C4<>;
+L_0x5592cfd1c3e0 .part v0x5592cfd06410_0, 31, 1;
+L_0x5592cfd1c660 .concat [ 1 1 0 0], L_0x5592cfd1c3e0, L_0x7ff85d2be450;
+L_0x5592cfd1c7a0 .functor MUXZ 2, L_0x5592cfd1c660, L_0x5592cfd1c2a0, L_0x5592cfd1bf30, C4<>;
+L_0x5592cfd1cb20 .cmp/gt 24, L_0x5592cfd088a0, L_0x5592cfd08c20;
+L_0x5592cfd1cbc0 .part v0x5592cfd06410_0, 31, 1;
+L_0x5592cfd1ce60 .concat [ 1 1 0 0], L_0x5592cfd1cbc0, L_0x7ff85d2be498;
+L_0x5592cfd1cfa0 .part v0x5592cfd06510_0, 31, 1;
+L_0x5592cfd1d250 .concat [ 1 1 0 0], L_0x5592cfd1cfa0, L_0x7ff85d2be4e0;
+L_0x5592cfd1d390 .functor MUXZ 2, L_0x5592cfd1d250, L_0x5592cfd1ce60, L_0x5592cfd1cb20, C4<>;
+L_0x5592cfd1d740 .functor MUXZ 2, L_0x5592cfd1d390, L_0x5592cfd1c7a0, L_0x5592cfd1ba00, C4<>;
+L_0x5592cfd1d8d0 .part L_0x5592cfd1d740, 0, 1;
+L_0x5592cfd1dbf0 .part v0x5592cfcfec10_0, 24, 1;
+L_0x5592cfd1dce0 .functor MUXZ 8, L_0x5592cfd06ef0, L_0x5592cfd06ef0, L_0x5592cfd1dbf0, C4<>;
+L_0x5592cfd1e010 .functor MUXZ 8, L_0x5592cfd1dce0, L_0x5592cfd1b4e0, L_0x5592cfd07290, C4<>;
+L_0x5592cfd1e0b0 .part L_0x5592cfd1b220, 24, 1;
+L_0x5592cfd1e4d0 .arith/sum 8, L_0x5592cfd06ef0, L_0x7ff85d2be528;
+L_0x5592cfd1e630 .functor MUXZ 8, L_0x5592cfd1b4e0, L_0x5592cfd06ef0, L_0x5592cfd07290, C4<>;
+L_0x5592cfd1e9c0 .functor MUXZ 8, L_0x5592cfd1e630, L_0x5592cfd1e4d0, L_0x5592cfd1e3a0, C4<>;
+L_0x5592cfd1eb00 .functor MUXZ 8, L_0x5592cfd1e9c0, L_0x5592cfd1e010, v0x5592cfd06280_0, C4<>;
+L_0x5592cfd1eeb0 .concat8 [ 23 8 1 0], L_0x5592cfd20c20, L_0x5592cfd1eb00, L_0x5592cfd1d8d0;
+L_0x5592cfd1f040 .part v0x5592cfcfec10_0, 0, 23;
+L_0x5592cfd1f360 .part v0x5592cfcfec10_0, 24, 1;
+L_0x5592cfd1f490 .part v0x5592cfcfec10_0, 1, 23;
+L_0x5592cfd1f7c0 .part v0x5592cfcfec10_0, 0, 23;
+L_0x5592cfd1f860 .functor MUXZ 23, L_0x5592cfd1f7c0, L_0x5592cfd1f490, L_0x5592cfd1f360, C4<>;
+L_0x5592cfd1fc40 .functor MUXZ 23, L_0x5592cfd1f860, L_0x5592cfd1f040, L_0x5592cfd07290, C4<>;
+L_0x5592cfd1fe90 .part L_0x5592cfd1b220, 24, 1;
+L_0x5592cfd201e0 .part L_0x5592cfd1b220, 1, 23;
+L_0x5592cfd20280 .part L_0x5592cfd1b220, 0, 23;
+L_0x5592cfd205e0 .part v0x5592cfcfec10_0, 0, 23;
+L_0x5592cfd20680 .functor MUXZ 23, L_0x5592cfd205e0, L_0x5592cfd20280, L_0x5592cfd07290, C4<>;
+L_0x5592cfd20a90 .functor MUXZ 23, L_0x5592cfd20680, L_0x5592cfd201e0, L_0x5592cfd1e570, C4<>;
+L_0x5592cfd20c20 .functor MUXZ 23, L_0x5592cfd20a90, L_0x5592cfd1fc40, v0x5592cfd06280_0, C4<>;
+S_0x5592cfc9c0b0 .scope module, "exp_calc0" "exp_calc" 3 42, 4 10 0, S_0x5592cfc9da90;
+ .timescale -6 -9;
+ .port_info 0 /INPUT 25 "significand";
+ .port_info 1 /INPUT 8 "Exponent_a";
+ .port_info 2 /OUTPUT 25 "Significand";
+ .port_info 3 /OUTPUT 8 "Exponent_sub";
+v0x5592cfc9b420_0 .net "Exponent_a", 7 0, L_0x5592cfd06ef0; alias, 1 drivers
+v0x5592cfcfeb30_0 .net "Exponent_sub", 7 0, L_0x5592cfd1b4e0; alias, 1 drivers
+v0x5592cfcfec10_0 .var "Significand", 24 0;
+v0x5592cfcfecd0_0 .net *"_ivl_0", 7 0, L_0x5592cfd1b440; 1 drivers
+L_0x7ff85d2be378 .functor BUFT 1, C4<000>, C4<0>, C4<0>, C4<0>;
+v0x5592cfcfedb0_0 .net *"_ivl_3", 2 0, L_0x7ff85d2be378; 1 drivers
+v0x5592cfcfeee0_0 .var "shift", 4 0;
+v0x5592cfcfefc0_0 .net "significand", 24 0, L_0x5592cfd1b220; alias, 1 drivers
+E_0x5592cfca3a00 .event edge, v0x5592cfcfefc0_0;
+L_0x5592cfd1b440 .concat [ 5 3 0 0], v0x5592cfcfeee0_0, L_0x7ff85d2be378;
+L_0x5592cfd1b4e0 .arith/sub 8, L_0x5592cfd06ef0, L_0x5592cfd1b440;
+ .scope S_0x5592cfc9c0b0;
+T_0 ;
+ %wait E_0x5592cfca3a00;
+ %load/vec4 v0x5592cfcfefc0_0;
+ %dup/vec4;
+ %pushi/vec4 33554431, 25165823, 25;
+ %cmp/x;
+ %jmp/1 T_0.0, 4;
+ %dup/vec4;
+ %pushi/vec4 25165823, 20971519, 25;
+ %cmp/x;
+ %jmp/1 T_0.1, 4;
+ %dup/vec4;
+ %pushi/vec4 20971519, 18874367, 25;
+ %cmp/x;
+ %jmp/1 T_0.2, 4;
+ %dup/vec4;
+ %pushi/vec4 18874367, 17825791, 25;
+ %cmp/x;
+ %jmp/1 T_0.3, 4;
+ %dup/vec4;
+ %pushi/vec4 17825791, 17301503, 25;
+ %cmp/x;
+ %jmp/1 T_0.4, 4;
+ %dup/vec4;
+ %pushi/vec4 17301503, 17039359, 25;
+ %cmp/x;
+ %jmp/1 T_0.5, 4;
+ %dup/vec4;
+ %pushi/vec4 17039359, 16908287, 25;
+ %cmp/x;
+ %jmp/1 T_0.6, 4;
+ %dup/vec4;
+ %pushi/vec4 16908287, 16842751, 25;
+ %cmp/x;
+ %jmp/1 T_0.7, 4;
+ %dup/vec4;
+ %pushi/vec4 16842751, 16809983, 25;
+ %cmp/x;
+ %jmp/1 T_0.8, 4;
+ %dup/vec4;
+ %pushi/vec4 16809983, 16793599, 25;
+ %cmp/x;
+ %jmp/1 T_0.9, 4;
+ %dup/vec4;
+ %pushi/vec4 16793599, 16785407, 25;
+ %cmp/x;
+ %jmp/1 T_0.10, 4;
+ %dup/vec4;
+ %pushi/vec4 16785407, 16781311, 25;
+ %cmp/x;
+ %jmp/1 T_0.11, 4;
+ %dup/vec4;
+ %pushi/vec4 16781311, 16779263, 25;
+ %cmp/x;
+ %jmp/1 T_0.12, 4;
+ %dup/vec4;
+ %pushi/vec4 16779263, 16778239, 25;
+ %cmp/x;
+ %jmp/1 T_0.13, 4;
+ %dup/vec4;
+ %pushi/vec4 16778239, 16777727, 25;
+ %cmp/x;
+ %jmp/1 T_0.14, 4;
+ %dup/vec4;
+ %pushi/vec4 16777727, 16777471, 25;
+ %cmp/x;
+ %jmp/1 T_0.15, 4;
+ %dup/vec4;
+ %pushi/vec4 16777471, 16777343, 25;
+ %cmp/x;
+ %jmp/1 T_0.16, 4;
+ %dup/vec4;
+ %pushi/vec4 16777343, 16777279, 25;
+ %cmp/x;
+ %jmp/1 T_0.17, 4;
+ %dup/vec4;
+ %pushi/vec4 16777279, 16777247, 25;
+ %cmp/x;
+ %jmp/1 T_0.18, 4;
+ %dup/vec4;
+ %pushi/vec4 16777247, 16777231, 25;
+ %cmp/x;
+ %jmp/1 T_0.19, 4;
+ %dup/vec4;
+ %pushi/vec4 16777231, 16777223, 25;
+ %cmp/x;
+ %jmp/1 T_0.20, 4;
+ %dup/vec4;
+ %pushi/vec4 16777223, 16777219, 25;
+ %cmp/x;
+ %jmp/1 T_0.21, 4;
+ %dup/vec4;
+ %pushi/vec4 16777219, 16777217, 25;
+ %cmp/x;
+ %jmp/1 T_0.22, 4;
+ %dup/vec4;
+ %pushi/vec4 16777217, 16777216, 25;
+ %cmp/x;
+ %jmp/1 T_0.23, 4;
+ %dup/vec4;
+ %pushi/vec4 16777216, 16777216, 25;
+ %cmp/x;
+ %jmp/1 T_0.24, 4;
+ %load/vec4 v0x5592cfcfefc0_0;
+ %store/vec4 v0x5592cfcfec10_0, 0, 25;
+ %pushi/vec4 0, 0, 5;
+ %store/vec4 v0x5592cfcfeee0_0, 0, 5;
+ %jmp T_0.26;
+T_0.0 ;
+ %load/vec4 v0x5592cfcfefc0_0;
+ %store/vec4 v0x5592cfcfec10_0, 0, 25;
+ %pushi/vec4 0, 0, 5;
+ %store/vec4 v0x5592cfcfeee0_0, 0, 5;
+ %jmp T_0.26;
+T_0.1 ;
+ %load/vec4 v0x5592cfcfefc0_0;
+ %ix/load 4, 1, 0;
+ %flag_set/imm 4, 0;
+ %shiftl 4;
+ %store/vec4 v0x5592cfcfec10_0, 0, 25;
+ %pushi/vec4 1, 0, 5;
+ %store/vec4 v0x5592cfcfeee0_0, 0, 5;
+ %jmp T_0.26;
+T_0.2 ;
+ %load/vec4 v0x5592cfcfefc0_0;
+ %ix/load 4, 2, 0;
+ %flag_set/imm 4, 0;
+ %shiftl 4;
+ %store/vec4 v0x5592cfcfec10_0, 0, 25;
+ %pushi/vec4 2, 0, 5;
+ %store/vec4 v0x5592cfcfeee0_0, 0, 5;
+ %jmp T_0.26;
+T_0.3 ;
+ %load/vec4 v0x5592cfcfefc0_0;
+ %ix/load 4, 3, 0;
+ %flag_set/imm 4, 0;
+ %shiftl 4;
+ %store/vec4 v0x5592cfcfec10_0, 0, 25;
+ %pushi/vec4 3, 0, 5;
+ %store/vec4 v0x5592cfcfeee0_0, 0, 5;
+ %jmp T_0.26;
+T_0.4 ;
+ %load/vec4 v0x5592cfcfefc0_0;
+ %ix/load 4, 4, 0;
+ %flag_set/imm 4, 0;
+ %shiftl 4;
+ %store/vec4 v0x5592cfcfec10_0, 0, 25;
+ %pushi/vec4 4, 0, 5;
+ %store/vec4 v0x5592cfcfeee0_0, 0, 5;
+ %jmp T_0.26;
+T_0.5 ;
+ %load/vec4 v0x5592cfcfefc0_0;
+ %ix/load 4, 5, 0;
+ %flag_set/imm 4, 0;
+ %shiftl 4;
+ %store/vec4 v0x5592cfcfec10_0, 0, 25;
+ %pushi/vec4 5, 0, 5;
+ %store/vec4 v0x5592cfcfeee0_0, 0, 5;
+ %jmp T_0.26;
+T_0.6 ;
+ %load/vec4 v0x5592cfcfefc0_0;
+ %ix/load 4, 6, 0;
+ %flag_set/imm 4, 0;
+ %shiftl 4;
+ %store/vec4 v0x5592cfcfec10_0, 0, 25;
+ %pushi/vec4 6, 0, 5;
+ %store/vec4 v0x5592cfcfeee0_0, 0, 5;
+ %jmp T_0.26;
+T_0.7 ;
+ %load/vec4 v0x5592cfcfefc0_0;
+ %ix/load 4, 7, 0;
+ %flag_set/imm 4, 0;
+ %shiftl 4;
+ %store/vec4 v0x5592cfcfec10_0, 0, 25;
+ %pushi/vec4 7, 0, 5;
+ %store/vec4 v0x5592cfcfeee0_0, 0, 5;
+ %jmp T_0.26;
+T_0.8 ;
+ %load/vec4 v0x5592cfcfefc0_0;
+ %ix/load 4, 8, 0;
+ %flag_set/imm 4, 0;
+ %shiftl 4;
+ %store/vec4 v0x5592cfcfec10_0, 0, 25;
+ %pushi/vec4 8, 0, 5;
+ %store/vec4 v0x5592cfcfeee0_0, 0, 5;
+ %jmp T_0.26;
+T_0.9 ;
+ %load/vec4 v0x5592cfcfefc0_0;
+ %ix/load 4, 9, 0;
+ %flag_set/imm 4, 0;
+ %shiftl 4;
+ %store/vec4 v0x5592cfcfec10_0, 0, 25;
+ %pushi/vec4 9, 0, 5;
+ %store/vec4 v0x5592cfcfeee0_0, 0, 5;
+ %jmp T_0.26;
+T_0.10 ;
+ %load/vec4 v0x5592cfcfefc0_0;
+ %ix/load 4, 10, 0;
+ %flag_set/imm 4, 0;
+ %shiftl 4;
+ %store/vec4 v0x5592cfcfec10_0, 0, 25;
+ %pushi/vec4 10, 0, 5;
+ %store/vec4 v0x5592cfcfeee0_0, 0, 5;
+ %jmp T_0.26;
+T_0.11 ;
+ %load/vec4 v0x5592cfcfefc0_0;
+ %ix/load 4, 11, 0;
+ %flag_set/imm 4, 0;
+ %shiftl 4;
+ %store/vec4 v0x5592cfcfec10_0, 0, 25;
+ %pushi/vec4 11, 0, 5;
+ %store/vec4 v0x5592cfcfeee0_0, 0, 5;
+ %jmp T_0.26;
+T_0.12 ;
+ %load/vec4 v0x5592cfcfefc0_0;
+ %ix/load 4, 12, 0;
+ %flag_set/imm 4, 0;
+ %shiftl 4;
+ %store/vec4 v0x5592cfcfec10_0, 0, 25;
+ %pushi/vec4 12, 0, 5;
+ %store/vec4 v0x5592cfcfeee0_0, 0, 5;
+ %jmp T_0.26;
+T_0.13 ;
+ %load/vec4 v0x5592cfcfefc0_0;
+ %ix/load 4, 13, 0;
+ %flag_set/imm 4, 0;
+ %shiftl 4;
+ %store/vec4 v0x5592cfcfec10_0, 0, 25;
+ %pushi/vec4 13, 0, 5;
+ %store/vec4 v0x5592cfcfeee0_0, 0, 5;
+ %jmp T_0.26;
+T_0.14 ;
+ %load/vec4 v0x5592cfcfefc0_0;
+ %ix/load 4, 14, 0;
+ %flag_set/imm 4, 0;
+ %shiftl 4;
+ %store/vec4 v0x5592cfcfec10_0, 0, 25;
+ %pushi/vec4 14, 0, 5;
+ %store/vec4 v0x5592cfcfeee0_0, 0, 5;
+ %jmp T_0.26;
+T_0.15 ;
+ %load/vec4 v0x5592cfcfefc0_0;
+ %ix/load 4, 15, 0;
+ %flag_set/imm 4, 0;
+ %shiftl 4;
+ %store/vec4 v0x5592cfcfec10_0, 0, 25;
+ %pushi/vec4 15, 0, 5;
+ %store/vec4 v0x5592cfcfeee0_0, 0, 5;
+ %jmp T_0.26;
+T_0.16 ;
+ %load/vec4 v0x5592cfcfefc0_0;
+ %ix/load 4, 16, 0;
+ %flag_set/imm 4, 0;
+ %shiftl 4;
+ %store/vec4 v0x5592cfcfec10_0, 0, 25;
+ %pushi/vec4 16, 0, 5;
+ %store/vec4 v0x5592cfcfeee0_0, 0, 5;
+ %jmp T_0.26;
+T_0.17 ;
+ %load/vec4 v0x5592cfcfefc0_0;
+ %ix/load 4, 17, 0;
+ %flag_set/imm 4, 0;
+ %shiftl 4;
+ %store/vec4 v0x5592cfcfec10_0, 0, 25;
+ %pushi/vec4 17, 0, 5;
+ %store/vec4 v0x5592cfcfeee0_0, 0, 5;
+ %jmp T_0.26;
+T_0.18 ;
+ %load/vec4 v0x5592cfcfefc0_0;
+ %ix/load 4, 18, 0;
+ %flag_set/imm 4, 0;
+ %shiftl 4;
+ %store/vec4 v0x5592cfcfec10_0, 0, 25;
+ %pushi/vec4 18, 0, 5;
+ %store/vec4 v0x5592cfcfeee0_0, 0, 5;
+ %jmp T_0.26;
+T_0.19 ;
+ %load/vec4 v0x5592cfcfefc0_0;
+ %ix/load 4, 19, 0;
+ %flag_set/imm 4, 0;
+ %shiftl 4;
+ %store/vec4 v0x5592cfcfec10_0, 0, 25;
+ %pushi/vec4 19, 0, 5;
+ %store/vec4 v0x5592cfcfeee0_0, 0, 5;
+ %jmp T_0.26;
+T_0.20 ;
+ %load/vec4 v0x5592cfcfefc0_0;
+ %ix/load 4, 20, 0;
+ %flag_set/imm 4, 0;
+ %shiftl 4;
+ %store/vec4 v0x5592cfcfec10_0, 0, 25;
+ %pushi/vec4 20, 0, 5;
+ %store/vec4 v0x5592cfcfeee0_0, 0, 5;
+ %jmp T_0.26;
+T_0.21 ;
+ %load/vec4 v0x5592cfcfefc0_0;
+ %ix/load 4, 21, 0;
+ %flag_set/imm 4, 0;
+ %shiftl 4;
+ %store/vec4 v0x5592cfcfec10_0, 0, 25;
+ %pushi/vec4 21, 0, 5;
+ %store/vec4 v0x5592cfcfeee0_0, 0, 5;
+ %jmp T_0.26;
+T_0.22 ;
+ %load/vec4 v0x5592cfcfefc0_0;
+ %ix/load 4, 22, 0;
+ %flag_set/imm 4, 0;
+ %shiftl 4;
+ %store/vec4 v0x5592cfcfec10_0, 0, 25;
+ %pushi/vec4 22, 0, 5;
+ %store/vec4 v0x5592cfcfeee0_0, 0, 5;
+ %jmp T_0.26;
+T_0.23 ;
+ %load/vec4 v0x5592cfcfefc0_0;
+ %ix/load 4, 23, 0;
+ %flag_set/imm 4, 0;
+ %shiftl 4;
+ %store/vec4 v0x5592cfcfec10_0, 0, 25;
+ %pushi/vec4 23, 0, 5;
+ %store/vec4 v0x5592cfcfeee0_0, 0, 5;
+ %jmp T_0.26;
+T_0.24 ;
+ %load/vec4 v0x5592cfcfefc0_0;
+ %ix/load 4, 24, 0;
+ %flag_set/imm 4, 0;
+ %shiftl 4;
+ %store/vec4 v0x5592cfcfec10_0, 0, 25;
+ %pushi/vec4 24, 0, 5;
+ %store/vec4 v0x5592cfcfeee0_0, 0, 5;
+ %jmp T_0.26;
+T_0.26 ;
+ %pop/vec4 1;
+ %jmp T_0;
+ .thread T_0, $push;
+ .scope S_0x5592cfc9f490;
+T_1 ;
+ %pushi/vec4 0, 0, 1;
+ %store/vec4 v0x5592cfd06280_0, 0, 1;
+ %end;
+ .thread T_1;
+ .scope S_0x5592cfc9f490;
+T_2 ;
+ %pushi/vec4 1075629261, 0, 32;
+ %store/vec4 v0x5592cfd06410_0, 0, 32;
+ %pushi/vec4 1059481190, 0, 32;
+ %store/vec4 v0x5592cfd06510_0, 0, 32;
+ %delay 5000, 0;
+ %vpi_call 2 18 "$display", "\012Sum: %16b + %16b = %16b", v0x5592cfd06410_0, v0x5592cfd06510_0, v0x5592cfd06340_0 {0 0 0};
+ %pushi/vec4 1075629261, 0, 32;
+ %store/vec4 v0x5592cfd06410_0, 0, 32;
+ %pushi/vec4 3206964838, 0, 32;
+ %store/vec4 v0x5592cfd06510_0, 0, 32;
+ %delay 5000, 0;
+ %vpi_call 2 23 "$display", "\012Sum: %16b + %16b = %16b", v0x5592cfd06410_0, v0x5592cfd06510_0, v0x5592cfd06340_0 {0 0 0};
+ %pushi/vec4 3223112909, 0, 32;
+ %store/vec4 v0x5592cfd06410_0, 0, 32;
+ %pushi/vec4 1059481190, 0, 32;
+ %store/vec4 v0x5592cfd06510_0, 0, 32;
+ %delay 5000, 0;
+ %vpi_call 2 28 "$display", "\012Sum: %16b + %16b = %16b", v0x5592cfd06410_0, v0x5592cfd06510_0, v0x5592cfd06340_0 {0 0 0};
+ %pushi/vec4 3223112909, 0, 32;
+ %store/vec4 v0x5592cfd06410_0, 0, 32;
+ %pushi/vec4 3206964838, 0, 32;
+ %store/vec4 v0x5592cfd06510_0, 0, 32;
+ %delay 5000, 0;
+ %vpi_call 2 33 "$display", "\012Sum: %16b + %16b = %16b", v0x5592cfd06410_0, v0x5592cfd06510_0, v0x5592cfd06340_0 {0 0 0};
+ %pushi/vec4 1, 0, 1;
+ %store/vec4 v0x5592cfd06280_0, 0, 1;
+ %pushi/vec4 1075629261, 0, 32;
+ %store/vec4 v0x5592cfd06410_0, 0, 32;
+ %pushi/vec4 1059481190, 0, 32;
+ %store/vec4 v0x5592cfd06510_0, 0, 32;
+ %delay 5000, 0;
+ %vpi_call 2 40 "$display", "\012Sum: %16b - %16b = %16b", v0x5592cfd06410_0, v0x5592cfd06510_0, v0x5592cfd06340_0 {0 0 0};
+ %pushi/vec4 1075629261, 0, 32;
+ %store/vec4 v0x5592cfd06410_0, 0, 32;
+ %pushi/vec4 3206964838, 0, 32;
+ %store/vec4 v0x5592cfd06510_0, 0, 32;
+ %delay 5000, 0;
+ %vpi_call 2 45 "$display", "\012Sum: %16b - %16b = %16b", v0x5592cfd06410_0, v0x5592cfd06510_0, v0x5592cfd06340_0 {0 0 0};
+ %pushi/vec4 3223112909, 0, 32;
+ %store/vec4 v0x5592cfd06410_0, 0, 32;
+ %pushi/vec4 1059481190, 0, 32;
+ %store/vec4 v0x5592cfd06510_0, 0, 32;
+ %delay 5000, 0;
+ %vpi_call 2 50 "$display", "\012Sum: %16b - %16b = %16b", v0x5592cfd06410_0, v0x5592cfd06510_0, v0x5592cfd06340_0 {0 0 0};
+ %pushi/vec4 3223112909, 0, 32;
+ %store/vec4 v0x5592cfd06410_0, 0, 32;
+ %pushi/vec4 3206964838, 0, 32;
+ %store/vec4 v0x5592cfd06510_0, 0, 32;
+ %delay 5000, 0;
+ %vpi_call 2 55 "$display", "\012Sum: %16b - %16b = %16b", v0x5592cfd06410_0, v0x5592cfd06510_0, v0x5592cfd06340_0 {0 0 0};
+ %vpi_call 2 56 "$finish" {0 0 0};
+ %end;
+ .thread T_2;
+# The file index is used to find the file name in the following table.
+:file_names 5;
+ "N/A";
+ "<interactive>";
+ "fpu_bench.v";
+ "./fpu_2.v";
+ "./exp_calc.v";
diff --git a/verilog/fpu/compile b/verilog/fpu/compile
new file mode 100755
index 0000000..08b3b83
--- /dev/null
+++ b/verilog/fpu/compile
@@ -0,0 +1,4 @@
+#!/bin/sh
+
+iverilog fpu_bench.v
+vvp a.out
diff --git a/verilog/fpu/exp_calc.v b/verilog/fpu/exp_calc.v
new file mode 100644
index 0000000..89838f4
--- /dev/null
+++ b/verilog/fpu/exp_calc.v
@@ -0,0 +1,152 @@
+///////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+//File Name: Priority Encoder.v
+//Created By: Sheetal Swaroop Burada
+//Date: 30-04-2019
+//Project Name: Design of 32 Bit Floating Point ALU Based on Standard IEEE-754 in Verilog and its implementation on FPGA.
+//University: Dayalbagh Educational Institute
+////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+
+module exp_calc(
+ input [24:0] significand,
+ input [7:0] Exponent_a,
+ output reg [24:0] Significand,
+ output [7:0] Exponent_sub
+ );
+
+reg [4:0] shift;
+
+always @(significand)
+begin
+ casex (significand)
+ 25'bx_1xxx_xxxx_xxxx_xxxx_xxxx_xxxx : begin
+ Significand = significand;
+ shift = 5'd0;
+ end
+ 25'bx_01xx_xxxx_xxxx_xxxx_xxxx_xxxx : begin
+ Significand = significand << 1;
+ shift = 5'd1;
+ end
+ 25'bx_001x_xxxx_xxxx_xxxx_xxxx_xxxx : begin
+ Significand = significand << 2;
+ shift = 5'd2;
+ end
+ 25'bx_0001_xxxx_xxxx_xxxx_xxxx_xxxx : begin
+ Significand = significand << 3;
+ shift = 5'd3;
+ end
+
+ 25'bx_0000_1xxx_xxxx_xxxx_xxxx_xxxx : begin
+ Significand = significand << 4;
+ shift = 5'd4;
+ end
+
+ 25'bx_0000_01xx_xxxx_xxxx_xxxx_xxxx : begin
+ Significand = significand << 5;
+ shift = 5'd5;
+ end
+
+ 25'bx_0000_001x_xxxx_xxxx_xxxx_xxxx : begin // 24'h020000
+ Significand = significand << 6;
+ shift = 5'd6;
+ end
+
+ 25'bx_0000_0001_xxxx_xxxx_xxxx_xxxx : begin // 24'h010000
+ Significand = significand << 7;
+ shift = 5'd7;
+ end
+
+ 25'bx_0000_0000_1xxx_xxxx_xxxx_xxxx : begin // 24'h008000
+ Significand = significand << 8;
+ shift = 5'd8;
+ end
+
+ 25'bx_0000_0000_01xx_xxxx_xxxx_xxxx : begin // 24'h004000
+ Significand = significand << 9;
+ shift = 5'd9;
+ end
+
+ 25'bx_0000_0000_001x_xxxx_xxxx_xxxx : begin // 24'h002000
+ Significand = significand << 10;
+ shift = 5'd10;
+ end
+
+ 25'bx_0000_0000_0001_xxxx_xxxx_xxxx : begin // 24'h001000
+ Significand = significand << 11;
+ shift = 5'd11;
+ end
+
+ 25'bx_0000_0000_0000_1xxx_xxxx_xxxx : begin // 24'h000800
+ Significand = significand << 12;
+ shift = 5'd12;
+ end
+
+ 25'bx_0000_0000_0000_01xx_xxxx_xxxx : begin // 24'h000400
+ Significand = significand << 13;
+ shift = 5'd13;
+ end
+
+ 25'bx_0000_0000_0000_001x_xxxx_xxxx : begin // 24'h000200
+ Significand = significand << 14;
+ shift = 5'd14;
+ end
+
+ 25'bx_0000_0000_0000_0001_xxxx_xxxx : begin // 24'h000100
+ Significand = significand << 15;
+ shift = 5'd15;
+ end
+
+ 25'bx_0000_0000_0000_0000_1xxx_xxxx : begin // 24'h000080
+ Significand = significand << 16;
+ shift = 5'd16;
+ end
+
+ 25'bx_0000_0000_0000_0000_01xx_xxxx : begin // 24'h000040
+ Significand = significand << 17;
+ shift = 5'd17;
+ end
+
+ 25'bx_0000_0000_0000_0000_001x_xxxx : begin // 24'h000020
+ Significand = significand << 18;
+ shift = 5'd18;
+ end
+
+ 25'bx_0000_0000_0000_0000_0001_xxxx : begin // 24'h000010
+ Significand = significand << 19;
+ shift = 5'd19;
+ end
+
+ 25'bx_0000_0000_0000_0000_0000_1xxx : begin // 24'h000008
+ Significand = significand << 20;
+ shift = 5'd20;
+ end
+
+ 25'bx_0000_0000_0000_0000_0000_01xx : begin // 24'h000004
+ Significand = significand << 21;
+ shift = 5'd21;
+ end
+
+ 25'bx_0000_0000_0000_0000_0000_001x : begin // 24'h000002
+ Significand = significand << 22;
+ shift = 5'd22;
+ end
+
+ 25'bx_0000_0000_0000_0000_0000_0001 : begin // 24'h000001
+ Significand = significand << 23;
+ shift = 5'd23;
+ end
+
+ 25'bx_0000_0000_0000_0000_0000_0000 : begin // 24'h000000
+ Significand = significand << 24;
+ shift = 5'd24;
+ end
+ default : begin
+ Significand = significand;
+ shift = 8'd0;
+ end
+
+ endcase
+end
+assign Exponent_sub = Exponent_a - shift;
+
+endmodule
diff --git a/verilog/fpu/fpu.v b/verilog/fpu/fpu.v
new file mode 100644
index 0000000..7ec70d9
--- /dev/null
+++ b/verilog/fpu/fpu.v
@@ -0,0 +1,71 @@
+module fpu
+(
+ input wire [31:0] fpu_in_1,
+ input wire [31:0] fpu_in_2,
+ output wire[31:0] fpu_output
+);
+
+reg[31:0] tmp_out;
+reg[22:0] fpu_reg_1;
+reg[22:0] fpu_reg_2;
+reg[7:0] exp;
+
+wire [7:0] dif_exp = fpu_in_1[30:23] - fpu_in_2[30:23];
+wire [7:0] neg_dif_exp = fpu_in_2[30:23] - fpu_in_1[30:23];
+
+reg[23:0] mantis_sum;
+
+always @ ( * )
+begin
+ /* $display("\nNEW TEST\n"); */
+ /* $display("\nMantissas R1: %16b R2: %16b", fpu_in_1[22:0], fpu_in_2[22:0]); */
+ /* $display("\ndif_exp[7]: %16b", dif_exp); */
+ if (dif_exp[7] == 1'b1) begin
+ fpu_reg_1 = fpu_in_1[22:0] >> 1;
+ fpu_reg_1[22] = 1'b1;
+ fpu_reg_1 = fpu_reg_1 >> neg_dif_exp-1;
+ fpu_reg_2 = fpu_in_2[22:0];
+ exp = fpu_in_2[30:23];
+ /* $display("\n1 1 smaller exp: %16b", neg_dif_exp, fpu_reg_1[22:0]); */
+ end else begin
+ if (dif_exp > 8'b0) begin
+ fpu_reg_2 = fpu_in_2 >> 1;
+ fpu_reg_2[22] = 1'b1;
+ fpu_reg_2 = fpu_reg_2 >> dif_exp-1;
+ /* $display("\n 2 smaller exp: %16b, shifted R2: %16b", dif_exp, fpu_reg_2[22:0]); */
+ end else begin
+ fpu_reg_2 = fpu_in_2[22:0];
+ /* $display("\nexp equal"); */
+ end
+ fpu_reg_1 = fpu_in_1[22:0];
+ exp = fpu_in_1[30:23];
+ end
+
+ /* $display("\nDenormalized mantissas: 1: %16b, 2: %16b: ", fpu_reg_1, fpu_reg_2); */
+ /* $display("\nexp: %16b", exp); */
+
+ mantis_sum = fpu_reg_1 + fpu_reg_2;
+
+ /* $display("\nmantis: %16b, exp:%16b", mantis_sum, exp); */
+
+ if (mantis_sum[23] == 1'b1) begin
+ exp = exp + 1;
+ mantis_sum = mantis_sum >> 1'b1;
+ if (dif_exp == 8'b0) begin
+ mantis_sum[22] = 1'b1;
+ end else begin
+ mantis_sum[22] = 1'b0;
+ end
+
+ /* $display("\nshifted exp: %16b", exp); */
+ /* $display("\nshifted mantis: %16b", mantis_sum); */
+ end
+
+
+ tmp_out[31] = 1'b0;
+ tmp_out[30:23] = exp;
+ tmp_out[22:0] = mantis_sum[22:0];
+end
+
+assign fpu_output = tmp_out;
+endmodule
diff --git a/verilog/fpu/fpu_2.v b/verilog/fpu/fpu_2.v
new file mode 100644
index 0000000..b1930a5
--- /dev/null
+++ b/verilog/fpu/fpu_2.v
@@ -0,0 +1,54 @@
+`include "exp_calc.v"
+module fpu_2(
+ input wire add_not,
+ input wire[31:0] a_in, b_in,
+ output wire[31:0] out
+);
+
+wire[23:0] a_sig, b_sig, b_shft_sig, a_shft_sig, a_sign_sig, b_sign_sig;
+wire[24:0] sig_sum, sig_diff, sig_op, sig_final;
+wire[7:0] exp;
+wire[7:0] diff, neg_diff;
+wire same_sign;
+
+assign diff = a_in[30:23] - b_in[30:23];
+assign neg_diff = b_in[30:23] - a_in[30:23];
+assign exp = diff[7] ? b_in[30:23] : a_in[30:23];
+
+assign same_sign = ~(a_in[31] ^ b_in[31]);
+
+// Pull hidden bit into sig, if exp 0, no hidden bit
+assign a_sig = (|a_in[30:23] ? {1'b1, a_in[22:0]} : {1'b0, a_in[22:0]});
+assign b_sig = (|b_in[30:23] ? {1'b1, b_in[22:0]} : {1'b0, b_in[22:0]});
+
+assign a_shft_sig = (diff[7] ? a_sig >> neg_diff : a_sig);
+assign b_shft_sig = (diff[7] ? b_sig : b_sig >> diff);
+
+//2C Invert if Negative and not same signs
+assign a_sign_sig = same_sign ? a_shft_sig : (a_in[31] ? ~(a_shft_sig) + 24'b1 : a_shft_sig);
+assign b_sign_sig = same_sign ? b_shft_sig : (b_in[31] ? ~(b_shft_sig) + 24'b1 : b_shft_sig);
+
+//Adding
+assign sig_sum = a_sign_sig + b_sign_sig;
+
+//Subtraction
+assign sig_diff = a_shft_sig + ~(b_shft_sig) + 25'b1;
+
+assign sig_op = add_not ? sig_diff : sig_sum;
+assign sig_final = sig_op[24] | same_sign ? sig_op : ~(sig_op) + 24'b1;
+
+wire[24:0] sig_diff_final;
+wire[7:0] exp_diff;
+exp_calc exp_calc0(sig_final,exp,sig_diff_final,exp_diff);
+
+
+// Assign exp and mantissa
+assign out[31] = add_not & (a_in[31] | b_in[31]) ? (a_in[31] ^ b_in[31] ^ add_not ? (a_shft_sig > b_shft_sig ? 1 : 0) : a_in[31]) : (a_shft_sig > b_shft_sig ? a_in[31] : b_in[31]);
+assign out[30:23] = add_not ? (same_sign ? exp_diff : (sig_diff_final[24] ? exp : exp)) : (sig_final[24] & same_sign ? exp + 8'b1 : (same_sign ? exp : exp_diff));
+assign out[22:0] = add_not ? (same_sign ? sig_diff_final[22:0] : sig_diff_final[24] ? sig_diff_final[23:1] : sig_diff_final[22:0]) : sig_final[24] & same_sign ? sig_final[23:1] : (same_sign ? sig_final[22:0] : sig_diff_final[22:0]);
+
+/* assign out = {exp_diff, 24'b0}; */
+// assign out = {diff, neg_diff, 16'b0};
+/* assign out = {sig_op, 7'b0}; */
+
+endmodule
diff --git a/verilog/fpu/fpu_2.v.add.bak b/verilog/fpu/fpu_2.v.add.bak
new file mode 100644
index 0000000..c4d29c8
--- /dev/null
+++ b/verilog/fpu/fpu_2.v.add.bak
@@ -0,0 +1,54 @@
+`include "exp_calc.v"
+module fpu_2(
+ input wire add_not,
+ input wire[31:0] a_in, b_in,
+ output wire[31:0] out
+);
+
+wire[23:0] a_sig, b_sig, b_shft_sig, a_shft_sig, a_sign_sig, b_sign_sig;
+wire[24:0] sig_sum, sig_diff, sig_op, sig_final;
+wire[7:0] exp;
+wire[7:0] diff, neg_diff;
+wire same_sign;
+
+assign diff = a_in[30:23] - b_in[30:23];
+assign neg_diff = b_in[30:23] - a_in[30:23];
+assign exp = diff[7] ? b_in[30:23] : a_in[30:23];
+
+assign same_sign = ~(a_in[31] ^ b_in[31]);
+
+// Pull hidden bit into sig, if exp 0, no hidden bit
+assign a_sig = (|a_in[30:23] ? {1'b1, a_in[22:0]} : {1'b0, a_in[22:0]});
+assign b_sig = (|b_in[30:23] ? {1'b1, b_in[22:0]} : {1'b0, b_in[22:0]});
+
+assign a_shft_sig = (diff[7] ? a_sig >> neg_diff : a_sig);
+assign b_shft_sig = (diff[7] ? b_sig : b_sig >> diff);
+
+//2C Invert if Negative and not same signs
+assign a_sign_sig = same_sign ? a_shft_sig : (a_in[31] ? ~(a_shft_sig) + 24'b1 : a_shft_sig);
+assign b_sign_sig = same_sign ? b_shft_sig : (b_in[31] ? ~(b_shft_sig) + 24'b1 : b_shft_sig);
+
+//Adding
+assign sig_sum = a_sign_sig + b_sign_sig;
+
+//Subtraction
+assign sig_diff = a_shft_sig + ~(b_shft_sig) + 25'b1;
+
+assign sig_op = add_not ? sig_diff : sig_sum;
+assign sig_final = sig_op[24] | same_sign ? sig_op : ~(sig_op) + 24'b1;
+
+wire[24:0] sig_diff_final;
+wire[7:0] exp_diff;
+exp_calc exp_calc0(sig_final,exp,sig_diff_final,exp_diff);
+
+
+// Assign exp and mantissa
+assign out[31] = a_shft_sig > b_shft_sig ? a_in[31] : b_in[31];
+assign out[30:23] = sig_final[24] & same_sign ? exp + 8'b1 : (same_sign ? exp : exp_diff);
+assign out[22:0] = sig_final[24] & same_sign ? sig_final[23:1] : (same_sign ? sig_final[22:0] : sig_diff_final[22:0]);
+
+/* assign out = {exp_diff, 24'b0}; */
+// assign out = {diff, neg_diff, 16'b0};
+/* assign out = {sig_op, 7'b0}; */
+
+endmodule
diff --git a/verilog/fpu/fpu_3.v b/verilog/fpu/fpu_3.v
new file mode 100644
index 0000000..69c7cec
--- /dev/null
+++ b/verilog/fpu/fpu_3.v
@@ -0,0 +1,36 @@
+module fpu_3(
+ input wire add_not,
+ input wire [31:0] a_in, b_in,
+ output wire[31:0] out
+);
+
+wire[7:0] diff, neg_diff, exp;
+assign diff = a_in[30:23] - b_in[30:23];
+assign neg_diff = b_in[30:23] - a_in[30:23];
+assign exp = diff[7] ? b_in[30:23] : a_in[30:23];
+
+// Pull hidden bit into sig, if exp 0, no hidden bit
+wire[23:0] a_sig, b_sig;
+assign a_sig = (|a_in[30:23] ? {1'b1, a_in[22:0]} : {1'b0, a_in[22:0]});
+assign b_sig = (|b_in[30:23] ? {1'b1, b_in[22:0]} : {1'b0, b_in[22:0]});
+
+//Denormalize correct one
+wire[23:0] a_shift_sig, b_shift_sig;
+assign a_shift_sig = (diff[7] ? a_sig >> neg_diff : a_sig);
+assign b_shift_sig = (diff[7] ? b_sig : b_sig >> diff);
+
+// Set signed based on inputs and signs
+wire[23:0] a_signed_sig, b_signed_sig;
+assign a_signed_sig = b[31] & (~(add_not ^ b_in[31])) ? ~a_shift_sig + 1'b1 : a_shift_sig;
+assign b_signed_sig = ~a[31] & (add_not ^ b_in[31]) ? ~b_shift_sig + 1'b1; : b_shift_sig;
+
+
+wire[24:0] sum_sig;
+assign sum_sig = a_signed_sig + b_signed_sig;
+
+wire[24:0] signed_sum_sig;
+assign signed_sum_sig = ~(a_in[31] ^ b_in[31]) ? sum_sig :
+
+assign out[31] = ;
+
+endmodule
diff --git a/verilog/fpu/fpu_bench.v b/verilog/fpu/fpu_bench.v
new file mode 100644
index 0000000..ecbd659
--- /dev/null
+++ b/verilog/fpu/fpu_bench.v
@@ -0,0 +1,58 @@
+`timescale 1us/1ns
+
+`include "fpu_2.v"
+
+module fpu_bench;
+
+reg[31:0] input1, input2;
+reg add = 1'b0;
+wire[31:0] fpu_output;
+
+fpu_2 fpu0 (add,input1, input2, fpu_output);
+
+initial begin
+
+ input1=32'b01000000000111001100110011001101; // 2.45
+ input2=32'b00111111001001100110011001100110; //.65
+ #5;
+ $display("\nSum: %16b + %16b = %16b",input1,input2,fpu_output);
+
+ input1=32'b01000000000111001100110011001101; // 2.45
+ input2=32'b10111111001001100110011001100110; //.65
+ #5;
+ $display("\nSum: %16b + %16b = %16b",input1,input2,fpu_output);
+
+ input1=32'b11000000000111001100110011001101; // 2.45
+ input2=32'b00111111001001100110011001100110; //.65
+ #5;
+ $display("\nSum: %16b + %16b = %16b",input1,input2,fpu_output);
+
+ input1=32'b11000000000111001100110011001101; // 2.45
+ input2=32'b10111111001001100110011001100110; //.65
+ #5;
+ $display("\nSum: %16b + %16b = %16b",input1,input2,fpu_output);
+
+ add = 1'b1;
+
+ input1=32'b01000000000111001100110011001101; // 2.45
+ input2=32'b00111111001001100110011001100110; //.65
+ #5;
+ $display("\nSum: %16b - %16b = %16b",input1,input2,fpu_output);
+
+ input1=32'b01000000000111001100110011001101; // 2.45
+ input2=32'b10111111001001100110011001100110; //.65
+ #5;
+ $display("\nSum: %16b - %16b = %16b",input1,input2,fpu_output);
+
+ input1=32'b11000000000111001100110011001101; // 2.45
+ input2=32'b00111111001001100110011001100110; //.65
+ #5;
+ $display("\nSum: %16b - %16b = %16b",input1,input2,fpu_output);
+
+ input1=32'b11000000000111001100110011001101; // 2.45
+ input2=32'b10111111001001100110011001100110; //.65
+ #5;
+ $display("\nSum: %16b - %16b = %16b",input1,input2,fpu_output);
+ $finish;
+end
+endmodule
diff --git a/verilog/riscv_alu.v b/verilog/riscv_alu.v
new file mode 100644
index 0000000..87dd637
--- /dev/null
+++ b/verilog/riscv_alu.v
@@ -0,0 +1,39 @@
+module riscv_alu
+(
+input wire signed [31:0] alu_in_1,
+input wire[31:0] alu_in_2,
+input wire[3:0] alu_op_i,
+output wire[31:0] alu_output
+);
+
+reg[31:0] tmp_out;
+`include "alu_ops.vh"
+
+wire [31:0] sub_alu = alu_in_1 - alu_in_2;
+
+always @(*)
+begin
+ case (alu_op_i)
+ `ADD: tmp_out = alu_in_1 + alu_in_2;
+ `SUB: tmp_out = sub_alu;
+ `XOR: tmp_out = alu_in_1 ^ alu_in_2;
+ `OR: tmp_out = alu_in_1 | alu_in_2;
+ `AND: tmp_out = alu_in_1 & alu_in_2;
+ `SLL: tmp_out = alu_in_1 << alu_in_2;
+ `SRL: tmp_out = alu_in_1 >> alu_in_2;
+ `SRA: tmp_out = alu_in_1 >>> alu_in_2;
+ `SLT: tmp_out = (alu_in_1 < alu_in_2) ? 32'h1 : 32'h0;
+ `SLTU:
+ begin
+ if (alu_in_1[31] != alu_in_2[31])
+ tmp_out = alu_in_1[31] ? 32'h1 : 32'h0;
+ else
+ tmp_out = sub_alu[31] ? 32'h1 : 32'h0;
+ end
+ default: tmp_out = alu_in_1;
+ endcase
+end
+
+assign alu_output = tmp_out;
+
+endmodule
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