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`timescale 1us/1ns
`include "riscv_alu.v"
`include "alu_ops.vh"
module bench_alu;
reg [3:0] op;
reg [31:0] input1, input2;
wire [31:0] alu_out;
riscv_alu alu0 (input1, input2, op, alu_out);
initial begin
op=`SLT;
input1=32'hA;
input2=32'hD;
#50
$display("\nALU OP AND: %d %16b + %d %16b = %d %b", $signed(input1), input1, $signed(input2), input2, $signed(alu_out), alu_out);
$finish;
end
endmodule
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