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| author | joshua <joshua@joshuayun.com> | 2022-04-16 23:00:55 -0500 |
|---|---|---|
| committer | joshua <joshua@joshuayun.com> | 2022-04-16 23:00:55 -0500 |
| commit | d6b7d26cf51b4b3a7b5604f9b81bb43f55cbc33c (patch) | |
| tree | c337d4454d3a4d5aa01ad3531e8c723b09fe7d0e /verilog/bench_alu.v | |
| parent | 2f1be3c7aabb42ac3ad4347595d5d7be0e2ad6a0 (diff) | |
| download | riscv-processor-inorder-d6b7d26cf51b4b3a7b5604f9b81bb43f55cbc33c.tar.gz | |
Added pdfs and more alu stuff
Diffstat (limited to 'verilog/bench_alu.v')
| -rw-r--r-- | verilog/bench_alu.v | 23 |
1 files changed, 0 insertions, 23 deletions
diff --git a/verilog/bench_alu.v b/verilog/bench_alu.v deleted file mode 100644 index 9c0140c..0000000 --- a/verilog/bench_alu.v +++ /dev/null @@ -1,23 +0,0 @@ -`timescale 1us/1ns - -`include "riscv_alu.v" -`include "alu_ops.vh" - -module bench_alu; - -reg [3:0] op; -reg [31:0] input1, input2; -wire [31:0] alu_out; - -riscv_alu alu0 (input1, input2, op, alu_out); - -initial begin - op=`SLT; - input1=32'hA; - input2=32'hD; - #50 - $display("\nALU OP AND: %d %16b + %d %16b = %d %b", $signed(input1), input1, $signed(input2), input2, $signed(alu_out), alu_out); - $finish; -end - -endmodule |