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| author | Joshua Yun <jjyun4@illinois.edu> | 2023-08-28 14:42:23 -0500 |
|---|---|---|
| committer | Joshua Yun <jjyun4@illinois.edu> | 2023-08-28 14:42:23 -0500 |
| commit | c1fa3c36da28e9e947f6279329c47777f31fe7a2 (patch) | |
| tree | bd321c8e33200427b23bffe96c7c1bae90d8a044 /verilog/data_mem.mem | |
| parent | d069ea63cce08c0f5c8d7da7f8ab05115bd8d856 (diff) | |
| download | riscv-processor-inorder-master.tar.gz | |
Diffstat (limited to 'verilog/data_mem.mem')
| -rw-r--r-- | verilog/data_mem.mem | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/verilog/data_mem.mem b/verilog/data_mem.mem new file mode 100644 index 0000000..d3d39ad --- /dev/null +++ b/verilog/data_mem.mem @@ -0,0 +1,59 @@ +00010203 // 0x00 +04050607 // 0x04 +08090A0B // 0x08 +0C0D0E0F // 0x0C +10111213 // 0x10 +14151617 // 0x14 +18191A1B // 0x08 +1C1D1E1F // 0x1C +00000000 // Zero Buffer +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 |