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authorJoshua Yun <jjyun4@illinois.edu>2023-08-28 14:42:23 -0500
committerJoshua Yun <jjyun4@illinois.edu>2023-08-28 14:42:23 -0500
commitc1fa3c36da28e9e947f6279329c47777f31fe7a2 (patch)
treebd321c8e33200427b23bffe96c7c1bae90d8a044 /verilog/instr_mem.mem
parentd069ea63cce08c0f5c8d7da7f8ab05115bd8d856 (diff)
downloadriscv-processor-inorder-master.tar.gz
Added new riscv processor design into git repoHEADmaster
Diffstat (limited to 'verilog/instr_mem.mem')
-rw-r--r--verilog/instr_mem.mem55
1 files changed, 55 insertions, 0 deletions
diff --git a/verilog/instr_mem.mem b/verilog/instr_mem.mem
new file mode 100644
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--- /dev/null
+++ b/verilog/instr_mem.mem
@@ -0,0 +1,55 @@
+01000093
+01234137
+00001197
+02000213
+03000293
+00000013 // NOP Buffer
+00000013
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