Added new riscv processor design into git repoHEADmaster

1 files changed, 20 insertions, 0 deletions

diff --git a/verilog/pc.v b/verilog/pc.v
new file mode 100644
index 0000000..a7c6b6d
--- /dev/null
+++ b/verilog/pc.v
@@ -0,0 +1,20 @@
+`default_nettype none
+`timescale 1ns/1ps
+
+module pc
+(
+	input wire we, clk, rst,
+	input wire [31:0] pc_new,
+	output reg [31:0] pc
+);
+
+always @ (posedge clk or posedge rst) begin
+	if (rst) begin
+		pc <= 0;
+	end
+	else if (we) begin
+		pc <= pc_new;
+	end
+end
+
+endmodule