summaryrefslogtreecommitdiff
path: root/verilog/register/registers.v
diff options
context:
space:
mode:
authorJoshua Yun <jjyun4@illinois.edu>2023-08-28 14:42:23 -0500
committerJoshua Yun <jjyun4@illinois.edu>2023-08-28 14:42:23 -0500
commitc1fa3c36da28e9e947f6279329c47777f31fe7a2 (patch)
treebd321c8e33200427b23bffe96c7c1bae90d8a044 /verilog/register/registers.v
parentd069ea63cce08c0f5c8d7da7f8ab05115bd8d856 (diff)
downloadriscv-processor-inorder-c1fa3c36da28e9e947f6279329c47777f31fe7a2.tar.gz
Added new riscv processor design into git repoHEADmaster
Diffstat (limited to 'verilog/register/registers.v')
-rw-r--r--verilog/register/registers.v22
1 files changed, 0 insertions, 22 deletions
diff --git a/verilog/register/registers.v b/verilog/register/registers.v
deleted file mode 100644
index f2dbb22..0000000
--- a/verilog/register/registers.v
+++ /dev/null
@@ -1,22 +0,0 @@
-module registers(
- input wire writeEnable,
- input wire clk,
- input wire [31:0] addr1,
- input wire [31:0] addr2,
- input wire [31:0] addr3,
- input wire [31:0] writeData,
- output wire [31:0] readData1,
- output wire [31:0] readData2
-);
-
-reg [31:0] register [0:31];
-
-always @ (posedge clk)
-begin
- register[addr3] <= writeEnable ? writeData : register[addr3];
-end
-
-assign readData1 = register[addr1];
-assign readData2 = register[addr2];
-
-endmodule