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authorfunctionpointersuss <joshua@joshuayun.com>2023-12-23 13:36:04 +0800
committerfunctionpointersuss <joshua@joshuayun.com>2023-12-23 13:36:04 +0800
commitdec5747241d15fca0b94117205a139b4ba692a9d (patch)
treec7e61055b703eef47bbf032d252135cc1d1c592e /multiplier/Makefile
parent5b04327dfa7a3005819045c9cc19e558e86d59d5 (diff)
downloadriscv-processor-dec5747241d15fca0b94117205a139b4ba692a9d.tar.gz
updated gitignore, updated testbench, added beginnings of synthesis testing
Diffstat (limited to 'multiplier/Makefile')
-rw-r--r--multiplier/Makefile13
1 files changed, 7 insertions, 6 deletions
diff --git a/multiplier/Makefile b/multiplier/Makefile
index 9bd8160..bfebb5e 100644
--- a/multiplier/Makefile
+++ b/multiplier/Makefile
@@ -1,6 +1,6 @@
SHELL = /bin/bash -o pipefail
-TOP_TB_SRCS := $(PWD)/hvl/tb_top.sv $(PWD)/hdl/multiplier.sv $(PWD)/hdl/sm.sv $(PWD)/hdl/ff_array.sv
+MULTIPLIER_TB_SRCS := $(PWD)/hvl/tb_multiplier.sv $(PWD)/hdl/*.sv
export REPORT_DIR = reports
@@ -9,19 +9,20 @@ export SYN_OUT_DIR = ./syn/synout
VCS_FLAGS= -full64 -lca -sverilog +lint=none,noNS -timescale=1ns/1ns -debug_acc+all -kdb -fsdb -j4 +notimingcheck
VCS_FLAGS_POST = -full64 -lca -sverilog +lint=none -timescale=1ns/1ns -debug_acc+all -kdb -fsdb +neg_tchk -negdelay +compsdf +mindelays +sdfverbose -j4 -fgp
-tree:
- ./gen_wallace.py 32 -a
-sim/top_tb: $(TOP_TB_SRCS)
+sim/tb_multiplier: $(TOP_TB_SRCS)
mkdir -p sim
- cd sim && vcs $(TOP_TB_SRCS) $(VCS_FLAGS) -l top_compile.log -o top_tb
+ cd sim && vcs $(MULTIPLIER_TB_SRCS) $(VCS_FLAGS) -l top_compile.log -o top_tb
cd sim && ./top_tb -l top_simulation.log
synth: synth_clean
mkdir -p $(REPORT_DIR) $(SYN_OUT_DIR)
- dc_shell-xg-t -64bit -f dc_syn.tcl |& tee $(REPORT_DIR)/synthesis.log
+ dc_shell-xg-t -64bit -f synthesis.tcl |& tee $(REPORT_DIR)/synthesis.log
$(MAKE) smol_clean
+tree:
+ ./gen_wallace.py 32 -a
+
.PHONY: verdi
verdi:
mkdir -p verdi