updated gitignore, updated testbench, added beginnings of synthesis testing

4 files changed, 168 insertions, 6 deletions

diff --git a/multiplier/Makefile b/multiplier/Makefile
index 9bd8160..bfebb5e 100644
--- a/multiplier/Makefile
+++ b/multiplier/Makefile
@@ -1,6 +1,6 @@
 SHELL = /bin/bash -o pipefail
 
-TOP_TB_SRCS   := $(PWD)/hvl/tb_top.sv   $(PWD)/hdl/multiplier.sv  $(PWD)/hdl/sm.sv  $(PWD)/hdl/ff_array.sv
+MULTIPLIER_TB_SRCS   := $(PWD)/hvl/tb_multiplier.sv  $(PWD)/hdl/*.sv
 
 
 export REPORT_DIR			= reports
@@ -9,19 +9,20 @@ export SYN_OUT_DIR			= ./syn/synout
 VCS_FLAGS= -full64 -lca -sverilog +lint=none,noNS -timescale=1ns/1ns -debug_acc+all -kdb -fsdb -j4 +notimingcheck
 VCS_FLAGS_POST = -full64 -lca -sverilog +lint=none -timescale=1ns/1ns -debug_acc+all -kdb -fsdb +neg_tchk -negdelay +compsdf +mindelays +sdfverbose -j4 -fgp
 
-tree:
-	./gen_wallace.py 32 -a
 
-sim/top_tb: $(TOP_TB_SRCS)
+sim/tb_multiplier: $(TOP_TB_SRCS)
 	mkdir -p sim
-	cd sim && vcs $(TOP_TB_SRCS) $(VCS_FLAGS) -l top_compile.log -o top_tb
+	cd sim && vcs $(MULTIPLIER_TB_SRCS) $(VCS_FLAGS) -l top_compile.log -o top_tb
 	cd sim && ./top_tb -l top_simulation.log
 
 synth: synth_clean
 	mkdir -p $(REPORT_DIR) $(SYN_OUT_DIR)
-	dc_shell-xg-t -64bit -f dc_syn.tcl |& tee $(REPORT_DIR)/synthesis.log
+	dc_shell-xg-t -64bit -f synthesis.tcl |& tee $(REPORT_DIR)/synthesis.log
 	$(MAKE) smol_clean
 
+tree:
+	./gen_wallace.py 32 -a
+
 .PHONY: verdi 
 verdi:
 	mkdir -p verdi
diff --git a/multiplier/hdl/half_adder.v b/multiplier/hdl/half_adder.sv
index a322900..a322900 100644
--- a/multiplier/hdl/half_adder.v
+++ b/multiplier/hdl/half_adder.sv
diff --git a/multiplier/hvl/tb_multiplier.sv b/multiplier/hvl/tb_multiplier.sv
new file mode 100644
index 0000000..f9dcf2c
--- /dev/null
+++ b/multiplier/hvl/tb_multiplier.sv
@@ -0,0 +1,48 @@
+`default_nettype none
+`timescale 1ns/1ps
+`define NUMTESTS 100000
+
+module tb_multiplier();
+
+logic [31:0] a;
+logic [31:0] b;
+logic [63:0] c;
+logic [63:0] product;
+
+multiplier dut (a, b, c);
+
+int i;
+initial begin
+
+	$fsdbDumpfile("dump.fsdb");
+	$fsdbDumpvars(0, "+all");
+
+	for (i = 0; i < `NUMTESTS; i=i+1) begin
+		a = $urandom();
+		b = $urandom();
+		product = a * b;
+		#10;
+		if (product != c) begin
+			$displayh("A: %0d", a);
+			$displayh("B: %0d", b);
+			$displayh("C: %0d", c);
+			$displayh("EXPTECTED: %0d", product);
+			$error("TEST FAILED");
+		end
+		else if (i % 1000 == 0) begin
+			$display("Test %d passed", i);
+			$displayh("A:         %0d", a);
+			$displayh("B:         %0d", b);
+			$displayh("C:         %0d", c);
+			$displayh("EXPTECTED: %0d", product);
+		end
+	end
+
+	$display("TEST PASSES");
+
+	$finish;
+end
+
+
+
+endmodule
diff --git a/multiplier/synthesis.tcl b/multiplier/synthesis.tcl
new file mode 100644
index 0000000..1a72191
--- /dev/null
+++ b/multiplier/synthesis.tcl
@@ -0,0 +1,113 @@
+set hdlin_ff_always_sync_set_reset true
+set hdlin_ff_always_async_set_reset true
+set hdlin_infer_multibit default_all
+set hdlin_check_no_latch true
+set_host_options -max_cores 4
+set_app_var report_default_significant_digits 6
+set design_toplevel mp4
+
+# output port '%s' is connected directly to output port '%s'
+suppress_message LINT-31
+# In design '%s', output port '%s' is connected directly to '%s'.
+suppress_message LINT-52
+# '%s' is not connected to any nets
+suppress_message LINT-28
+# output port '%s' is connected directly to output port '%s'
+suppress_message LINT-29
+# a pin on submodule '%s' is connected to logic 1 or logic 0
+suppress_message LINT-32
+# the same net is connected to more than one pin on submodule '%s'
+suppress_message LINT-33
+# '%s' is not connected to any nets
+suppress_message LINT-28
+# In design '%s', cell '%s' does not drive any nets.
+suppress_message LINT-1
+# There are %d potential problems in your design. Please run 'check_design' for more information.
+suppress_message LINT-99
+# In design '%s', net '%s' driven by pin '%s' has no loads.
+suppress_message LINT-2
+# The register '' is a constant and will be removed.
+suppress_message OPT-1206
+# The register '' will be removed.
+suppress_message OPT-1207
+# Can't read link_library file '%s'
+suppress_message UID-3
+# Design '%s' contains %d high-fanout nets.
+suppress_message TIM-134
+# The trip points for the library named %s differ from those in the library named %s.
+suppress_message TIM-164
+# Design has unannotated black box outputs.
+suppress_message PWR-428
+# Skipping clock gating on design %s, since there are no registers.
+suppress_message PWR-806
+# Ungrouping hierarchy %s before Pass 1.
+suppress_message OPT-776
+# Verilog 'assign' or 'tran' statements are written out.
+suppress_message VO-4
+# Verilog writer has added %d nets to module %s using %s as prefix.
+suppress_message VO-11
+
+# %s DEFAULT branch of CASE statement cannot be reached.
+suppress_message ELAB-311
+# Netlist for always_comb block is empty.
+suppress_message ELAB-982
+# Netlist for always_ff block is empty.
+suppress_message ELAB-984
+
+define_design_lib WORK -path ./work
+set alib_library_analysis_path [getenv STD_CELL_ALIB]
+
+set symbol_library [list generic.sdb]
+set synthetic_library [list dw_foundation.sldb]
+set target_library [getenv STD_CELL_LIB]
+set sram_library [getenv SRAM_LIB]
+
+if {$sram_library eq ""} {
+   set link_library [list "*" $target_library $synthetic_library]
+} else {
+   set link_library [list "*" $target_library $synthetic_library $sram_library]
+}
+
+set design_clock_pin clk
+set design_reset_pin rst
+
+analyze -library WORK -format sverilog [getenv PKG_SRCS]
+
+set modules [split [getenv HDL_SRCS] " "]
+foreach module $modules {
+   analyze -library WORK -format sverilog "${module}"
+}
+
+elaborate $design_toplevel
+current_design $design_toplevel
+check_design
+
+set_wire_load_model -name "5K_hvratio_1_1"
+set_wire_load_mode enclosed
+
+set clk_name $design_clock_pin
+set clk_period [expr [getenv CLOCK_PERIOD_PS] / 1000.0]
+create_clock -period $clk_period -name my_clk $clk_name
+set_fix_hold [get_clocks my_clk]
+
+set_input_delay 0.5 [all_inputs] -clock my_clk
+set_output_delay 0.5 [all_outputs] -clock my_clk
+set_load 0.1 [all_outputs]
+set_max_fanout 1 [all_inputs]
+set_fanout_load 8 [all_outputs]
+
+link
+
+# compile_ultra -gate_clock -retime
+compile
+
+current_design $design_toplevel
+
+report_area -hier > reports/area.rpt
+report_timing -delay max > reports/timing.rpt
+check_design > reports/check.rpt
+
+write_file -format ddc -hierarchy -output outputs/synth.ddc
+write_file -format verilog -hierarchy -output [format "outputs/%s.gate.v" $design_toplevel]
+
+exit