renamed to sv

8 files changed, 44 insertions, 106 deletions

diff --git a/multiplier/Makefile b/multiplier/Makefile
index d14a14f..9bd8160 100644
--- a/multiplier/Makefile
+++ b/multiplier/Makefile
@@ -1,10 +1,41 @@
-all: tree test
+SHELL = /bin/bash -o pipefail
+
+TOP_TB_SRCS   := $(PWD)/hvl/tb_top.sv   $(PWD)/hdl/multiplier.sv  $(PWD)/hdl/sm.sv  $(PWD)/hdl/ff_array.sv
+
+
+export REPORT_DIR			= reports
+export SYN_OUT_DIR			= ./syn/synout
+
+VCS_FLAGS= -full64 -lca -sverilog +lint=none,noNS -timescale=1ns/1ns -debug_acc+all -kdb -fsdb -j4 +notimingcheck
+VCS_FLAGS_POST = -full64 -lca -sverilog +lint=none -timescale=1ns/1ns -debug_acc+all -kdb -fsdb +neg_tchk -negdelay +compsdf +mindelays +sdfverbose -j4 -fgp
+
 tree:
 	./gen_wallace.py 32 -a
-test:
-	verilator --trace --cc --exe --build -j 0 -Wall tb_multiplier.cpp multiplier.v
-	./obj_dir/Vmultiplier
-synth:
-	yosys -p "read_verilog multiplier.v ; hierarchy -top multiplier -libdir . ; synth_ecp5"
-clean:
-	rm -rf log_* obj_dir
+
+sim/top_tb: $(TOP_TB_SRCS)
+	mkdir -p sim
+	cd sim && vcs $(TOP_TB_SRCS) $(VCS_FLAGS) -l top_compile.log -o top_tb
+	cd sim && ./top_tb -l top_simulation.log
+
+synth: synth_clean
+	mkdir -p $(REPORT_DIR) $(SYN_OUT_DIR)
+	dc_shell-xg-t -64bit -f dc_syn.tcl |& tee $(REPORT_DIR)/synthesis.log
+	$(MAKE) smol_clean
+
+.PHONY: verdi 
+verdi:
+	mkdir -p verdi
+	cd verdi && $(VERDI_HOME)/bin/verdi -ssf $(PWD)/sim/dump.fsdb
+
+.PHONY: synth_clean
+synth_clean: smol_clean
+	rm -f  synthesis.log
+	rm -rf $(REPORT_DIR)
+	rm -rf $(SYN_OUT_DIR)
+
+.PHONY: smol_clean
+smol_clean:
+	rm -f  command.log
+	rm -f  default.svf
+	rm -rf work
+
diff --git a/multiplier/full_adder.v b/multiplier/hdl/full_adder.sv
index 1238aa7..1238aa7 100644
--- a/multiplier/full_adder.v
+++ b/multiplier/hdl/full_adder.sv
diff --git a/multiplier/gen_wallace.py b/multiplier/hdl/gen_wallace.py
index ed5c4f5..579041f 100755
--- a/multiplier/gen_wallace.py
+++ b/multiplier/hdl/gen_wallace.py
@@ -3,7 +3,7 @@ import argparse
 
 def gen_half_adder():
 	print(f"---------- Half adder generation ----------")
-	f = open(f"half_adder.v", "w")
+	f = open(f"half_adder.sv", "w")
 	f.write(f"""module half_adder (
 	input logic a,
 	input logic b,
@@ -20,7 +20,7 @@ endmodule
 
 def gen_full_adder():
 	print(f"---------- Full adder generation ----------")
-	f = open(f"full_adder.v", "w")
+	f = open(f"full_adder.sv", "w")
 	f.write(f"""module full_adder (
 	input logic a,
 	input logic b,
@@ -38,7 +38,7 @@ endmodule
 
 def gen_multiplier(bits):
 	print(f"\n---------- {bits} Bit Top Level Multiplier Generation ----------")
-	f = open(f"multiplier.v", "w")
+	f = open(f"multiplier.sv", "w")
 	f.write(f"""module multiplier(
 	input  logic [{bits-1}:0] a,
 	input  logic [{bits-1}:0] b,
@@ -59,7 +59,7 @@ endmodule
 
 def gen_partial_products(bits):
 	print(f"------------ {bits} Bit Partial Products Generation ------------")
-	f = open(f"partial_products.v", "w")
+	f = open(f"partial_products.sv", "w")
 	f.write(f"""module partial_products
 (
 	input  logic [{bits-1}:0] a,
@@ -276,7 +276,7 @@ def gen_adder_tree(bits, debug):
 	bit_vector_0 = bit_vector_0[:-2] + "}"
 	bit_vector_1 = bit_vector_1[:-2] + "};"
 
-	f = open(f"wallace_adder.v", "w")
+	f = open(f"wallace_adder.sv", "w")
 
 	# Start by printing module declaration
 	f.write(f"module wallace_adder (\n")
diff --git a/multiplier/half_adder.v b/multiplier/hdl/half_adder.v
index a322900..a322900 100644
--- a/multiplier/half_adder.v
+++ b/multiplier/hdl/half_adder.v
diff --git a/multiplier/multiplier.v b/multiplier/hdl/multiplier.sv
index 0522800..0522800 100644
--- a/multiplier/multiplier.v
+++ b/multiplier/hdl/multiplier.sv
diff --git a/multiplier/partial_products.v b/multiplier/hdl/partial_products.sv
index e05c859..e05c859 100644
--- a/multiplier/partial_products.v
+++ b/multiplier/hdl/partial_products.sv
diff --git a/multiplier/wallace_adder.v b/multiplier/hdl/wallace_adder.sv
index 34c9ecd..34c9ecd 100644
--- a/multiplier/wallace_adder.v
+++ b/multiplier/hdl/wallace_adder.sv
diff --git a/multiplier/tb_multiplier.cpp b/multiplier/tb_multiplier.cpp
deleted file mode 100644
index 040df80..0000000
--- a/multiplier/tb_multiplier.cpp
+++ /dev/null
@@ -1,93 +0,0 @@
-#include <iostream>
-#include <iomanip>
-#include <bitset>
-#include <cstdint>
-
-#include "Vmultiplier.h"
-#include "verilated.h"
-
-#define BITWIDTH 32
-
-int main(int argc, char** argv, char** env) {
-
-	if (false && argc && argv && env) {}
-
-	Verilated::mkdir("logs");
-	VerilatedContext* contextp = new VerilatedContext;
-
-	contextp->debug(0);
-	contextp->randReset(2);
-	contextp->traceEverOn(true);
-	contextp->commandArgs(argc, argv);
-
-	Vmultiplier* dut = new Vmultiplier{contextp};
-
-	uint32_t testsize = 0x1000;
-
-	for (int i = 0; i < testsize; i++) {
-		for (int j = 0; j < testsize; j++) {
-			dut->a = (uint32_t) i;
-			dut->b = (uint32_t) j;
-			unsigned int answer = (unsigned int) (i * j);
-
-			dut->eval();
-			if (answer != dut->c) {
-				std::bitset<BITWIDTH> in1(dut->a);
-				std::bitset<BITWIDTH> in2(dut->b);
-				std::bitset<BITWIDTH*2> expected(answer);
-				std::bitset<BITWIDTH*2> actual(dut->c);
-				std::cout << "Inputs: 1: " << in1 << " 2: " << in2 << '\n';
-				std::cout << "Expected: " << expected << '\n';
-				std::cout << "Actual: " << actual << '\n';
-				return -1;
-			}
-		}
-	}
-
-
-	std::cout << "LOWER HALF PASSED\n";
-
-	uint64_t top = 1;
-	for (int i = 1; i < BITWIDTH; i++) {
-		top <<= 1;
-		top |= 1;
-	}
-	uint64_t bottom = top - testsize;
-
-	for (uint64_t i = bottom; i < top; i++) {
-		for (uint64_t j = bottom; j < top; j++) {
-
-			dut->a = (uint32_t) i;
-			dut->b = (uint32_t) j;
-
-			uint64_t answer = i * j;
-
-			dut->eval();
-			if (answer != dut->c) {
-				std::bitset<BITWIDTH> in1(dut->a);
-				std::bitset<BITWIDTH> in2(dut->b);
-				std::bitset<BITWIDTH*2> expected(answer);
-				std::bitset<BITWIDTH*2> actual(dut->c);
-				std::cout << "In 1: " << in1 << '\n';
-				std::cout << "In 2: " << in2 << '\n';
-				std::cout << "Expected: " << expected << '\n';
-				std::cout << "Actual:   " << actual << '\n';
-
-				std::cout << "In 1: " << std::hex << (uint32_t) dut->a  << '\n';
-				std::cout << "In 2: " << std::hex << (uint32_t) dut->b << '\n';
-				std::cout << "Expected: " << std::hex << (uint64_t) answer << '\n';
-				std::cout << "Actual:   " << std::hex << (uint64_t) dut->c << '\n';
-				return -1;
-			}
-		}
-	}
-
-	std::cout << "UPPER HALF PASSED\n";
-
-
-	std::cout << "Test Passed for " << BITWIDTH <<  " bit multiplier\n";
-
-	delete dut;
-	delete contextp;
-	return 0;
-}