updated gitignore, updated testbench, added beginnings of synthesis testing

1 files changed, 11 insertions, 0 deletions

diff --git a/multiplier/hdl/half_adder.sv b/multiplier/hdl/half_adder.sv
new file mode 100644
index 0000000..a322900
--- /dev/null
+++ b/multiplier/hdl/half_adder.sv
@@ -0,0 +1,11 @@
+module half_adder (
+	input logic a,
+	input logic b,
+	output logic sum,
+	output logic carry
+);
+
+assign sum = a ^ b;
+assign carry = a & b;
+
+endmodule