diff options
| author | joshua <joshua@joshuayun.com> | 2023-12-30 23:54:31 -0500 |
|---|---|---|
| committer | joshua <joshua@joshuayun.com> | 2023-12-30 23:54:31 -0500 |
| commit | 86608c6770cf08c138a2bdab5855072f64be09ef (patch) | |
| tree | 494a61b3ef37e76f9235a0d10f5c93d97290a35f /Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device | |
| download | sdr-software-master.tar.gz | |
Diffstat (limited to 'Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device')
5 files changed, 625 insertions, 0 deletions
diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/mem_ARMCA5.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/mem_ARMCA5.h new file mode 100644 index 0000000..96fc081 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/mem_ARMCA5.h @@ -0,0 +1,94 @@ +/**************************************************************************//**
+ * @file mem_ARMCA5.h
+ * @brief Memory base and size definitions (used in scatter file)
+ * @version V1.00
+ * @date 10. January 2018
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MEM_ARMCA5_H
+#define __MEM_ARMCA5_H
+
+/*----------------------------------------------------------------------------
+ User Stack & Heap size definition
+ *----------------------------------------------------------------------------*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- ROM Configuration ------------------------------------
+//
+// <h> ROM Configuration
+// <o0> ROM Base Address <0x0-0xFFFFFFFF:8>
+// <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE 0x80000000
+#define __ROM_SIZE 0x00200000
+
+/*--------------------- RAM Configuration -----------------------------------
+// <h> RAM Configuration
+// <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
+// <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <h> Stack / Heap Configuration
+// <o4> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o5> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <h> Exceptional Modes
+// <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+// </h>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE 0x80200000
+#define __RAM_SIZE 0x00200000
+
+#define __RW_DATA_SIZE 0x00100000
+#define __ZI_DATA_SIZE 0x000F0000
+
+#define __STACK_SIZE 0x00001000
+#define __HEAP_SIZE 0x00008000
+
+#define __UND_STACK_SIZE 0x00000100
+#define __ABT_STACK_SIZE 0x00000100
+#define __SVC_STACK_SIZE 0x00000100
+#define __IRQ_STACK_SIZE 0x00000100
+#define __FIQ_STACK_SIZE 0x00000100
+
+/*----------------------------------------------------------------------------*/
+
+/*--------------------- TTB Configuration ------------------------------------
+//
+// <h> TTB Configuration
+// <o0> TTB Base Address <0x0-0xFFFFFFFF:8>
+// <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __TTB_BASE 0x80500000
+#define __TTB_SIZE 0x00004000
+
+#endif /* __MEM_ARMCA5_H */
diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/mmu_ARMCA5.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/mmu_ARMCA5.c new file mode 100644 index 0000000..91f1432 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/mmu_ARMCA5.c @@ -0,0 +1,235 @@ +/**************************************************************************//**
+ * @file mmu_ARMCA5.c
+ * @brief MMU Configuration for ARM Cortex-A5 Device Series
+ * @version V1.1.0
+ * @date 23. November 2018
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 ARM Cortex-A Series memory map
+
+ Memory Type
+0xffffffff |--------------------------| ------------
+ | FLAG SYNC | Device Memory
+0xfffff000 |--------------------------| ------------
+ | Fault | Fault
+0xfff00000 |--------------------------| ------------
+ | | Normal
+ | |
+ | Daughterboard |
+ | memory |
+ | |
+0x80505000 |--------------------------| ------------
+ |TTB (L2 Sync Flags ) 4k | Normal
+0x80504C00 |--------------------------| ------------
+ |TTB (L2 Peripherals-B) 16k| Normal
+0x80504800 |--------------------------| ------------
+ |TTB (L2 Peripherals-A) 16k| Normal
+0x80504400 |--------------------------| ------------
+ |TTB (L2 Priv Periphs) 4k | Normal
+0x80504000 |--------------------------| ------------
+ | TTB (L1 Descriptors) | Normal
+0x80500000 |--------------------------| ------------
+ | Heap | Normal
+ |--------------------------| ------------
+ | Stack | Normal
+0x80400000 |--------------------------| ------------
+ | ZI Data | Normal
+0x80300000 |--------------------------| ------------
+ | RW Data | Normal
+0x80200000 |--------------------------| ------------
+ | RO Data | Normal
+ |--------------------------| ------------
+ | RO Code | USH Normal
+0x80000000 |--------------------------| ------------
+ | Daughterboard | Fault
+ | HSB AXI buses |
+0x40000000 |--------------------------| ------------
+ | Daughterboard | Fault
+ | test chips peripherals |
+0x2c002000 |--------------------------| ------------
+ | Private Address | Device Memory
+0x2c000000 |--------------------------| ------------
+ | Daughterboard | Fault
+ | test chips peripherals |
+0x20000000 |--------------------------| ------------
+ | Peripherals | Device Memory RW/RO
+ | | & Fault
+0x00000000 |--------------------------|
+*/
+
+// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
+// Write-Through support *not* available
+// Write-Back support available.
+// Read allocation support available.
+// Write allocation support available.
+
+//Note: You should use the Shareable attribute carefully.
+//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
+//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
+//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
+
+//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
+//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
+//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
+
+
+//Following MMU configuration is expected
+//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
+//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
+//Domain 0 is always the Client domain
+//Descriptors should place all memory in domain 0
+
+#include "ARMCA5.h"
+
+
+// L2 table pointers
+//----------------------------------------
+#define PRIVATE_TABLE_L2_BASE_4k (0x80504000) //Map 4k Private Address space
+#define SYNC_FLAGS_TABLE_L2_BASE_4k (0x80504C00) //Map 4k Flag synchronization
+#define PERIPHERAL_A_TABLE_L2_BASE_64k (0x80504400) //Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF
+#define PERIPHERAL_B_TABLE_L2_BASE_64k (0x80504800) //Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF
+
+//--------------------- PERIPHERALS -------------------
+#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M)
+#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M)
+
+//--------------------- SYNC FLAGS --------------------
+#define FLAG_SYNC 0xFFFFF000
+#define F_SYNC_BASE 0xFFF00000 //1M aligned
+
+//Import symbols from linker
+extern uint32_t Image$$VECTORS$$Base;
+extern uint32_t Image$$RW_DATA$$Base;
+extern uint32_t Image$$ZI_DATA$$Base;
+extern uint32_t Image$$TTB$$ZI$$Base;
+
+static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
+static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
+static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable
+static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable
+static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0
+static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable
+
+/* Define global descriptors */
+static uint32_t Page_L1_4k = 0x0; //generic
+static uint32_t Page_L1_64k = 0x0; //generic
+static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0
+static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
+
+void MMU_CreateTranslationTable(void)
+{
+ mmu_region_attributes_Type region;
+
+ //Create 4GB of faulting entries
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
+
+ /*
+ * Generate descriptors. Refer to core_ca.h to get information about attributes
+ *
+ */
+ //Create descriptors for Vectors, RO, RW, ZI sections
+ section_normal(Sect_Normal, region);
+ section_normal_cod(Sect_Normal_Cod, region);
+ section_normal_ro(Sect_Normal_RO, region);
+ section_normal_rw(Sect_Normal_RW, region);
+ //Create descriptors for peripherals
+ section_device_ro(Sect_Device_RO, region);
+ section_device_rw(Sect_Device_RW, region);
+ //Create descriptors for 64k pages
+ page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
+ //Create descriptors for 4k pages
+ page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
+
+
+ /*
+ * Define MMU flat-map regions and attributes
+ *
+ */
+
+ //Define Image
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, 2, Sect_Normal_Cod);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, 1, Sect_Normal_RW);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base, 1, Sect_Normal_RW);
+
+ //all DRAM executable, rw, cacheable - applications may choose to divide memory into ro executable
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$TTB$$ZI$$Base, 2043, Sect_Normal);
+
+ //--------------------- PERIPHERALS -------------------
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_FLASH_BASE0 , 64, Sect_Device_RO);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_FLASH_BASE1 , 64, Sect_Device_RO);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_SRAM_BASE , 64, Sect_Device_RW);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_VRAM_BASE , 32, Sect_Device_RW);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_ETHERNET_BASE , 16, Sect_Device_RW);
+ MMU_TTSection (&Image$$TTB$$ZI$$Base, VE_A5_MP_USB_BASE , 16, Sect_Device_RW);
+
+ // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_A_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
+ // Define peripheral range 0x1C000000-0x1C00FFFF
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_DAP_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_SYSTEM_REG_BASE, 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_SERIAL_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_AACI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_MMCI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_KMI0_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_UART_BASE , 4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_WDT_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+
+ // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_B_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
+ // Define peripheral range 0x1C100000-0x1C10FFFF
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_TIMER_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_DVI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_RTC_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_UART4_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+ MMU_TTPage64k(&Image$$TTB$$ZI$$Base, VE_A5_MP_CLCD_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
+
+ // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory
+ MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR() ,256, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
+ // Define private address space entry.
+ MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR() , 3, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+ // Define L2CC entry. Uncomment if PL310 is present
+ // MMU_TTPage4k (&Image$$TTB$$ZI$$Base, VE_A5_MP_PL310_BASE , 1, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+
+ // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)
+ MMU_TTPage4k (&Image$$TTB$$ZI$$Base, F_SYNC_BASE , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
+ // Define synchronization space entry.
+ MMU_TTPage4k (&Image$$TTB$$ZI$$Base, FLAG_SYNC , 1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW);
+
+ /* Set location of level 1 page table
+ ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
+ ; 13:7 - 0x0
+ ; 6 - IRGN[0] 0x1 (Inner WB WA)
+ ; 5 - NOS 0x0 (Non-shared)
+ ; 4:3 - RGN 0x01 (Outer WB WA)
+ ; 2 - IMP 0x0 (Implementation Defined)
+ ; 1 - S 0x0 (Non-shared)
+ ; 0 - IRGN[1] 0x0 (Inner WB WA) */
+ __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 0x48);
+ __ISB();
+
+ /* Set up domain access control register
+ ; We set domain 0 to Client and all other domains to No Access.
+ ; All translation table entries specify domain 0 */
+ __set_DACR(1);
+ __ISB();
+}
diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/startup_ARMCA5.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/startup_ARMCA5.c new file mode 100644 index 0000000..19c343b --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/startup_ARMCA5.c @@ -0,0 +1,138 @@ +/******************************************************************************
+ * @file startup_ARMCA5.c
+ * @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series
+ * @version V1.00
+ * @date 10. January 2018
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <ARMCA5.h>
+
+/*----------------------------------------------------------------------------
+ Definitions
+ *----------------------------------------------------------------------------*/
+#define USR_MODE 0x10 // User mode
+#define FIQ_MODE 0x11 // Fast Interrupt Request mode
+#define IRQ_MODE 0x12 // Interrupt Request mode
+#define SVC_MODE 0x13 // Supervisor mode
+#define ABT_MODE 0x17 // Abort mode
+#define UND_MODE 0x1B // Undefined Instruction mode
+#define SYS_MODE 0x1F // System mode
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Vectors (void) __attribute__ ((naked, section("RESET")));
+void Reset_Handler (void) __attribute__ ((naked));
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+void Vectors(void) {
+ __ASM volatile(
+ "LDR PC, =Reset_Handler \n"
+ "LDR PC, =Undef_Handler \n"
+ "LDR PC, =SVC_Handler \n"
+ "LDR PC, =PAbt_Handler \n"
+ "LDR PC, =DAbt_Handler \n"
+ "NOP \n"
+ "LDR PC, =IRQ_Handler \n"
+ "LDR PC, =FIQ_Handler \n"
+ );
+}
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void) {
+ __ASM volatile(
+
+ // Mask interrupts
+ "CPSID if \n"
+
+ // Put any cores other than 0 to sleep
+ "MRC p15, 0, R0, c0, c0, 5 \n" // Read MPIDR
+ "ANDS R0, R0, #3 \n"
+ "goToSleep: \n"
+ "WFINE \n"
+ "BNE goToSleep \n"
+
+ // Reset SCTLR Settings
+ "MRC p15, 0, R0, c1, c0, 0 \n" // Read CP15 System Control register
+ "BIC R0, R0, #(0x1 << 12) \n" // Clear I bit 12 to disable I Cache
+ "BIC R0, R0, #(0x1 << 2) \n" // Clear C bit 2 to disable D Cache
+ "BIC R0, R0, #0x1 \n" // Clear M bit 0 to disable MMU
+ "BIC R0, R0, #(0x1 << 11) \n" // Clear Z bit 11 to disable branch prediction
+ "BIC R0, R0, #(0x1 << 13) \n" // Clear V bit 13 to disable hivecs
+ "MCR p15, 0, R0, c1, c0, 0 \n" // Write value back to CP15 System Control register
+ "ISB \n"
+
+ // Configure ACTLR
+ "MRC p15, 0, r0, c1, c0, 1 \n" // Read CP15 Auxiliary Control Register
+ "ORR r0, r0, #(1 << 1) \n" // Enable L2 prefetch hint (UNK/WI since r4p1)
+ "MCR p15, 0, r0, c1, c0, 1 \n" // Write CP15 Auxiliary Control Register
+
+ // Set Vector Base Address Register (VBAR) to point to this application's vector table
+ "LDR R0, =Vectors \n"
+ "MCR p15, 0, R0, c12, c0, 0 \n"
+
+ // Setup Stack for each exceptional mode
+ "CPS #0x11 \n"
+ "LDR SP, =Image$$FIQ_STACK$$ZI$$Limit \n"
+ "CPS #0x12 \n"
+ "LDR SP, =Image$$IRQ_STACK$$ZI$$Limit \n"
+ "CPS #0x13 \n"
+ "LDR SP, =Image$$SVC_STACK$$ZI$$Limit \n"
+ "CPS #0x17 \n"
+ "LDR SP, =Image$$ABT_STACK$$ZI$$Limit \n"
+ "CPS #0x1B \n"
+ "LDR SP, =Image$$UND_STACK$$ZI$$Limit \n"
+ "CPS #0x1F \n"
+ "LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit \n"
+
+ // Call SystemInit
+ "BL SystemInit \n"
+
+ // Unmask interrupts
+ "CPSIE if \n"
+
+ // Call __main
+ "BL __main \n"
+ );
+}
+
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+ while(1);
+}
diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/system_ARMCA5.c b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/system_ARMCA5.c new file mode 100644 index 0000000..cca3026 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/system_ARMCA5.c @@ -0,0 +1,93 @@ +/******************************************************************************
+ * @file system_ARMCA5.c
+ * @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series
+ * @version V1.0.1
+ * @date 13. February 2019
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+#include "irq_ctrl.h"
+
+#define SYSTEM_CLOCK 12000000U
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System Initialization
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+/* do not use global variables because this function is called before
+ reaching pre-main. RW section may be overwritten afterwards. */
+
+ // Invalidate entire Unified TLB
+ __set_TLBIALL(0);
+
+ // Invalidate entire branch predictor array
+ __set_BPIALL(0);
+ __DSB();
+ __ISB();
+
+ // Invalidate instruction cache and flush branch target cache
+ __set_ICIALLU(0);
+ __DSB();
+ __ISB();
+
+ // Invalidate data cache
+ L1C_InvalidateDCacheAll();
+
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+ // Enable FPU
+ __FPU_Enable();
+#endif
+
+ // Create Translation Table
+ MMU_CreateTranslationTable();
+
+ // Enable MMU
+ MMU_Enable();
+
+ // Enable Caches
+ L1C_EnableCaches();
+ L1C_EnableBTAC();
+
+#if (__L2C_PRESENT == 1)
+ // Enable GIC
+ L2C_Enable();
+#endif
+
+ // IRQ Initialize
+ IRQ_Initialize();
+}
diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/system_ARMCA5.h b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/system_ARMCA5.h new file mode 100644 index 0000000..4b61321 --- /dev/null +++ b/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/system_ARMCA5.h @@ -0,0 +1,65 @@ +/******************************************************************************
+ * @file system_ARMCA5.h
+ * @brief CMSIS Device System Header File for Arm Cortex-A5 Device Series
+ * @version V1.00
+ * @date 10. January 2018
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SYSTEM_ARMCA5_H
+#define __SYSTEM_ARMCA5_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ \brief Setup the microcontroller system.
+
+ Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+ \brief Update SystemCoreClock variable.
+
+ Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+ \brief Create Translation Table.
+
+ Creates Memory Management Unit Translation Table.
+ */
+extern void MMU_CreateTranslationTable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_ARMCA5_H */
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