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authorJoshua Yun <joshua@joshuayun.com>2024-07-10 00:19:30 -0500
committerJoshua Yun <joshua@joshuayun.com>2024-07-10 00:19:30 -0500
commit13d946fe67c56411bf22ea97ad323bf4d4f66ec6 (patch)
treedcb750f8426e623c8928d3e4b81429bbd7cb906c /projects/riscv/411-improvements.html
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downloadwebsite-13d946fe67c56411bf22ea97ad323bf4d4f66ec6.tar.gz
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+ <h2 class="title">Class Processor Improvements</h2>
+ <a class="back" href=riscv.html>&lt;-Back</a>
+ <p>
+ My groupmates and I made a Out of Order processor with a LSU, GShare Branch predictor, and Early branch resolution that supports RISCV-IM.
+ I will be writing about the further improvments that I make to the processor.
+ </p>
+</body>