Added new riscv processor design into git repoHEADmaster

1 files changed, 10 insertions, 0 deletions

diff --git a/verilog/Makefile b/verilog/Makefile
new file mode 100644
index 0000000..4775c0d
--- /dev/null
+++ b/verilog/Makefile
@@ -0,0 +1,10 @@
+datapath_test:
+	verilator --trace --cc --exe --build -j 0 -Wall tbdatapath.cpp datapath.v
+	./obj_dir/Vdatapath
+datapath_synth:
+	yosys -p "read_verilog datapath.v ; hierarchy -top datapath -libdir . ; synth_ecp5"
+clean:
+	rm -rf log_* obj_dir
+alu_test:
+	verilator --cc --exe --build -j 0 -Wall tbalu.cpp alu.v
+	./obj_dir/Valu