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| author | joshua <joshua@fedora.framework> | 2022-05-14 23:30:38 -0500 |
|---|---|---|
| committer | joshua <joshua@fedora.framework> | 2022-05-14 23:30:38 -0500 |
| commit | b8936029065835366e9e057a219c0c5194db8662 (patch) | |
| tree | 31e50944ac6e23850f92bb0e0f6d851b74307f60 /verilog/alu/v6/synth_alu6.v alu6.blif | |
| parent | d6b7d26cf51b4b3a7b5604f9b81bb43f55cbc33c (diff) | |
| download | riscv-processor-inorder-b8936029065835366e9e057a219c0c5194db8662.tar.gz | |
Verilog update
Diffstat (limited to 'verilog/alu/v6/synth_alu6.v alu6.blif')
| -rw-r--r-- | verilog/alu/v6/synth_alu6.v alu6.blif | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/verilog/alu/v6/synth_alu6.v alu6.blif b/verilog/alu/v6/synth_alu6.v alu6.blif new file mode 100644 index 0000000..8186d4c --- /dev/null +++ b/verilog/alu/v6/synth_alu6.v alu6.blif @@ -0,0 +1 @@ +# Generated by Yosys 0.15+70 (git sha1 48d7a6c47, gcc 11.2.0 -march=x86-64 -mtune=generic -O2 -fno-plt -fexceptions -fstack-clash-protection -fcf-protection -fPIC -Os) |