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| author | joshua <joshua@joshuayun.com> | 2022-04-16 23:00:55 -0500 |
|---|---|---|
| committer | joshua <joshua@joshuayun.com> | 2022-04-16 23:00:55 -0500 |
| commit | d6b7d26cf51b4b3a7b5604f9b81bb43f55cbc33c (patch) | |
| tree | c337d4454d3a4d5aa01ad3531e8c723b09fe7d0e /verilog/alu_ops.vh | |
| parent | 2f1be3c7aabb42ac3ad4347595d5d7be0e2ad6a0 (diff) | |
| download | riscv-processor-inorder-d6b7d26cf51b4b3a7b5604f9b81bb43f55cbc33c.tar.gz | |
Added pdfs and more alu stuff
Diffstat (limited to 'verilog/alu_ops.vh')
| -rw-r--r-- | verilog/alu_ops.vh | 14 |
1 files changed, 0 insertions, 14 deletions
diff --git a/verilog/alu_ops.vh b/verilog/alu_ops.vh deleted file mode 100644 index 258e124..0000000 --- a/verilog/alu_ops.vh +++ /dev/null @@ -1,14 +0,0 @@ -`ifndef ALU_OP -`define ALU_OP -`define NONE 4'b0000 -`define SLL 4'b0001 -`define SRL 4'b0010 -`define SRA 4'b0011 -`define ADD 4'b0100 -`define SUB 4'b0110 -`define AND 4'b0111 -`define OR 4'b1000 -`define XOR 4'b1001 -`define SLTU 4'b1010 -`define SLT 4'b1011 -`endif |