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| author | joshua <joshua@joshuayun.com> | 2021-12-14 01:46:40 -0600 |
|---|---|---|
| committer | joshua <joshua@joshuayun.com> | 2021-12-14 01:46:40 -0600 |
| commit | 9dc6d7180438031d25daf6a68a3959c3cfa9312d (patch) | |
| tree | e7bcab090bf1872392c0ca40e6128269136d42be /verilog/fpu/compile | |
| download | riscv-processor-inorder-9dc6d7180438031d25daf6a68a3959c3cfa9312d.tar.gz | |
Initial Commit
Diffstat (limited to 'verilog/fpu/compile')
| -rwxr-xr-x | verilog/fpu/compile | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/verilog/fpu/compile b/verilog/fpu/compile new file mode 100755 index 0000000..08b3b83 --- /dev/null +++ b/verilog/fpu/compile @@ -0,0 +1,4 @@ +#!/bin/sh + +iverilog fpu_bench.v +vvp a.out |