Initial Commit

1 files changed, 58 insertions, 0 deletions

diff --git a/verilog/fpu/fpu_bench.v b/verilog/fpu/fpu_bench.v
new file mode 100644
index 0000000..ecbd659
--- /dev/null
+++ b/verilog/fpu/fpu_bench.v
@@ -0,0 +1,58 @@
+`timescale 1us/1ns
+
+`include "fpu_2.v"
+
+module fpu_bench;
+
+reg[31:0] input1, input2;
+reg add = 1'b0;
+wire[31:0] fpu_output;
+
+fpu_2 fpu0 (add,input1, input2, fpu_output);
+
+initial begin
+
+	input1=32'b01000000000111001100110011001101; // 2.45
+	input2=32'b00111111001001100110011001100110; //.65
+	#5;
+	$display("\nSum: %16b + %16b = %16b",input1,input2,fpu_output);
+
+	input1=32'b01000000000111001100110011001101; // 2.45
+	input2=32'b10111111001001100110011001100110; //.65
+	#5;
+	$display("\nSum: %16b + %16b = %16b",input1,input2,fpu_output);
+
+	input1=32'b11000000000111001100110011001101; // 2.45
+	input2=32'b00111111001001100110011001100110; //.65
+	#5;
+	$display("\nSum: %16b + %16b = %16b",input1,input2,fpu_output);
+
+	input1=32'b11000000000111001100110011001101; // 2.45
+	input2=32'b10111111001001100110011001100110; //.65
+	#5;
+	$display("\nSum: %16b + %16b = %16b",input1,input2,fpu_output);
+
+	add = 1'b1;
+
+	input1=32'b01000000000111001100110011001101; // 2.45
+	input2=32'b00111111001001100110011001100110; //.65
+	#5;
+	$display("\nSum: %16b - %16b = %16b",input1,input2,fpu_output);
+
+	input1=32'b01000000000111001100110011001101; // 2.45
+	input2=32'b10111111001001100110011001100110; //.65
+	#5;
+	$display("\nSum: %16b - %16b = %16b",input1,input2,fpu_output);
+
+	input1=32'b11000000000111001100110011001101; // 2.45
+	input2=32'b00111111001001100110011001100110; //.65
+	#5;
+	$display("\nSum: %16b - %16b = %16b",input1,input2,fpu_output);
+
+	input1=32'b11000000000111001100110011001101; // 2.45
+	input2=32'b10111111001001100110011001100110; //.65
+	#5;
+	$display("\nSum: %16b - %16b = %16b",input1,input2,fpu_output);
+	$finish;
+end
+endmodule